Patent Application
20100073048
1. Field of the Invention
The invention relates to time constant calibration, and in particular to a method and apparatus for calibrating time constant of a phase locked loop and a system using the same.
2. Description of the Related Art
Phase locked loop (PLL) is a common form of frequency synthesizer used to generate frequency signals for use in an electronic or communication system. The PLL is generally designed to have a constant loop bandwidth, meeting requirements of noise suppression and lock time. The loop filter in the PLL generally comprises passive elements such as resistors and capacitors. The charge pump in the PLL generally provides a reference current determined by a current source and a reference resistor. However, variations inherent to resistors, capacitors or other elements in systems may lead to unacceptable variations in the loop bandwidth and gain, thus degrading noise suppression and lock time of the PLL.
There have been numerous approaches in conventional art to adjust the aforementioned undesired variations. Nonetheless, two of the prevailing calibration approaches are RC time constant calibration and RC time compensation calibration. The RC time constant calibration, for example proposed by Gehring (U.S. Pat. No. 6,842,710), performs RC time constant detection and RC time constant adjustment by binary/sequential search, thereby achieving frequency response calibration. However, according to Gehring's disclosure, a relatively longer time period is required to complete the calibration process due to a binary/sequential search mechanism. The RC time compensation calibration, for example proposed by Humphreys (U.S. Pat. No. 6,731,145), performs RC time detection and calculates RC time compensation by an operation or computation unit, thereby completing calibration process in one time (thus in a short period). Nonetheless, according to Humphreys' disclosure, the operation unit must also comprise a charging mechanism and a voltage storage mechanism, therefore resulting in relatively higher costs.
Accordingly, a novel approach is desired to adjust undesired variations inherent in resistors, capacitors or other elements in systems, which is faster and less costly than the conventional art.
An exemplary embodiment of a phase locked loop is disclosed, comprising a charge pump, a loop filter, a voltage comparator, a counting device, and a calibration device. The loop filter comprises a voltage storage device coupled to the charge pump for charging by the charge pump, wherein the voltage storage device comprises a variable impedance. The voltage comparator is coupled to a voltage reference and to the voltage storage device for comparing a voltage of the storage device and a voltage of the voltage reference. The counting device is coupled to the voltage comparator to measure the charge time required for the voltage of the voltage storage device to substantially equal to the voltage of the voltage reference. The calibration device adjusts the variable impedance to calibrate the time measured by the counting device to a desired time.
An exemplary embodiment of a method for calibrating a time constant for an integrated circuit or an electronic system is also disclosed, wherein the integrated circuit or the electronic system comprises a phase locked loop having a charge pump and a loop filter. The calibrating method comprises the steps of: charging a voltage storage device of the loop filter by a charge current from the charge pump; measuring a time required for a voltage of the voltage storage device to match a voltage of a voltage reference, wherein the charge time is dependent on an impedance of the loop filter; and adjusting the impedance of the loop filter to make the charge time substantially equal to a desired time constant value. It is noted the calibrating method further configuring a second circuit (excluding the phase locked loop) on the integrated circuit to have the desired constant value.
A detailed description is given in the following embodiments with reference to the accompanying drawings.
The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
The phase locked loop 100 further comprises a calibration block 106 for carrying out calibration in conjunction with the charge pump 102 and the loop filter 103. The calibration block 106 comprises: a voltage comparator 106a coupled to a voltage reference 106b and to the voltage storage device (not shown in
The loop filter 103 comprises a voltage storage device 103a which has a variable impedance. In this exemplary implementation, the voltage storage device 103a (or the variable impedance) comprises a plurality of passive elements, such as capacitors C1˜C3 and resistors R2˜R3, but it is not limited thereto. The impedances of the resistors R2˜R3 and the capacitors C1˜C3 are adjustable, and thus the voltage storage device 103a equivalently comprises the variable impedance. Also the loop filter may comprise the switch SW3 for selectively connecting the capacitor C1 and the group of the capacitors C1˜C2 and resistors R1˜R2.
Operation of the phase locked loop 100 in the calibration mode will be described in detail with reference to
The calibration logic 106e calculates a compensation time Tcom according to the desired time Td and the measured charge time Tch, and selectively adjusts impedances of the capacitors C1˜C3 and resistors R2˜R3 for compensating the measured charge time Tch to the desired time Td. The calibration logic 106e may comprise a mapping logic (not shown in
When the phase lock loop 100 operates in the frequency locking mode, the charge controller 102a controls the switches SW1 and SW2 for charging and discharging the loop filter 103 according to the phase difference signals Up and Dn. In addition, the switch SW3 closes such that the voltage storage device 103a obtains a required RC time constant responsive to the desired time Td, thereby generating the control signal Vt for the VCO 104 to generate the output carrier signal Fvco.
Another exemplary embodiment of the invention provides a method for calibrating a time constant for an electronic system or an integrated circuit which comprises a phase locked loop. Conceptually, the calibrating method comprises the steps of: charging a voltage storage device of a loop filter of the phase locked loop by a charge current from the charge pump of the phase locked loop; measuring a time required for a voltage of the voltage storage device to match a voltage of a voltage reference, wherein the charge time is dependent on an impedance of the loop filter; adjusting the impedance of the loop filter to make the charge time substantially equal to a desired time constant value. If other circuit portions (excluding the phase locked loop), in the electronic system or integrated circuit, operate based on timing signals correlated to the desired time constant value, the method for calibrating a time constant for an electronic system or an integrated circuit may further comprise the step of: configuring the other circuit portions to have the desired constant value characterized by the desired time constant.
The method for calibrating time constant in an electronic system or integrated circuit begins by opening the loop filter (103) output and charge pump (102) input, in step S1. For example, the calibration controller 106d opens switches SW3 to open the loop filter output, and controls the charge controller 102a to not receive the phase difference signals Up and Dn. Secondly, the voltage of the loop filter 103 is initialized (or discharged) to ground, in step S2. For example, the calibration controller 106d closes SW2 such that the voltage Vf of the capacitor C1 (or the voltage storage device 103a) is discharged to ground. Then, the charge pump 102 begins to charge the voltage Vf of the capacitor C1, and the counter 106c begins counting the charge time of the capacitor C1, in step S3. Next, the charge time for the voltage Vf of the capacitor C1 to reach the voltage Vref of the voltage reference 106b is recorded, in step S4. In step S5, it is determined whether the recorded charge time is equal to a desired time (or a desired time constant value). If the recorded time is not equal to the desired time, a compensation time is calculated, in step S6. Note that the steps S5, S6 and S7 can be performed by the calibration logic 106e. Subsequently, the impedance of the loop filter 103 is adjusted to calibrate the charge time to the desired time, in step S7. For example, adjusting impedance may be performed by tuning and combining the capacitors and resistors by control of the adjusting signals Rn and Cn and connection of the switch SW3, as described in
The method described in
In step S5 of
According to the disclosure of the invention, time constant calibration is performed without a binary/sequential search mechanism, thereby achieving faster calibration than the conventional art. Also, the disclosure of the invention directly uses a charge pump and a loop filter in the phase locked loop for calibration, without an additional charge mechanism and voltage storage mechanism as required in the conventional art, thereby reducing the costs for calibration.
While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
