Phase-locked loop for maintaining system synchronization through packet dropout

Abstract

A phase-locked loop for maintaining system synchronization of a receiver with a transmitter through packet dropout. A clock signal is generated by an oscillator and the interval between the neighboring pieces of incoming system timing information is determined by a first packet counter. A second packet counter determines the interval between neighboring timing signals generated by the first packet counter. Two count values of the system timing information are retained by a delay buffer. In accordance with a value of comparison which is obtained by a difference circuit from the difference between the two count values and is larger or smaller than an error expected on system synchronization, the counter value is corrected by an overflow corrector. A cumulative offset of the clock position is corrected by a phase difference detector. The corrected offset is integrated by an integrator only at a timing of the system timing information incoming.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The objects and features of the present invention will become more apparent from consideration of the following detailed description taken in conjunction with the accompanying drawings in which:

FIG. 1 is a schematic block diagram showing an embodiment of a phase-locked loop for maintaining system synchronization through packet dropout; and

FIG. 2 is a timing chart useful for understanding the operation of restoring system synchronization in the illustrative embodiment shown in FIG. 1.

Claims

1. A phase-locked loop for maintaining system synchronization between a transmitter and a receiver in a wireless communications system of packet transmission, said phase-locked loop comprising: an oscillator having an oscillation frequency controlled by a control signal for generating a clock for receiver system operation;a first counter operative directly in response to the clock for receiver system operation for autonomously counting the clock recursively at a period of incoming system timing information estimated to generate a first count value every period of the incoming system timing information;a second counter for counting a circuit clock of the receiver distinct from the clock for system operation to generate a second count value, the second count value being reset in response to the first count value;a holding circuit for holding the second count values corresponding to at least two packet intervals and detecting the system timing information transmitted from the transmitter;a difference circuit for comparing a temporally previous second count value held by said holding circuit with a temporally posterior second count value;an adder/subtractor for subtracting from or adding to an output of said difference circuit a value equivalent to an estimated period of incoming system timing information which is estimated with the circuit clock taken into account if the output of said difference circuit is, respectively, larger or smaller than a value expected with the system synchronization taken into account;a phase difference detector for changing the value obtained by said adder/subtractor to zero to output the resulting zero if the value obtained by said adder/subtractor is larger than a reference value expected with the system synchronization taken into account, and otherwise directly outputting the value obtained by said adder/subtractor; andan integrator for integrating an output of said phase difference detector, on acquisition of the system timing information from the transmitter to apply a result of integration to said oscillator as the control signal,whereby the system synchronization of the receiver with the transmitter is substantially maintained through packet dropout.

2. A phase-locked loop for maintaining system synchronization between a transmitter and a receiver in a wireless communications system of packet transmission, said phase-locked loop comprising: a phase difference detector for calculating a time difference between previous receiving timing and current receiving timing;an integrator for integrating the time difference if the current receiving timing is correctly received; andan oscillator operative in response to on an output of said integrator for adjusting a clock signal frequency to output an adjusted clock signal,whereby the system synchronization of the receiver with the transmitter is substantially maintained through packet dropout.