In certain embodiments, an apparatus may comprise a data channel including a clock synchronization module (CSM) having a first clock circuit, a second clock circuit, a first digital divider circuit, a second digital divider circuit, and a phase lock loop. The first clock circuit may be configured to produce a first clock signal having a first frequency, and the second clock circuit may be configured to produce a second clock signal having a second frequency different from the first frequency. The first digital divider circuit may be configured to downsample the first clock signal to produce a first downsampled clock signal having a third frequency, and the second digital divider circuit may be configured to downsample the second clock signal to produce a second downsampled clock signal having the third frequency. The phase lock loop may be configured to synchronize phases of the first downsampled clock signal and the second downsampled clock signal by adjusting a phase of the second clock signal via the second clock circuit based on a phase error between the first downsampled clock signal and the second downsampled clock signal. The data channel may be configured to perform data access to a memory after synchronization using the first clock signal and the second clock signal.
In certain embodiments, an apparatus may comprise a data channel including a clock synchronization module (CSM) having a first digital divider circuit, a second digital divider circuit, and a phase lock loop. The first digital divider circuit may be configured to downsample a first clock signal having a first frequency to produce a first downsampled clock signal having a third frequency, and the second digital divider circuit may be configured to downsample a second clock signal having a second frequency to produce a second downsampled clock signal having the third frequency. The phase lock loop may be configured to synchronize phases of the first downsampled clock signal and the second downsampled clock signal by adjusting a phase of the second clock signal based on a phase error between the first downsampled clock signal and the second downsampled clock signal. The data channel may be configured to perform data access to a memory after synchronization using the first clock signal and the second clock signal.
In certain embodiments, a method may comprise downsampling a first clock signal having a first frequency via a first digital divider circuit to produce a first downsampled clock signal having a third frequency, and downsampling a second clock signal having a second frequency via a second digital divider circuit to produce a second downsampled clock signal having the third frequency. The method may comprise synchronizing phases of the first downsampled clock signal and the second downsampled clock signal via a phase lock loop circuit by adjusting a phase of the second clock signal based on a phase error between the first downsampled clock signal and the second downsampled clock signal. The method may comprise performing data access to a memory after synchronization using the first clock signal and the second clock signal.
In the following detailed description of certain embodiments, reference is made to the accompanying drawings which form a part hereof, and in which are shown by way of illustration of example embodiments. It is also to be understood that features of the embodiments and examples herein can be combined, exchanged, or removed, other embodiments may be utilized or created, and structural changes may be made without departing from the scope of the present disclosure.
In accordance with various embodiments, the methods and functions described herein may be implemented as one or more software programs running on a computer processor or controller. Dedicated hardware implementations including, but not limited to, application specific integrated circuits, programmable logic arrays, and other hardware devices can likewise be constructed to implement the methods and functions described herein. Methods and functions may be performed by modules, which may include one or more physical components of a computing device (e.g., logic, circuits, processors, etc.) configured to perform a particular task or job, or may include instructions that, when executed, can cause a processor to perform a particular task or job, or any combination thereof. Further, the methods described herein may be implemented as a computer readable storage medium or memory device including instructions that, when executed, cause a processor to perform the methods.
The DSD 104 may include a memory 106 and a read/write (R/W) channel 108. The memory 106 may include a nonvolatile data storage medium, which may include a magnetic storage medium such as a hard disc, other nonvolatile storage mediums, or any combination thereof. The R/W channel 108 may comprise one or more circuits or processors configured to process signals for recording to or reading from the memory 106. During operation, the DSD 104 may receive a data access request, such as a read or write request, from the host device 102. In response, the DSD 104 may perform data access operations on the memory 106 via the R/W channel 108 based on the request.
The DSD 104 may retrieve data from the memory 106 as one or more analog signals, e.g. using one or more receivers, such as reader elements or heads, to detect magnetic signals from tracks of a disc. The R/W channel 108 may perform processing on the analog signals to detect a digital bit sequence representing stored data. Similarly, the DSD 104 may store data to the memory 106 by using reader elements or heads to generate magnetic fields and set localized polarity of the disc surface, which in turn can be read as analog signals. The R/W channel 108 may convert a digital bit sequence into an analog magnetic signal for storing data to the disc.
A DSD 104 may have multiple clock signal generators to control the timing of operations and signals within the device. For example, the DSD 104 may have a read clock to control a read head, and a write clock to control a write head, and each clock may have a different frequency (e.g. how quickly it produces timing pulses). There are various reasons that it may be advantageous to synchronize clocks having different frequencies (e.g. via phase-locking the clocks), so that there is a known fixed relationship between the clocks. Accordingly, the DSD 104 may include a clock synchronization module (CSM) 110 to perform the operations described herein to synchronize two or more clocks having different frequencies. The CSM 110 may be located within the R/W channel 108, separate from the R/W channel, or partially within the R/W channel and partially distributed elsewhere. In this manner, the functioning of the DSD 104 may be improved by providing the ability to accurately and precisely synchronize multiple clocks having different frequencies, allowing for the performance of synchronized operations that include the multiple different clocks. For example, applications that rely on read and write heads being carefully synchronized may benefit from the described methodology. One such application may be the performance of self-servo writing (SSW), in which the DSD 104 uses its heads to write servo data to the disc surface which is then used for head positioning during normal data input/output (I/O) read and write operations. An example depiction of servo data and an associated servo writing process are described in regard to
Data may be stored to a disc memory 200 along very narrow concentric bands called tracks. There may be hundreds of thousands of tracks on a single disc surface, and so the DSD may need to be extremely precise in positioning the heads over a correct track when performing reading and writing operations. In order to know where the heads are currently located (e.g. over which track), the DSD may read servo positioning information stored to the disc.
As stated, the disc 200 may be configured to record data (e.g. host or user data) to a multitude of concentric circular data tracks (or just “tracks”) arranged from an outer diameter 202 to an inner diameter 204 of the disc 200. The disc 200 may spin about a central spindle located at the inner diameter 204. A read or write head may be positioned above the surface of the disc 200, and can read or write data to the tracks while the disc 200 spins below the head. A hard disc surface may include servo signals written during manufacture procedures, which the DSD may use to determine a head's positioning relative to tracks and the disc. The head and channel can look for these servo signals to locate the data tracks, where the user data will be read or written. Each track may include portions devoted to user data and portions reserved for the servo signals. During a manufacturing process for the DSD, the servo signals can be written to a disk through a multi-disc writer (MDW, a machine that can write dedicated patterns, such as servo patterns, or spiral signals), or they can be written through a procedure called self-servo write (SSW).
As explained herein, the storage and subsequent retrieval of data from a hard disc drive may be made possible by the demodulation of servo signals from a servo pattern, which may be written to the surface of each disc 200 during manufacturing. As shown in
The data contained within each servo sector 206 may specify its physical radial and tangential locations. As the read head passes over each servo sector 206, the servo sector's information may be demodulated such that the position of the read head is always known to the hard-disk controller (the position of the write-head may also be inferred). Furthermore, the spacing between servo sectors 206 can be utilized to modulate the frequency of clocks used for all write and read operations such that the frequencies remain consistent relative to the rotational velocity of the disc 200. It is this processing of the servo pattern which allows for consistent writes and reliable reads from a hard disc drive. Although a simplified example is provided in
The writing procedure of the servo pattern can be performed by a dedicated machine known as a servowriter, disc writer, STW (servo track writer), MDW, or MDSW (multi-disk servo writer), where the servo patterns are written to the discs before the discs are assembled into the drive. A servowriter may be a very precise and expensive piece of equipment, and therefore it may be advantageous to use as efficiently as possible to improve manufacturing throughput and reduce overhead. Using a servowriter to write every servo wedge 208 of every disc 200 may be slow and inefficient.
Another way to write the servo pattern is called self-servo write (SSW). A drive employing SSW techniques may utilize its embedded controller and its own write heads to write the servo wedges and associated servo sectors 206 to the surface(s) of its constituent disc(s), thus saving cost and time. In order to accurately position the servo patterns on the disc 200, the controller may determine the position of the heads by locking on to a pre-written (e.g. written using a STW) or self-written pattern on the disc 200 called spirals 212. The spirals 212 may be written to include a sync mark data pattern that can be used to determine when a spiral is encountered by a read head. Writing the spirals 212 may include moving a write head in a controlled manner (e.g. at a constant velocity) from the outer diameter 202 to the inner diameter 204 (or vice versa) as the disc 200 is spun to create the spiral pattern 212. Although a single spiral pattern 212 is depicted in
The DSD may read the spirals 212 with the read head and lock the read clock based on the spirals 212. However, the servo patterns will be written with a write head and an associated write clock, and the frequency of the read clock and the write clock could be very different. In order to achieve radial coherence of the servo patterns, the radial location where servo signals are written to the disk for each track should be consistent. In other words, the write gate position should have a fixed relationship to the place where the spiral signals 212 are. This relationship should also be repeatable if the SSW procedure is restarted. Therefore, the write clock should be synchronized to the read clock such that the clock cycles have a known relationship.
One approach may be to set the frequency of the read and write clocks to be the same for SSW, or to have a simple fixed relationship such as 2× or 4×, such that one clock source can be used for both reading and writing after the application some digital dividers, sometimes called frequency dividers. A digital divider may be a circuit that receives an input signal of a frequency fin and generates an output signal of frequency fout, where fout=fin/n, where “n” may be an integer. However, with the servo frequency going up and zoned servo techniques being used, it may be difficult to maintain such a simple relationship between the read and write clocks. The servo frequency may refer to the clock frequency of the servo pattern, and may determine the physical bit width on the disc. The higher the frequency, the tighter the bits may be written together, assuming the same rotation speed of the disc.
The methodology proposed herein can work for a much larger range of read and write clock frequency relationships, and can support finer granularity. The methodology can include providing clocks that both have an integer number of clock cycles in a selected period; e.g. the clock cycle ratio of the two clocks is a rational number. In SSW there should be an integer number of clock cycles in a single disc revolution for both servo and spiral signals, and so the clocks may be configured for an integer number of clock cycles per revolution in any event.
The proposed methodology could even allow for synchronizing multiple write clocks running at different frequencies to one read clock, via a duplication of the described circuits. This technique can make it possible to write multiple disc surfaces with servo patterns simultaneously or in a staggered fashion, thus greatly reducing servo writing time. An example embodiment of a system configured for synchronizing clocks is described in regard to
The system 300 may include a reference clock signal Fref 302, which may be provided to a first phase-locked loop (PLL), PLL1304, and a second PLL, PLL2306. Both PLLs can be adjusted by the same clock frequency control signal 1+α from a disc-locked clock (DLC). The DLC can be a control algorithm, circuit, or firmware which locks clocks to a written pattern on the disc (e.g. servo signal patterns, or in the case of SSW, the spiral pattern). In normal read and write operations, the servo signal can be read to obtain sync-mark and other track information. The sync-mark position can be compared for each servo sector. If the distance between two adjacent servo sectors is different from an expected number of clock cycles, a timing error can be generated indicating the clock is running faster or slower than needed to match the disc read back signal. This error can be passed to an algorithm to control the alpha value. In turn, changing the alpha value can change the clock frequencies such that the clock cycles between two servo sectors are changed. This feed-back loop (DLC, or sometimes called a disc lock loop DLL) may converge when the average clock cycles between servo sectors are as expected.
Accordingly, the 1+α clock frequency control signal can provide the same alpha value to both PLLs, and can modulate the frequency of the PLLs by the same percentage. For example, if a disc is spinning a little bit faster than expected, with the alpha value fed back from a servo channel the data read and write clocks and the servo clock can be sped up with the same percentage to catch up with the disc.
The clock frequency control signal applied to each PLL may be modified by a multiplier value “D”. PLL1304 may be modified by a first multiplier value D1308 at a first multiplier node 310. Similarly, PLL2306 may be modified by a second multiplier value D2312 at a second multiplier node 314. The signals output from PLL1304 and PLL2306 may be the clock signals for a first clock and a second clock, respectively. Each PLL may be connected to a digital phase converter (DPC), with PLL1304 connected to DPC1316, and PLL2306 connected to DPC2318. The digital phase converters can adjust the phase of the respective clock signals with a digital control. For example, a DPC can have an input of 6-bit unsigned number to indicate the clock's phase, with granularity of 1/26T (with “T” being a single clock cycle). The DPCs may output phase adjusted clock signals, with DPC1316 outputting the signal clk1 for the first clock, and with DPC2318 outputting clk2 for the second clock. As stated herein, clk1 and clk2 may be clock signals with different frequencies. As the signals clk1 and clk2 are produced by PLLs and modified by DPCs, the combination of PLL1304 and DPC1316 may be referred to as a first clock, clock circuit, or clock generation circuit, and the combination of PLL2306 and PDC 318 may be referred to as a second clock, clock circuit, or clock generation circuit. Although clk1 and clk2 derive from the same reference clock signal Fref 302, the relative phases of the two clocks may still be uncertain.
Each clock may be connected to a modulo-counter (or, e.g., a pair or set of modulo-counters), with clock 1 (clk1) connected to PLL1 counter 320, and clock 2 (clk2) connected to PLL2 counter 322. A modulo-counter may count from an initial value to an end value and then reset to the initial value to continue counting. For example, assume that there are a total of 1000 read clock cycles in a single disc revolution. A modulo-counter can be set such that it counts up by one for each clock cycle, from 0 to 999, and then resets to 0 again on the next clock cycle. Another configuration may be to have a pair of counters for each clock. A first modulo-counter of the pair may count the cycles from servo wedge to servo wedge, while the other counter may count the number of wedges. For example, if a disc has 8 wedges and each wedge corresponds to 125 read clock cycles, the cycle counter may count from 0 to 124, while the wedge counter may count from 0 to 7. For the convenience of explanation, the provided examples will include only one counter for each clock. In an embodiment directed to SSW, the modulo-counters may be used to generate a “timestamp” when spirals are encountered by a read head, which timestamps can be used to determine a location of the heads on the disc and where spirals will be encountered on each revolution.
In the scenario of SSW, clock 1 may be the reading clock and clock 2 may be the writing clock. As the reading clock may be used to identify the location of the spiral signals, it may be referred to as the spiral clock. Likewise, the writing clock may be used to write the servo patterns to the disc, and may therefore be referred to as the servo clock.
When the system 300 is reading the signal (e.g. the spiral pattern or servo data) on the disk, the read clock can be locked to the media through disc lock control based on the timestamps given by the signal and PLL1 counter 320. The disc lock control can be accomplished by firmware utilizing the timestamp information provided by the hardware read channel from the PLL1 counter 320. The system 300 may associate a particular timestamp value with the location of a spiral pattern in order to establish the lock. For example, the PLL1 counter 320 may provide a counter output to a spiral read module 321, which may use signal patterns read from the disc to process and detect signal patterns. When the spiral read module 321 detects a sync mark from a spiral pattern, it may record the corresponding counter value or timestamp from the PLL1 counter 320 to one or more registers 323. The system 300 firmware can read the values from the registers 323 to know where spiral patterns are located. When the read clock is locked to the disc, each read counter value may correspond to one unique position on the track within one revolution. The disc lock procedure may be repeatable, so that a particular counter value can always map to the same position on the drive even after resets. The system may have various ways to distinguish different spirals along the track so that the same position can be located again. For example, one of the spirals can have a different sync mark than the rest, so that when this particular sync mark is detected, the system knows that this particular spiral was met and can use it as a reference point.
When writing servo patterns to the disc, the write counter (PLL2 counter 322) can be used to give the writing location over one revolution. In order to be able to write at exactly the same radial location for adjacent tracks (e.g. to achieve the radially-oriented “spoke” arrangement of the servo wedges across the disc surface, called radial coherence), the PLL2 counter 322 values can be used to identify a specific position uniquely on the disk in one revolution. However, only the read clock may be locked to the disc via the read counter 320 and spiral pattern locations, and the read counter 320 and the write counter 322 may be in different clock domains. The write circuit may have to use the read counter 322, or else there will be uncertainty in the system 300 operation. Therefore, identifying unique points along a track using the PLL2 write counter 322 can be accomplished by fixing the phase relationship between the write counter 322 and the read counter 320, thereby synchronizing the write clock to the read clock. An example of a fixed phase relationship is depicted in
Clock 1 and clock 2 of
Returning to
The two clocks may operate at two different frequencies. Assume the output frequency “F” of each PLL can be calculated by F=Fref×D, where D is a fractional number setting applied via registers (e.g. via D1308 and D2312). There might be DLC control modifying the fractional D values (e.g. the multiplication of 1+α and the multipliers D at the multiplier nodes 310 and 314) going into the PLLs as well. In such a scenario, the actual output frequency of the PLL can be written as F=Fref×D×(1+α), where D is the register setting to generate the nominal frequency.
Assume that the ratio of the two clock frequencies is M1/M2. In other words, when clock 1 is downsampled by M1326 (e.g. the frequency of clock 1 is divided by a value M1) and clock 2 is downsampled by M2328, the two downsampled clocks (clock signals clk1_d and clk2_d) have the same frequency. For example, if clock 1 completes 200 cycles per disc revolution (such that PLL1 counter 320 counts from 0 to 199), and clock 2 completes 292 cycles per disc revolution (such that PLL2 counter 322 counts from 0 to 291), the values of M1 and M2 may be 50 and 73. In this example, 200/50=4, and 292/73=4. In system 300, clock signals from clk1 may be passed to a digital divider M1326. The digital dividers may function like counters that increment by 1 for each pulse received from the input clock signal. The M1 divider 326 may therefore count from 0 to 49 and then reset to 0. For every 50 clk1 signals received at the divider M1326, one downsampled clk1_d signal may be generated. In other words, every time the divider M1 rolls over from 49 to 0, it may generate a pulse. Similarly, clk2 may be passed to digital divider M2328, which may produce one downsampled clk2_d signal for every 73 clk2 signals received. In this manner, the two downsampled signals will share the same frequency, even if the phase of the clk1_d and clk2_d clock signals is not yet aligned.
Therefore, a phase lock loop 324 can be used to synchronize and lock the edges of the two downsampled clocks. In the example system 300, the two downsampled clocks may be passed to a phase error detector (PED) 330. The PED 330 can generate and output a coarse phase error between the two signals. The phase error may, for example, be a +1 or −1 value to indicate the relationship of the clock edges of the input clocks. This phase error may be provided to a loop filter 334, which may generate a phase adjustment to compensate for the phase error. The phase adjustment may be provided to the DPC2318 of clock 2, in order to adjust clock 2's phase toward alignment with clock 1. Since clock 1 (e.g., the read clock in the example SSW application) may be regarded as a reference clock whose phase is not adjusted, clock 2 may be a slaving clock to clock 1 through this phase locking of the downsampled clocks.
The phase error generated by the PED 330 may also be provided to a phase lock detector 332. The phase lock detector 332 can be used to indicate whether the two downsampled clocks (clk1_d and clk2_d) are locked or not. For example, the phase lock detector 332 may determine that the clocks are locked if the sum or average of a selected number of the phase error values from the PED 330 is lower than a threshold value. A long sequence of +1 or −1 error values may indicate that there is ongoing phase adjustment between the clocks, while a sequence of variable +1 and −1 values may total or average out to approximately 0, indicating the clocks are locked. When the phase lock detector 332 determines that the two downsampled clocks are phase locked, it may generate a lock signal. Once the downsampled clock signals share the same frequency and phase, the counters PLL1 counter 320 and PLL2 counter 322 may be partially aligned, in as much as they may share a fixed relationship due to the locked downsampled clocks. However, it may not be known how the PLL counters are aligned, and the relationship may not be fixed if the SSW operation is restarted. For example, the 0 value for PLL1 counter 320 may be aligned with a 5 on the PLL2 counter 322 during a first operation, and after a reset the 0 value may be aligned with a 17 value, such that there isn't a known correlation between counter values and disc positions for both clocks. So in order to guarantee that every time the two PLL counters will have a known fixed relationship after the synchronization procedure, the PLL counters may be aligned to known reset positions, and therefore fixed disc positions. Accordingly, once the downsampled clocks are locked, the PLL counters may be further aligned, which may provide the ability to determine specific head locations over the disc for precise servo data writing. An overview of the process to synchronize clocks having different frequencies is described in regard to
Synchronization of two clocks may include phase-adjusting the slave clock to match the reference clock so that their downsampled clocks share the same frequency and phase alignment. The clock counter for the slave clock may then be reset based on the reference clock counter so that both clock counters are aligned, such that clock counter values from either counter may correspond to a specific location on a disc surface.
The method 500 may include aligning one pulse of the downsampled clock signals for a first clock (clock 1) and a second clock (clock 2) to a particular value of the clock 1 modulo counter (e.g. PLL1 counter 320 of
The method 500 may include adjusting the phase of the downsampled clock 2 to match the phase of the downsampled clock 1, at 504. This can be achieved via a phase lock loop, by providing the output of the digital dividers (e.g. the clk1_d and clk2_d signals) to a phase error detector, and using a loop filter to adjust the phase of the clock 2 signal until the clk2_d signal aligns in phase with the clk1_d signal.
Once the downsampled clocks are phase aligned, the method 500 may include aligning the clock 2 counter (e.g. PLL2 counter 322 of
At 508, the method 500 may include operating the system based on the synchronized clock 1 and clock 2. Operations may include data access operations such as reading or writing data, including performing a self servo writing operation. An example illustration of the steps of method 500 are depicted in
A clock 1 counter 602 may represent a modulo counter, such as PLL1 counter 320 of
In STAGE 1, the clock 1 counter 602 and the clock 2 counter 604 may be free-running and not synchronized at all. Each counter may be configured to count to a number corresponding to a number of corresponding clock cycles within a single disc revolution, but they may not be aligned to reset at the same point in time (and therefore not reset at the same position of the disc). Similarly, the clock 1 divider 606 and the clock 2 divider 608 have been programmed to the correct divider values (e.g. to reset at M1 and M2 received clock signals, respectively), but the reset points are not set to correspond to any particular clock 1 counter 602 or clock 2 counter 604 values. Further, the phase lock circuit may not be turned on and so the downsampled clocks are not phase aligned.
A first step of synchronization may include aligning the downsampled clocks, clock1_d 610 and clock2_d 612, to a particular position on the disc, by aligning the downsampled clocks to a particular value of the clock 1 counter 602. This particular value may be the ‘counter 1 align value’ 614, which may be where clock 1 counter 602 resets to 0 (e.g. as an example shown in
The clock 1 counter 706 and the M1 divider counter 712 may increment at each rising edge of the clock 1 signal 708. A clk1_d 714 downsampled clock pulse may be generated each time the M1 divider counter 712 resets to 0. Similarly, the M2 divider counter 718 may increment at each rising edge of a clock 2716, and a clk2_d 720 downsampled clock pulse may be generated each time the M2 divider counter 718 resets to 0.
To align clk1_d 714 to the clock 1 counter 706 align value (e.g. when the clock 1 counter 706 resets to zero), a synchronous reset to 1 on the M1 clock 1 divider counter 712 may be enabled when the clock 1 counter reaches the align value. That is, an internal reset signal 710 may be generated upon the clock 1708 pulse corresponding to the clock 1 counter 706 hits the align value of 0. Upon the next clock 1708 pulse after the reset signal 710 is generated, the M1 divider counter 712 may be reset to 1. In this manner, the timing of the M1 divider counter 712 reset point should correspond to future clock 1 counter 706 reset points. At the align value of the clock 1 counter (which is 0 in this case), there will be a clock pulse of the downsampled clock. For example, every time the clock 1 counter 706 counts to fifty (e.g. 0-49, 50-99, 100-149, 150-199) the M1 divider counter 712 will reset to 0. Although the example here has the reset signal 710 generated when the clock 1 counter 706 reaches the align value, alternate implementations are also possible. For example, the reset signal 710 could be generated when the clock 1 counter 706 reaches the align value −1, and the M1 divider counter 712 could be reset to 0 instead of 1.
For the clock 2 M2 divider 718, since the clock 2 domain 704 may be a different frequency domain than clock 1, the clock 2716 signal may be used to sample the reset signal 710 and reset the M2 divider 718 asynchronously with the M1 divider counter 712. The reset may not occur at the exact same time due to the different frequencies. On the next clock 2716 pulse after the reset signal 710 is generated, the M2 divider counter 718 may be reset to 1. Although both downsampled clocks may have the same frequency and may have both been reset based on the clock 1 counter 706, the difference in frequencies between clock 1708 and clock 2716 may result in a phase error 722 between the downsampled clock pulses. In other words, after STAGE 1 the downsampled clocks may have a different phase, but the same frequency.
Note that the example provided is just for illustration; in reality, hardware may require multiple clock 2716 cycles to finish the asynchronous reset of the M2 divider 718. In such a case, the phase error 722 between the clk2_d 714 and clk2_d 720 might be larger, but may still be compensated for later by running the phase lock loop.
Returning to
At the end of STAGE 2, the downsampled clocks may be phase locked with each other, and may be aligned to the clock 1 counter 602. In addition, clock 1 and clock 2 may be phase locked at particular positions where the downsampled clock pulses are. However, the clock 2 counter 604 may not be aligned to the clock 1 counter 602. Resetting the clock 2 counter 604 to align with the clock 1 counter 602 may enable the system to align a particular value for both counters to a particular position on the disc, so that the same position is achieved every time the system loses lock and must re-lock again. The align value positions for each counter is such a fixed position for resetting. Otherwise, while the clock 1 counter 602 may always correspond to the same disc position after lock is re-established, the clock 2 counter 604 may be at, e.g. value 1 for that position during one lock, and at value 3 for the same position during a subsequent lock, introducing uncertainty. In order to align the clock 2 counter 604 to the clock 1 counter 602 at the align values shown in
When the first downsampled clock clk1_d 814 and the second downsampled clock clk2_d 820 are phase locked, as of the end of STAGE 2 in
Once a logical AND of the reset pulse 824 and the clk2_d 820 pulse is detected, a reset signal may be generated upon the next rising edge of the clock 2816 signal. The clock 2 counter 822 may be set to 1 for the next cycle such that the zeros of the clock 1 counter 806 and clock 2 counter 822 are aligned. After this step, the synchronization procedure for clock 1808 and clock 2816 may be completed.
Returning to
The process of STAGES 1 to 3 can be performed using firmware, hardware, or any combination thereof. For example, after the firmware programs the align values (e.g. counter values “0”) of clock 1 counter 602 and clock 2 counter 604, STAGES 1 and 3 may be implemented by setting reset bits, while STAGE 2 may be implemented via setting an enable bit. For example, in STAGE 1 reset bits may be used to reset the clock 1 divider (M1) 606 and the clock 2 divider (M2) 608 in response to the clock 1 counter 602 reaching the align value. STAGE 2 may be accomplished by the firmware setting an enable bit to turn on the phase lock loop and phase lock the downsampled clk2_d 612 to the downsampled clk1_d 610. STAGE 3 may include using a reset bit to reset the clock 2 counter 604 to its align value when the downsampled clocks are phase locked and the clock 1 counter 602 reaches its align value. An interrupt can be provided once the downsampled clocks are phase locked, such that the firmware can move to STAGE 3.
The implementation may be modified from the examples provided in regard to
The system can be extended to include a third PLL3912 and a third DPC3914 to generate a third clock signal clk3, with a third modulo counter PLL3 counter 916. The third clock clk3 may have a different frequency than clk1 and clk2. Clk3 may be synchronized to clk1 by providing both signals to a second phase lock loop 918, and following the same methodology as described to synchronize clk2 to clk1. As clk1 is the reference clock in both instances and does not have its phase or PLL1 counter changed during the synchronization process, multiple clocks can be synchronized to clk1 in this manner.
In a SSW procedure, two writing channels (e.g. including PLL2906 and PLL3912) can be synchronized to one reading channel (e.g. including PPL1902) for example, such that servo patterns can be written on two disc surfaces at the same time (or staggered). A single spiral pattern on one disc surface can be read by the single read channel and used to record servo data on multiple disc surfaces. The two writing clocks can have totally different frequencies. In this way, the servo writing time can be substantially improved.
Turning now to
Method 1000 may include downsampling a first clock and a second clock having different frequencies to generate downsampled clocks having the same frequency, for example using digital dividers, at 1002. The downsampled clocks may be alilgned to a counter value for the first clock by resetting the downsampling divider counters based on a counter value for the first clock, at 1004. For example, when the counter for the first clock resets to 0, the divider counters for the downsampled signals may both be reset so that their 0 counter values will align with the first clock counter value of 0. In this manner, the downsampled clocks may have a same frequency and be aligned with the first clock counter, but may be offset in phase.
At 1006, the method 1000 may include adjusting the phase of the downsampled second clock to match, or “lock to”, the phase of the downsampled first clock using a phase lock loop. The phase lock loop may determine a phase error between the downsampled clock signals, and adjust the phase of the second clock based on the error until the phases of the downsampled clocks are aligned. A determination may be made whether a phase lock is detected between the downsampled clocks, at 1008. If not, the method 1000 may include continuing to adjust the phase of the second clock via the phase lock loop, at 1006.
When a phase lock is detected, at 1008, the method 1000 may include aligning a counter for the second clock with the counter for the first clock based on a reset pulse from the first clock counter, at 1010. For example, when the counter for the first clock resets to 0, a reset pulse may be generated. In response to the reset pulse, the counter for the second clock counter may be set to a value (e.g. the value “1”) so that the 0 values for both counters will be aligned.
A determination may be made whether there are more clocks to synchronize to the first clock, at 1012. If there are, a next clock may be selected as the “second clock”, at 1014, and the method may repeat at 1002. If there are no additional clocks to synchronize to the first clock, at 1012, the method 1000 may include writing servo data to discs using the one or more second clock(s) based on positioning information from the first clock, at 1016. An example data storage device incorporating a read/write (R/W) channel having a clock synchronization module (CSM) configured to perform the clock synchronization operations described herein is shown in
The DSD 1100 can communicate with a host device 1102 (such as the host system 102 shown in
The buffer 1112 can temporarily store data during read and write operations, and can include a command queue (CQ) 1113 where multiple pending operations can be temporarily stored pending execution. Commands arriving over the interface 1104 may automatically be received in the CQ 1113 or may be stored there by controller 1106, interface 1104, or another component.
The DSD 1100 can include a programmable controller 1106, which can include associated memory 1108 and processor 1110. The controller 1106 may control data access operations, such as reads and writes, to one or more disc memories 1109. The DSD 1100 may include an additional memory 1103 instead of or in addition to disc memory 1109. For example, additional memory 1103 can be a solid state memory, which can be either volatile memory such as DRAM or SRAM, or non-volatile memory, such as NAND Flash memory. The additional memory 1103 can function as a cache and store recently or frequently read or written data, or data likely to be read soon. Additional memory 1103 may also function as main storage instead of or in addition to disc(s) 1109. A DSD 1100 containing multiple types of nonvolatile storage mediums, such as a disc(s) 1109 and Flash 1103, may be referred to as a hybrid storage device.
The DSD 1100 can include a read-write (R/W) channel 1117, which can encode data during write operations and reconstruct user data retrieved from a memory, such as disc(s) 1109, during read operations. A preamplifier circuit (preamp) 1118 can apply write currents to the heads 1119 and provides pre-amplification of read-back signals. In some embodiments, the preamp 1118 and heads 1119 may be considered part of the R/W channel 1117. A servo control circuit 1120 may use servo data to provide the appropriate current to the coil 1124, sometimes called a voice coil motor (VCM), to position the heads 1119 over a desired area of the disc(s) 1109. The controller 1106 can communicate with a processor 1122 to move the heads 1119 to the desired locations on the disc(s) 1109 during execution of various pending I/O commands in the command queue 1113.
DSD 1100 may include one or more clock synchronization modules (CSMs) 1130, for example in the R/W channel 1117, distributed among multiple components, as one or more stand-alone circuits, or any combination thereof. The CSM 1130 may perform the methods and processes described herein to synchronize multiple clocks having different frequencies. For example, different heads 1119 may be controlled according to different clock frequencies. The CSM 1130 may downsample the clocks so that the downsampled clock signals share a same frequency, phase lock the downsampled clocks, and align the clock counters and digital dividers so that the clocks are fully synchronized. The synchronized clocks may be used to perform techniques such as self-servo writing of servo data to the disc(s) 1109 in a manner that allows for writing data to precise locations on a disc's surface even in the absence of pre-written servo data.
The illustrations of the embodiments described herein are intended to provide a general understanding of the structure of the various embodiments. The illustrations are not intended to serve as a complete description of all of the elements and features of apparatus and systems that utilize the structures or methods described herein. Many other embodiments may be apparent to those of skill in the art upon reviewing the disclosure. Other embodiments may be utilized and derived from the disclosure, such that structural and logical substitutions and changes may be made without departing from the scope of the disclosure. Moreover, although specific embodiments have been illustrated and described herein, it should be appreciated that any subsequent arrangement designed to achieve the same or similar purpose may be substituted for the specific embodiments shown.
This disclosure is intended to cover any and all subsequent adaptations or variations of various embodiments. Combinations of the above embodiments, and other embodiments not specifically described herein, will be apparent to those of skill in the art upon reviewing the description. Additionally, the illustrations are merely representational and may not be drawn to scale. Certain proportions within the illustrations may be exaggerated, while other proportions may be reduced. Accordingly, the disclosure and the figures are to be regarded as illustrative and not restrictive.
The present application is a non-provisional application of and claims priority to U.S. provisional patent application, Application No. 62/522,248, filed Jun. 20, 2017, entitled “MISO Systems and Methods”, the contents of which are hereby incorporated by reference in their entirety.
Number | Name | Date | Kind |
---|---|---|---|
5321564 | Takahashi | Jun 1994 | A |
5461644 | Bermans et al. | Oct 1995 | A |
5543978 | Park | Aug 1996 | A |
5621769 | Wan et al. | Apr 1997 | A |
5654765 | Kim | Aug 1997 | A |
5742532 | Duyne et al. | Apr 1998 | A |
5862192 | Huszar et al. | Jan 1999 | A |
5970093 | Lantremange | Oct 1999 | A |
6111712 | Vishakhadatta | Aug 2000 | A |
6157510 | Schreck et al. | Dec 2000 | A |
6181213 | Chang | Jan 2001 | B1 |
6222592 | Patel | Apr 2001 | B1 |
6320920 | Beyke | Nov 2001 | B1 |
6377552 | Moran et al. | Apr 2002 | B1 |
6396887 | Ware | May 2002 | B1 |
6438185 | Huttunen | Aug 2002 | B1 |
6505222 | Davis et al. | Jan 2003 | B1 |
6519107 | Ehrlich | Feb 2003 | B1 |
6549587 | Li | Apr 2003 | B1 |
6580676 | Yanagisawa et al. | Jun 2003 | B1 |
6581182 | Lee | Jun 2003 | B1 |
6633894 | Cole | Oct 2003 | B1 |
6665308 | Rakib et al. | Dec 2003 | B1 |
6670901 | Brueske et al. | Dec 2003 | B2 |
6687073 | Kupferman | Feb 2004 | B1 |
6697891 | Emberty et al. | Feb 2004 | B2 |
6707772 | Marrec et al. | Mar 2004 | B1 |
6738205 | Moran et al. | May 2004 | B1 |
6738215 | Yatsu | May 2004 | B2 |
6950258 | Takaishi | Sep 2005 | B2 |
6993291 | Parssinen et al. | Jan 2006 | B2 |
7046701 | Mohseni et al. | May 2006 | B2 |
7085330 | Shirali | Aug 2006 | B1 |
7133233 | Ray et al. | Nov 2006 | B1 |
7133239 | Hartman | Nov 2006 | B1 |
7245448 | Urata | Jul 2007 | B2 |
7298573 | Kitamura | Nov 2007 | B2 |
7324437 | Czylwik et al. | Jan 2008 | B1 |
7362432 | Roth | Apr 2008 | B2 |
7440208 | McEwen et al. | Oct 2008 | B1 |
7929238 | Vasquez | Apr 2011 | B1 |
7940667 | Coady | May 2011 | B1 |
7948703 | Yang | May 2011 | B1 |
8027117 | Sutardja | Sep 2011 | B1 |
8139301 | Li et al. | Mar 2012 | B1 |
8160181 | Song et al. | Apr 2012 | B1 |
8172755 | Song et al. | May 2012 | B2 |
8296637 | Varnica et al. | Oct 2012 | B1 |
8400726 | Wu et al. | Mar 2013 | B1 |
8456977 | Honma | Jun 2013 | B2 |
8479086 | Xia et al. | Jul 2013 | B2 |
8508879 | Zou | Aug 2013 | B1 |
8514506 | Li et al. | Aug 2013 | B1 |
8539328 | Jin et al. | Sep 2013 | B2 |
8542766 | Chekhovstov et al. | Sep 2013 | B2 |
8543894 | Varnica et al. | Sep 2013 | B1 |
8713413 | Bellorado et al. | Apr 2014 | B1 |
8724245 | Smith et al. | May 2014 | B1 |
8755139 | Zou et al. | Jun 2014 | B1 |
8760794 | Coker et al. | Jun 2014 | B1 |
8767341 | Coker et al. | Jul 2014 | B1 |
8780477 | Guo et al. | Jul 2014 | B1 |
8837068 | Liao et al. | Sep 2014 | B1 |
8861111 | Liao et al. | Oct 2014 | B1 |
8861112 | Pan et al. | Oct 2014 | B1 |
8887033 | Varnica et al. | Nov 2014 | B1 |
8953276 | Pokharel et al. | Feb 2015 | B1 |
9007707 | Lu et al. | Apr 2015 | B1 |
9019642 | Xia et al. | Apr 2015 | B1 |
9025269 | Wong et al. | May 2015 | B1 |
9064537 | Nie | Jun 2015 | B1 |
9082418 | Ong et al. | Jul 2015 | B2 |
9093115 | Fung et al. | Jul 2015 | B1 |
9099132 | Grundvig et al. | Aug 2015 | B1 |
9129650 | Mathew et al. | Sep 2015 | B2 |
9147416 | Grundvig et al. | Sep 2015 | B2 |
9189315 | Varnica et al. | Nov 2015 | B1 |
9196298 | Zhang et al. | Nov 2015 | B1 |
9245578 | Wang et al. | Jan 2016 | B1 |
9245579 | Song et al. | Jan 2016 | B2 |
9245580 | Lu et al. | Jan 2016 | B1 |
9246668 | Yu et al. | Jan 2016 | B1 |
9257135 | Ong et al. | Feb 2016 | B2 |
9257145 | Soderbloom et al. | Feb 2016 | B1 |
9286915 | Dziak et al. | Mar 2016 | B1 |
9311937 | Zou et al. | Apr 2016 | B2 |
9311959 | Fan et al. | Apr 2016 | B1 |
9385757 | Nangare | Jul 2016 | B1 |
9401161 | Jury | Jul 2016 | B1 |
9424878 | Dziak et al. | Aug 2016 | B1 |
9431052 | Oberg et al. | Aug 2016 | B2 |
9489976 | Jury et al. | Nov 2016 | B2 |
9508369 | Chu et al. | Nov 2016 | B2 |
9536563 | Liu et al. | Jan 2017 | B1 |
9542972 | Nayak et al. | Jan 2017 | B1 |
9564157 | Trantham | Feb 2017 | B1 |
9590803 | Derras et al. | Mar 2017 | B2 |
9645763 | Sankaranarayanan et al. | May 2017 | B2 |
9672850 | Grundvig et al. | Jun 2017 | B2 |
9728221 | Oberg et al. | Aug 2017 | B2 |
9947362 | Venkataramani et al. | Apr 2018 | B1 |
9998136 | Wu | Jun 2018 | B1 |
10014026 | Wu et al. | Jul 2018 | B1 |
10152457 | Bellorado | Dec 2018 | B1 |
10164760 | Bellorado et al. | Dec 2018 | B1 |
10177771 | Bellorado et al. | Jan 2019 | B1 |
10180868 | Alhussien et al. | Jan 2019 | B2 |
10276233 | Danjean et al. | Apr 2019 | B1 |
10297281 | Bellorado et al. | May 2019 | B1 |
10469290 | Marrow et al. | Nov 2019 | B1 |
10498565 | Azenkot et al. | Dec 2019 | B1 |
20020080898 | Agazzi et al. | Jun 2002 | A1 |
20020181439 | Orihashi et al. | Dec 2002 | A1 |
20030185114 | Liaw | Oct 2003 | A1 |
20030198152 | Morishima | Oct 2003 | A1 |
20030198165 | Mouri et al. | Oct 2003 | A1 |
20040101068 | Wang et al. | May 2004 | A1 |
20040228397 | Bach | Nov 2004 | A1 |
20050117243 | Serizawa | Jun 2005 | A1 |
20050270687 | Zweighaft | Dec 2005 | A1 |
20060214708 | Huang | Sep 2006 | A1 |
20060215290 | Kurtas et al. | Sep 2006 | A1 |
20070139805 | Mead | Jun 2007 | A1 |
20070139806 | Southerland et al. | Jun 2007 | A1 |
20070177292 | Bui et al. | Aug 2007 | A1 |
20080007855 | Vityaev et al. | Jan 2008 | A1 |
20080158711 | Bliss et al. | Jul 2008 | A1 |
20080175309 | Fimoff et al. | Jul 2008 | A1 |
20090028252 | Lu | Jan 2009 | A1 |
20090097606 | Hutchins et al. | Apr 2009 | A1 |
20090141386 | Miura | Jun 2009 | A1 |
20090262870 | Ashbrook et al. | Oct 2009 | A1 |
20090323214 | Grundvig et al. | Dec 2009 | A1 |
20100290153 | Hampshire | Nov 2010 | A1 |
20110002375 | Honma | Jan 2011 | A1 |
20110072335 | Liu et al. | Mar 2011 | A1 |
20110090773 | Yu et al. | Apr 2011 | A1 |
20110176400 | Gerasimov | Jul 2011 | A1 |
20120082018 | Gushima | Apr 2012 | A1 |
20120105994 | Bellorado et al. | May 2012 | A1 |
20120155577 | Shukla et al. | Jun 2012 | A1 |
20130076433 | Fratti | Mar 2013 | A1 |
20130201838 | Homchaudhuri et al. | Aug 2013 | A1 |
20140009192 | Suzuki | Jan 2014 | A1 |
20140035638 | Bode | Feb 2014 | A1 |
20140223114 | Wang et al. | Aug 2014 | A1 |
20150003221 | Sankaranarayanan et al. | Jan 2015 | A1 |
20150022916 | Zou et al. | Jan 2015 | A1 |
20150279398 | Fan et al. | Oct 2015 | A1 |
20150355838 | Chen et al. | Dec 2015 | A1 |
20150380048 | Oberg et al. | Dec 2015 | A1 |
20160019921 | Bui et al. | Jan 2016 | A1 |
20160112218 | Abe | Apr 2016 | A1 |
20160164532 | Zhang | Jun 2016 | A1 |
20160293205 | Jury et al. | Oct 2016 | A1 |
20160351227 | Koshino | Dec 2016 | A1 |
20170125089 | Sankaranarayanan et al. | May 2017 | A1 |
20170125110 | Sankaranarayanan et al. | May 2017 | A1 |
20170236592 | Alhussien et al. | Aug 2017 | A1 |
20170249206 | Jeong et al. | Aug 2017 | A1 |
20180011753 | Alhussien et al. | Jan 2018 | A1 |
20180012663 | Alhussien et al. | Jan 2018 | A1 |
20180277158 | Kishino | Sep 2018 | A1 |
20180367164 | Marrow et al. | Dec 2018 | A1 |
20190130967 | Danjean et al. | May 2019 | A1 |
20200065262 | Bellorado | Feb 2020 | A1 |
Entry |
---|
Bellorado et al., “Target Parameter Adaptation”, U.S. Appl. No. 15/334,167, filed Oct. 25, 2016, Seagate Technology LLC. |
Guo, Yuanbin , “An Efficient Circulant MIMO Equalizer for CDMA Downlink: Algorithm and VLSI Architecture”, Hindawi Publishing Corporation, 2006, pp. 1-18. |
Hicks, James , “Overloaded Array Processing with Spatially Reduced Search Joint Detection”, Virginia Polytechnic Institute & State University, May 10, 2000, pp. 1-144. |
Mohammad, Maruf , “Blind Acquisition of Short Burst with Per-Survivor Processing (PSP)”, Virginia Polytechnic Institute & State University, Nov. 26, 2002, pp. 1-127. |
Nechaev, Y. B., et al., “Increasing Efficiency of Information Transmission with Interference Influence by the Use of Multi-Parameter Adaptation”, East-West Design & Test Symposium (EWDTS 2013), Rostov-on-Don, 2013, pp. 1-4 (Year: 2013). |
Number | Date | Country | |
---|---|---|---|
62522248 | Jun 2017 | US |