Patent Application
20080007855
The embodiments of the present invention may be practiced in a variety of settings that implement a hard disk drive (HDD) or other memory storage devices that utilize a motor, or some such moving device, to rotate a storage medium. The HDD may be stand alone, implemented within another device or integrated in a device or product.
Disk drive 100 typically includes one or more read/write heads 102 that are coupled to an arm 103 that is moved by an actuator 104 over the surface of the disk 101 either by translation, rotation or both. Disk drive 100 may have one disk 101, or multiple disks with multiple read/write heads 102. Disk drive 100 includes a disk controller module 110 that is utilized for controlling the operation of the disk drive, including read and write operations to disk 101, as well as controlling the speed of the servo motor and the motion of actuator 108. Disk controller module 110 may also include an interface to couple to an external device, such as a host device. It is to be noted that disk drive 100 is but one example and other disk drives may be readily implemented to practice various embodiments of the invention.
Disk drive 100, or any other equivalent disk drive, may be implemented in a variety of devices. For example, disk drive 100 may be implemented in a handheld audio unit. In one such embodiment, disk drive 100 may include a small form factor magnetic hard disk that has a diameter of approximately 1.8″ or smaller and incorporated into or otherwise used by handheld audio unit to provide general storage, including storage of audio content.
In another example embodiment, disk drive 100 may be implemented in a computer. In one such embodiment, disk drive 100 may include a small form factor magnetic disk that may be used in a variety of applications, including enterprise storage applications. Disk drive 100 is incorporated into or otherwise used by a computer to provide general purpose storage and the computer may be attached to a storage array, such as a redundant array of independent disks (RAID) array, storage router, edge router, storage switch and/or storage director. Disk drive 100 may be implemented in a variety of computers (or computing devices), such as desktop computers and notebook computers.
In another example embodiment, disk drive unit 100 may be implemented in a wireless communication device to provide general storage. In one such embodiment, the wireless communication device may communicate via a wireless telephone network such as a cellular, personal communications service (PCS), general packet radio service (GPRS), global system for mobile communications (GSM), integrated digital enhanced network (iDEN) or other wireless communications network capable of sending and receiving telephone calls. Furthermore, the wireless communication device may communicate via the Internet to access email, download content, access websites, and provide streaming audio and/or video programming. In this fashion, the wireless communication device may place and receive telephone calls, text messages, short message service (SMS) messages, pages and other data messages that may include attachments such as documents, audio files, video files, images and other graphics.
Still as another example, disk drive 100 may be implemented in the personal digital assistant (PDA). In one such embodiment, disk drive 100 may include a small form factor magnetic hard disk to provide general data storage.
In these various embodiments for disk drive 100, a variety of data, as well as program instructions, may be stored. Stored data may include, and is not limited to, general data, data for motion picture expert group (MPEG) audio layer 3 (MP3) files or Windows Media Architecture (WMA) files, video content such as MPEG4 files, JPEG (Joint Photographic Expert Group) files, bitmap files and files stored in other graphics formats, emails, webpage information and other information downloaded from the Internet, address book information, and/or any other type of information that may be stored on a disk medium.
Processing module 207 may be implemented using one or more microprocessors, micro-controllers, digital signal processors, microcomputers, central processing units, field programmable gate arrays, programmable logic devices, state machines, logic circuits, analog circuits, digital circuits, and/or any devices that manipulates signal (analog and/or digital) based on operational instructions. The operational instructions may reside in memory module 208 or may reside elsewhere. When processing module 207 is implemented with two or more devices, each device may perform the same steps, processes or functions in order to provide fault tolerance or redundancy. Alternatively, the function, steps and processes performed by processing module 207 may be split between different devices to provide greater computational speed and/or efficiency.
Memory module 208 may be a single memory device or a plurality of memory devices. Such a memory device may be a read-only memory (ROM), random access memory (RAM), volatile memory, non-volatile memory, static random access memory (SRAM), dynamic random access memory (DRAM), flash memory, cache memory, and/or any device that stores digital information. It is to be noted that when processing module 207 implements one or more of its functions via a state machine, analog circuitry, digital circuitry, and/or logic circuitry, memory module 208 storing the corresponding operational instructions may be embedded within, or reside external to, the circuitry comprising the state machine, analog circuitry, digital circuitry, and/or logic circuitry. Furthermore, memory module 208 stores, and the processing module 207 executes, operational instructions that may correspond to one or more of the steps or a process, method and/or function illustrated herein.
Each of these elements of controller 210 may be implemented in hardware, firmware, software or a combination thereof, in accordance with the broad scope of the present invention. While a particular bus architecture is shown in
In one embodiment, one or more modules of disk controller 210 are implemented as part of a system on a chip (SoC) integrated circuit. In the particular embodiment shown, disk controller 210 is part of a SoC integrated circuit that may include other circuits, devices, modules, units, etc., which provide various functions such as protocol conversion, code encoding and decoding, power supply, etc. In other embodiments, the various functions and features of disk controller 210 may be implemented in a plurality of integrated circuits that communicate and combine to perform the functionality of disk controller 210.
When the drive unit 100 is manufactured, disk formatter 203 generally writes a plurality of servo wedges along with a corresponding plurality of servo address marks at equal radial distance along the disk 101. The servo address marks are used by the timing generator for triggering a “start time” for various events employed when accessing the media of the disk 101.
Apparatus 300 of
Apparatus 300 also includes an actuator servo (or motor) 313 to move read/write head or heads 314. Read/write heads 314 are part of a read/write head assembly 315 which read data from disks 312, as well as write data to disks 312. In some embodiments, head assembly 315 may include a preamplifier to provide preamplification of data read from disks 312.
In the embodiment of
Likewise, position module 302 is used to control head actuator servo 313 to precisely place the heads 314 over a desired location on disks 312 to read or write data. The position module 302 includes a servo demodulator 330 to demodulate signals from read/write channel module 301 and the demodulated output from servo demodulator 330 is coupled to an analog-to-digital converter (ADC) 331. Demodulator 330 looks at the signal coming from the head and determines how far off the head is from being on the right track. ADC 331 converts the analog demodulated signal to a digital form for input to a servo processor 332. A second signal path from read/write channel module 301 is coupled to a servo peak detector 333, which identifies the 0's and 1's of the servo information, to determine where the head is over the disk. The output from peak detector 333 is then decoded by servo decoder 334 for input to processor 332. The demodulated and decoded information is processed by processor 332 and utilized to generate drive signals for voice coil motor (VCM) driver 336. A digital-to-analog converter (DAC) 335 is used to convert digital control signals from processor 332 into analog form. VCM driver 336 then uses the feedback loop to operate actuator servo 313 to correct the positioning of the head(s). A memory 337, shown as a ROM, is included to store instructions to operate processor 332.
Read/write channel module 301 includes a sampled detector 340 for sampling and detecting a read signal from assembly 315. The analog read data from the disk is coupled to detector 340, via head assembly 315, to be sampled and detected. The detected signal is coupled to encoder/decoder (ENDEC) module 341 to be decoded. Typically, detector 340 has an ADC to provide analog-to-digital conversion. ENDEC module 341 then decodes digital form of the sampled/detected read data and couples the read data to controller module 304. Outputs from detector 340 are also coupled to demodulator 330 and detector 333. During a write operation, ENDEC module 341 receives digital data from controller module 304 and encodes the data for writing to the disk through head assembly 315.
Read/write channel module 301 includes a clock generator 343 to provide a reference clock for generating other timing and/or clock signals for use by one or more components of disk controller 310. In other embodiments, the reference clock may be provided from a clock source external to disk controller 310, or even apparatus 300. A clock synchronizer module 342 receives the reference clock and generates clocking or timing signals for coupling to detector 340. In one embodiment, synchronizer 342 uses a phase-locked-loop (PLL) to synchronize the sampling timing of detector 340 when sampling data from disks 312.
ENDEC 341 is coupled to sequencer 351 of controller module 304 for transfer of data between read/write module 301 and controller module 304. Controller module 304 includes sequencer 351, data-path processor 352 and its memory (in way of a ROM) 355, buffer memory (shown as a RAM) 354, buffer control circuitry 353 and interface 356. As noted above, sequencer 351 provides for the transfer of data between modules 301, 304. Buffer 354, under control of buffer control circuitry 353, stores data that is to be written to the disk or was read from the disk. Interface 356 is used to interface disk controller 310 with host 212 via bus 340. As shown, bus 357 is used as an internal bus for data transfer among sequencer 351, buffer 345 and interface 356.
As noted in
As earlier described in the Background section above, the use of appropriate sampling techniques allows effective recovery of stored information read from the disk. Higher performing HDD devices may implement disk-locked clocking techniques to fine-align the electronics to compensate for looser tolerance of mechanical devices, such as disk drives. However, degradation of SNR may result in degraded BER, even with the use of disk-locked clocking control circuitry. Present use of 512 byte sector size HDD devices generally require a BER of approximately 104 (1 bit error per 10,000 bits), but when HDDs migrate to a larger sector size, such as 4096 (4K) byte sector size, it may be difficult to maintain an acceptable BER.
One way to ensure an acceptable BER is to maintain an adequate SNR. However, if a desired SNR is not possible or reasonably obtainable, then some other technique may need to be employed, which allows a lower SNR, but that which also provides for an acceptable BER.
Data sampler 402 receives read data input 401 from the read head(s), such as read/write heads 102 of
It is to be noted that a function of a PLL is to have a timing recovery loop to compare received samples to what the samples should be, based on an earlier decoded data. An offset component is then used to make a correction. In typical operation, phase or frequency correction is made to obtain timing synchronization. Accordingly, PLL 403 performs equivalently in comparing a parameter of received read data samples to earlier samples via the feedback loop. However, with PLL 403, there are two recovery timing feedback loops to choose from, depending on the state of a disk-locked clocking (DLC) scheme/system.
As noted in
Subsequently, once the DLC loop acquires a lock, so that circuit electronics are made adjustable to compensate for disk rotation tolerances, PLL 403 uses Loop B for recovery timing, in which only the phase adjustment is used in the PLL feedback loop. Once DLC locks on, the recovery timing is corrected by phase offset adjustment only.
The sampled data output is provided to error correction code (ECC) module 405 to perform error correction. A variety of ECC schemes may be used with ECC module 405. One such ECC scheme employs Reed-Solomon ECC. Accordingly, in one embodiment, ECC module 405 uses Reed-Solomon ECC to perform error correction on the sampled data to generate an ECC corrected data output 406. Other embodiments may use other ECC schemes.
A variety of techniques, including known techniques, may be employed to provide frequency and/or phase offset in a PLL to correct or recover proper timing for sampling data. The PLL timing recovery may be achieved by hardware, software, firmware, or combinations of these methods. Similarly a variety of DLC techniques, including known techniques, may be employed for DLC control of mechanical devices, such as disk servos/motors.
Furthermore, a co-pending patent application titled “Timing Recovery Optimization Using Disk Clock,” having an application Ser. No.; ______ filed ______; which is incorporated herein by reference, also describes a technique of using a PLL with a timing recovery loop and a disk-locked clock loop. The described technique of the co-pending application may be used in some embodiments to provide the two timing recovery loops A and B noted above.
The apparatus 400 of
Once DLC acquires a lock, only phase offset adjustment is used in the timing recovery (block 602), since much tighter synchronization tolerances may be achieved with DLC. The DLC allows for a finer adjustment in synchronizing the electronics to the mechanical rotation of the disk. Phase offset with DLC is generally adequate to synchronize the timing with the synchronization marks that are available on preambles of incoming analog signal, which is typically a sine wave signal.
The sampled data is then error corrected using ECC. That is, the read and sampled data is operated by a ECC module using a particular correction scheme, such as Reed Solomon ECC. One advantage of using ECC is that the combination of phase offset for the timing recovery and ECC error correction allows a worse (higher) BER to be tolerated out of the data sampler. The higher BER from the data sampler is tolerated, since the ECC further corrects the error, so that essentially the overall BER out of the ECC module is an acceptable BER for the HDD. Thus, by using an ECC scheme in combination, the disk controller may permit BERs of 10−3 (1 bit error per 1000), or even worse, such as 10−2 from the data sampler. The ECC would then compensate by improving the raw BER from the data sampler to an acceptable BER at the output of the ECC module.
One advantage of using the combination of a DLC/phase offset adjustment with ECC is that HDD migration to larger sector sizes may be achieved with current HDD technology. When the sector size of HDD devices migrate from the current 512 byte sector size to a larger sector size (for example 4096 (4K) byte sector size), current HDD devices operating with some form of recovery loop timing will most likely have worse BER when reading the larger sector size. Such undesirable change in the BER may be readily compensated by redesigning the HDD, such as by adjusting for the SNR. However this scheme most likely requires a redesign for a new HDD. Instead, as described in the above embodiments, if ECC is placed at the output of the data sampler to provide error correction, then current HDD designs need not be changed appreciably to accommodate the larger sector size. Although, the raw BER of the data at the output of the data sampler may be above an unacceptable or undesirable level, the overall BER at the output of the ECC module may be reduced to an acceptable BER level.
Furthermore, for future applications of larger sector size disks, the use of ECC allows 12-bit chunks or 12-bit symbols to be processed effectively, such as by Reed-Solomon ECC, in which the use of 12-bit error correction allows for an effective migration from 512 byte sector size HDDs to 4K byte sector size HDDs.
Thus, phase offset correction for timing recovery with use of ECC in a read channel for a disk drive is described.
As may be used herein, the terms “substantially” and “approximately” provides an industry-accepted tolerance for its corresponding term and/or relativity between items. Such an industry-accepted tolerance ranges from less than one percent to fifty percent and corresponds to, but is not limited to, component values, integrated circuit process variations, temperature variations, rise and fall times, and/or thermal noise. Such relativity between items ranges from a difference of a few percent to magnitude differences. As may also be used herein, the term(s) “coupled” and/or “coupling” includes direct coupling between items and/or indirect coupling between items via an intervening item (e.g., an item includes, but is not limited to, a component, an element, a circuit, and/or a module) where, for indirect coupling, the intervening item does not modify the information of a signal but may adjust its current level, voltage level, and/or power level. As may further be used herein, inferred coupling (i.e., where one element is coupled to another element by inference) includes direct and indirect coupling between two items in the same manner as “coupled to”. As may even further be used herein, the term “operable to” indicates that an item includes one or more of power connections, input(s), output(s), etc., to perform one or more of its corresponding functions and may further include inferred coupling to one or more other items.
Furthermore, the term “module” is used herein to describe a functional block and may represent hardware, software, firmware, etc., without limitation to its structure. A “module” may be a circuit, integrated circuit chip or chips, assembly or other component configurations. Accordingly, a “processing module” may be a single processing device or a plurality of processing devices. Such a processing device may be a microprocessor, micro-controller, digital signal processor, microcomputer, central processing unit, field programmable gate array, programmable logic device, state machine, logic circuitry, analog circuitry, digital circuitry, and/or any device that manipulates signals (analog and/or digital) based on hard coding of the circuitry and/or operational instructions and such processing device may have accompanying memory. A “module” may also be software or software operating in conjunction with hardware.
Additionally, the various components noted in the description above, may be implemented separately or integrated onto an integrated circuit (IC) chip, including being integrated as a system on a chip (SoC).
The embodiments of the present invention have been described above with the aid of functional building blocks illustrating the performance of certain functions. The boundaries of these functional building blocks have been arbitrarily defined for convenience of description. Alternate boundaries could be defined as long as the certain functions are appropriately performed. Similarly, flow diagram blocks and methods of practicing the embodiments of the invention may also have been arbitrarily defined herein to illustrate certain significant functionality. To the extent used, the flow diagram block boundaries and methods could have been defined otherwise and still perform the certain significant fumctionality. Such alternate definitions of functional building blocks, flow diagram blocks and methods are thus within the scope and spirit of the claimed embodiments of the invention. One of ordinary skill in the art may also recognize that the functional building blocks, and other illustrative blocks, modules and components herein, may be implemented as illustrated or by discrete components, application specific integrated circuits, processors executing appropriate software and the like or any combination thereof.
This application claims the benefit of priority to U.S. Provisional Patent Application Ser. No. 60/819,588; filed Jul. 10, 2006; and titled “Phase offset correction for timing recovery with use of ECC in a read channel for a disk drive,” which is incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| 60819588 | Jul 2006 | US |
