Patent Application
20100171532
The present invention relates to a phase-locked loop frequency synthesizer of the fractional N-type (hereinafter may be referred to as “F-PLL synthesizer”) having a phase variable function of an output signal used in a radio communication device or the like, and a phase shift circuit with a frequency converting function having the F-PLL synthesizer.
A conventional F-PLL synthesizer will be described with reference to
Referring to
Also, the feedback circuit includes a variable frequency divider (FD) 5 that divides the frequency of a high frequency signal to output the feedback signal, and a fractional control circuit 6 that outputs, to the variable frequency divider 5, the control signal from the frequency divider according to setting data N, K, and M from an external in synchronism with the feedback signal. As shown in
In the F-PLL synthesizer, the control signal of the frequency division has a cyclic property and fluctuates with a time, and a time average nave of the control signal within one cycle is given by (N+K/M). Accordingly, the output frequency fo of the F-PLL synthesizer is represented by the following Expression (1).
f
o
=f
r
·n
ave
=f
r·(N+K/M) (1)
where fr is a phase comparison frequency, N is an integer portion of the frequency division number of the variable frequency divider 5, and K/M is a fractional portion of the frequency division number of the variable frequency divider 5 (for example, refer to Non-patent Document 1).
Patent Document 1: JP 05-500894 A
Non-patent Document 1: T. A. D. Riley, “Delta-Sigma Modulation in Fractional-N Frequency Synthesis” IEEE Journal of Solid State Circuits, Vol. 28, No. 5, MAY. 1993, pp. 553 to 559
In the conventional F-PLL synthesizer described above, the output frequency can be controlled by the setting data N, K, and M from the external. However, because there is no means for setting the phase of the output signal with respect to the reference signal, there arises such a problem that the control cannot be conducted.
The present invention has been made to solve the above problem, and an object of the present invention is to provide a phase-locked loop frequency synthesizer of the fractional N-type and a phase shift circuit with a frequency converting function, which are capable of controlling the phases of the output signal.
According to the present invention, there is provided a phase-locked loop frequency synthesizer of a fractional N-type including: a reference oscillator that generates a reference signal; a voltage controlled oscillator that generates a high frequency signal; a variable frequency divider that divides the high frequency signal in frequency to output a feedback signal; a phase comparator that compares the reference signal and the feedback signal with each other to output a phase comparison signal; and a loop filter that outputs a control signal of the voltage controlled oscillator based on the phase comparison signal. Further, the phase-locked loop frequency synthesizer of a fractional N-type includes a frequency/phase control circuit that generates frequency division number control data in synchronism with any one of the feedback signal and the reference signal based on first setting data and second setting data to output the frequency division number control data to the variable frequency divider.
The phase-locked loop frequency synthesizer of the fractional N-type according to the present invention produces the effect that the phase control of the output signal can be conducted.
First embodiment to eleventh embodiment of the present invention will be described below.
A description will be given of a phase-locked loop frequency synthesizer of a fractional N-type according to a first embodiment of the present invention with reference to
Referring to
Subsequently, a description will be given of the operation of the phase-locked loop frequency synthesizer of the fractional N-type according to the first embodiment with reference to the drawings.
Setting data N, K, and M that gives the output frequency of the F-PLL synthesizer 100 and setting data 8 that gives the phase with respect to the reference signal are input from the external in advance. The frequency/phase control circuit 21 receives the setting data (N, K, M, θ) from the external as an input to output the frequency division number control data n(t) of the variable frequency divider 5 corresponding to the setting data to the variable frequency divider 5 in synchronism with an output signal of the variable frequency divider 5.
The variable frequency divider 5 receives the output signal of the voltage controlled oscillator 4 as an input to output the signal that has been divided in frequency according to the set frequency division number control data n(t) to the phase comparator 2 as the feedback signal and to the frequency/phase control circuit 21 as a clock signal, respectively.
The phase comparator 2 receives the output signal (feedback signal) of the variable frequency divider 5 and the output signal (reference signal) of the reference oscillator 1 as inputs to output a phase comparison signal to the loop filter 3. The loop filter 3 receives the phase comparison signal of the phase comparator 2 as an input to output a smoothed phase comparison signal to the voltage controlled oscillator 4. The voltage controlled oscillator 4 operates so that the frequencies of the reference signal and the feedback signal become equal to each other, and outputs the high frequency signal to the external of the F-PLL synthesizer 100 and the variable frequency divider 5, respectively.
The operation of the frequency/phase control circuit 21 will be described. The frequency/phase control circuit 21 obtains a pattern of n(t) in which a time average nave of n(t) per cycle becomes (N+K/M) from the setting data N, K, and M. In this example, it is assumed that N=2, K=1, and M=2, and 2 and 3 are repeated such as n(t)=2, 3, 2, 3, . . . as a pattern.
When the free running frequency of the voltage controlled oscillator 4 before the control starts is identical with each other, a time for establishing the phase synchronization is identical with each other not depending on the start data of n(t).
Now, a description will be given of the phase quantity of the output signal Do(t) with respect to the reference signal Dr(t) with reference to
Δti=(ni+ . . . +ni)/fo−i·nave/fo (2)
The total value Δtsum is represented by the following Expression (3) from Expression (2).
Δtsum=Δt1+ . . . +ΔtM=(M·n1+(M−1)·n2+ . . . nM)/fo−0.5M·(M+1)·nave/fo (3)
In order to establish the phase synchronization, it is necessary that Δtsum converge to Δtx which becomes a desired control voltage of the voltage controlled oscillator 4. In general, because the DC gain of the loop filter 3 is sufficiently high, Δtx becomes substantially zero. In order to set Δtsum to 0, it is necessary to shift the widths of the respective rectangular waveforms by toffset. The toffset is represented by the following Expression (4).
t
offset
=Δt
sum
/M (4)
The feedback signal Dv(t) is shifted from the reference signal Dr(t) by toffset with the result that Δtsum converges to 0 to establish the phase synchronization. Since the feedback signal Dv(t) and the output signal Do(t) operate in phase synchronization, the phase of the output signal Do(t) changes from the reference signal Dr(t) by (2πfo·toffset) (rad).
In this example, the description has been given assuming that the pattern of n(t) whose nave is 2.5 repeats 2 and 3. A desired output frequency (fo) can be obtained even in another data pattern (for example, 1, 4, 2, and 3 are repeated such as 1, 4, 2, 3, 1, 4, 2, 3, . . . ) of n(t) whose nave become identical through Expression (1) to Expression (4), and the phase of the output signal can be controlled. That is, even if the contents of data and the pattern cycle are different in each of the phase setting data, n(t) has the same advantage when the time average per cycle is identical.
Through Expression (2) to Expression (4), the F-PLL synthesizer according to this embodiment does not depend on the frequency (fr) of the output signal of the reference oscillator 1. Hence, as shown in
In the above description, the frequency/phase control circuit 21 operates in synchronism with the output signal of the variable frequency divider 5. Because the phase relationship between the output signal of the variable frequency divider 5 after the phase synchronization is established and the reference signal is constant, even if the frequency/phase control circuit 21 operates in synchronism with the reference signal of the reference oscillator (XO) 1, the same advantage is obtained.
A description will be given of a frequency/phase control circuit according to a second embodiment of the present invention with reference to
Referring to
In the above first embodiment, the phase of the output signal of the F-PLL synthesizer 100 can be controlled by the pattern of the frequency division number control data n(t) of the variable frequency divider 5. In the second embodiment, one technique of the frequency/phase control circuit 21 will be described.
The frequency/phase control circuit 21 shown in
The register 23 holds the input n′(t) within the register 23, and outputs the data that has been held in synchronism with the output signal Dv(t) of the variable frequency divider 5 to the variable frequency divider 5 from a first address of the register 23 as n(t). Then, after the register 23 outputs the data of a last address, the register 23 returns to the first address and repetitively outputs the data.
As shown in
A description will be given of a frequency/phase control circuit according to a third embodiment of the present invention with reference to
Referring to
In the above second embodiment, one technique of the frequency/phase control circuit 21 was described. In order to generate the output signal of a desired frequency and enable the phase control, the pattern of n(t) corresponding to the setting data (N, K, M, θ) is stored in the memory 22 in advance. However, there arises such a problem that the capacity of the memory 22 increases with an increase in the frequency and the resolution of phase. In the third embodiment, a technique by which the capacity of the memory 22 can be reduced more than that in the above second embodiment will be described.
The frequency/phase control circuit 21 shown in
The phase calculation circuit 25 receives the setting data (θ) from the external and n′(t) from the memory 22 as inputs to output n(t) corresponding to θ to the register 23. The register 23 holds the input n(t) within the register 23, and outputs the data that has been held in synchronism with the output signal Dv(t) of the variable frequency divider 5 to the variable frequency divider 5 from a first address of the register 23 as n(t). Then, after the register 23 outputs the data of a last address, the register 23 returns to the first address and repetitively outputs the data.
The phase calculation circuit 25 calculates the phase quantity obtained by n′(t) by the aid of Expression (2) to Expression (4). When the number of pattern data of n′(n) is M, the phase calculation circuit 25 conducts the calculation M times while changing the start data to obtain start data nx corresponding to θ. Then, the phase calculation circuit 25 changes the pattern of n′(t) to a pattern starting from nx to output the pattern to the register 23 as n(t).
a) and 10(b) show an example of the output data from the memory 22 with respect to the address and the output data from the phase calculation circuit 25 and the register 23. As shown in
A description will be given of a frequency/phase control circuit according to a fourth embodiment of the present invention with reference to
In the above second and third embodiments, the techniques of the frequency/phase control circuit 21 were described. Those techniques suffer from such a problem that the capacity of the memory 22 increases with an increase in the frequency and the resolution of phase. In the fourth embodiment, a technique of controlling the frequency and phase of the output signal without using the memory will be described.
The frequency/phase control circuit 21 shown in
The phase calculation circuit 25 receives the setting data (θ) from the external and n′(t) from the fractional control circuit 6 as inputs to output n(t) corresponding to θ to the register 23. The register 23 holds the input n(t) within the register 23, and outputs the data that has been held in synchronism with the output signal Dv(t) of the variable frequency divider 5 to the variable frequency divider 5 from a first address of the register 23 as n(t). Then, after the register 23 outputs the data of a last address, the register 23 returns to the first address and repetitively outputs the data.
In the frequency/phase control circuit 21 described in the fourth embodiment, the pattern of n′(t) corresponding to the setting data (N, K, M) is generated by the fractional control circuit 6 without using the memory. The calculation quantity of the phase calculation circuit 25 increases with an increase in the frequency and the resolution of the phase, but the frequency and the phase can be controlled.
A description will be given of a frequency/phase control circuit according to a fifth embodiment of the present invention with reference to
In the above second to fourth embodiments, the techniques of the frequency/phase control circuit 21 were described. In the fifth embodiment, another technique of controlling the frequency and phase of the output signal will be described.
The frequency/phase control circuit 21 shown in
The fractional control circuit 6 receives the reset signal (RST) from the reset circuit 29 and the setting data (N, K, M) from the external as inputs to output n(t) corresponding to the setting data to the variable frequency divider 5 in synchronism with the output signal Dv(t) of the variable frequency divider 5 at a timing corresponding to the reset signal.
a) and 13(b) show a relationship of the reset signal (RST) and n(t).
The timing of resetting the fractional control circuit 6 is controlled, thereby enabling the phase of the output signal of the F-PLL synthesizer 100 to be controlled.
A description will be given of a frequency/phase control circuit according to a sixth embodiment of the present invention with reference to
The frequency/phase control circuit 21 shown in
In the above fourth and fifth embodiments, a technique of generating n(t) by the aid of the fractional control circuit 6 was described. A pattern length X of n(t) is given by a function of K and M, and the longest one is α·M (α is a natural number). The number α is different depending on the fractional control circuit 6, and α is 1 in the fractional control circuit 6 shown in
The control pattern generation circuit 31 receives the setting data (θ) from the external as an input to output a control pattern p(t) corresponding to 8 to the synthetic circuit 32. The fractional control circuit 6 receives the setting data (N, K, M) from the external as an input to output a control pattern n′(t) corresponding to the setting data to the synthetic circuit 32. The synthetic circuit 32 adds or subtracts p(t) and n′(t), and outputs the synthesized control pattern n(t) to the variable frequency divider 5 in synchronism with the output signal Dv(t) of the variable frequency divider 5.
When it is assumed that the pattern length of p(t) is Y, Y that can obtain the desired Δθ regardless of X needs to satisfy the following Expression.
Y≧int(2π·360/Δθ) (5)
A pattern length Z of the synthesized n(t) is the lowest common multiple of X and Y, and Δθ is 2π·360/Z(rad). The p(t) and n′(t) of Y that satisfies Expression (5) are synthesized to make Z sufficiently longer than X, thereby making it possible to obtain a desired Δθ.
The output frequency fo of the F-PLL synthesizer in the case of using the synthesized n(t) is represented by the following Expression. In the Expressions (6) and (7) , pave is a time average value of p(t).
f
o
=f
r·(nave+pave) (a case of n′(t)+p(t)) (6)
f
o
=f
r·(nave−pave) (a case of n′(t)−p(t)) (7)
In the frequency/phase control circuit 21 described in the sixth embodiment, the control pattern generation circuit 31 and the synthetic circuit 32 are newly provided so as to obtain the desired Δθ regardless of the setting data (N, K, M) of the fractional control circuit 6.
A description will be given of a frequency/phase control circuit according to a seventh embodiment of the present invention with reference to
With the use of the synthesized n(t) through Expressions (6) and (7), the output frequency fo of the F-PLL synthesizer is a value shifted by fr·(pave) as compared with Expression (1). In this example, a description will be given of a technique of correcting the frequency shift attributable to the synthesis of the control pattern.
The frequency/phase control circuit 21 shown in
The frequency corrected setting data (N′, K′, M′) is set so as to satisfy the following Expression.
N′+K′/M′=N+K/M−p
ave(a case of n′(t)+p(t)) (8)
N′+K′/M′=N+K/M+p
ave (a case of n′(t)−p(t)) (9)
The n′(t) is generated by the aid of the frequency corrected setting data (N′, K′, M′), and then synthesized with p(t) to obtain the frequency corrected n(t). As a result, a desired fo and Δθ can be controlled.
A description will be given of a control pattern generation circuit of a frequency/phase control circuit according to a eighth embodiment of the present invention with reference to
In the above sixth and seventh embodiments, p(t) that is an output of the control pattern generation circuit 31 is synthesized with n′(t) that is an output of the fractional control circuit 6 to obtain the desired Δθ. In the eighth embodiment, a technique of the control pattern generation circuit 31 will be described.
The control pattern generation circuit 31 shown in
A description will be given of a control pattern generation circuit of a frequency/phase control circuit according to a ninth embodiment of the present invention with reference to
In the above eighth embodiment, a technique of the control pattern generation circuit 31 was described. A pattern of p(t) corresponding to the setting data 8 is stored in the memory in advance. However, because the pattern length of p(t) corresponding to 8 is extended with an increase in Δθ, there arises such a problem that the capacity of the memory 41 increases. In this example, a technique of the control pattern generation circuit 31 without using the memory 41 will be described.
The control pattern generation circuit 31 shown in
The phase calculation circuit 44 calculates the phase quantity that is obtained by p(t) by the aid of Expression (2) to Expression (4). When the number of data for one cycle of the control pattern p′(t) is X, the phase calculation circuit 44 conducts the calculation X times while shifting the start data of p′(t) one by one, and obtains p(t) corresponding to θ to output p(t) to the register 42.
In the control pattern generation circuit 31 described in the ninth embodiment, p′(t) corresponding to θ is generated by the fractional control circuit 43. The calculation quantity of the phase calculation circuit 44 increases with an increase in the resolution of the phase, but the phase can be controlled without using the memory.
A description will be given of a control pattern generation circuit of a frequency/phase control circuit according to a tenth embodiment of the present invention with reference to
In the above eighth and ninth embodiments, the techniques of the control pattern generation circuit 31 using the register were described. The pattern of p(t) corresponding to θ is temporarily stored in the register, and is output in synchronism with the clock signal. However, there arises such a problem that the capacity of the register increases with an increase in the resolution of phase. In this example, a technique of the control pattern generation circuit 31 without using the register will be described.
The control pattern generation circuit 31 shown in
A description will be given of a phase shift circuit with a frequency converting function according to an eleventh embodiment of the present invention with reference to
Referring to
In the eleventh embodiment, a description will be given of a technique of realizing the phase shift circuit 200 with a frequency converting function by the aid of the F-PLL synthesizer 100 described in the above first to tenth embodiments.
As described above, the phase shift circuit 200 with a frequency converting function shown in
The frequency conversion circuit 26 receives the signal (frequency fif) from the external and the signal (frequency fo) from the F-PLL synthesizer 100 as inputs to output the frequency mixed signal to the band pass filter 27. The band pass filter 27 receives the output signal of the frequency conversion circuit 26 as an input, suppresses the unnecessary frequency component, and outputs the desired frequency component to the external.
The input signal Dif(t) of the phase shift circuit 200 with a frequency converting function and the output signal Do(t) of the F-PLL synthesizer 100 are represented by the following Expressions (10) and (11).
D
if(t)=sin(2πfift+θif) (10)
D
o(t)=sin(2πfot+θo) (11)
where θif is an initial phase of Dif(t), and θo is a phase of Do(t).
Through Expressions (10) and (11), the output signal Dmix(t) of the frequency conversion circuit 26 is represented by the following Expression (12). In this example, it is assumed that the frequency conversion circuit 26 is an ideal multiplexer.
D
mix(t)=Dif(t)·Do(t)=sin(2πfift+θif)·sin(2πfot+θo)=0.5·(cos(2πfot+θo−2πfift−θif)−cos(2πfot+θo+2πfift+θif)) (12)
In this example, the pass frequency of the band pass filter 27 is an upper side band. Through Expression (12), the output signal Drf(t) of the phase shift circuit 200 with a frequency converting function is represented by the following Expression (13). In this example, it is assumed that the frequency conversion circuit 26 is an ideal multiplexer.
D
if(t)=−cos(2πfot+θo+2πfift)+θif=−cos(2πfrft+θrf) (13)
As represented by Expression (13), with the use of the phase shift circuit 200 with a frequency converting function, the frequency of the input signal can be converted from fif to frf(=fo+fif), and the phase can be converted from θif to θrf(=θo+θif).
| Number | Date | Country | Kind |
|---|---|---|---|
| 2006-029947 | Feb 2006 | JP | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/JP2007/051912 | 2/5/2007 | WO | 00 | 6/26/2008 |
