Patent Application
20250141100
The present disclosure relates to antennas, and, more particularly, to a phased array antenna with reconfigurable time delay units and associated methods.
Phased array antennas include an array of antenna elements that may be controlled to create a beam of radio waves that can be electronically steered to point in different directions without moving the antennas elements. The array of antenna elements are fed with a radio frequency (RF) input signal having a proper phase relationship so that the radio waves from the separate antenna elements combine to form beams, to increase power radiated in desired directions and suppress radiation in undesired directions.
Time delay units (TDUs) are typically used in a phased array antenna to provide the beam steering and phase shifting. The time delay units may be switched delay lines with quantized delays, for example. When placed in the signal paths on the array of antenna elements, these time delay lines introduce specific time delays.
Time delay units are generally designed on a case-by-case basis. Time delay units may be formed using gallium arsenide (GaAs) Monolithic Microwave IC (MMIC) technology, for example, which is expensive and has long lead times. A phased array antenna may have multiple time delay level requirements supporting the phased array architecture. This leads to multiple time delay unit designs. There is a need for time delay units to support the different time delay level requirements in phased array antennas.
A phased array antenna may include an antenna substrate, an array of antenna elements carried by the antenna substrate, and a plurality of time delay units (TDUs) coupled to the array of antenna elements. Each time delay unit may include a circuit substrate, and a plurality of delay circuits carried by the circuit substrate and coupled in series. Each delay circuit has a controllable respective signal delay value. At least one first delay circuit of the plurality of delay circuits may include a bypassable delay circuit having a bypassable signal loss, and at least one second delay circuit of the plurality of delay circuits may include a non-bypassable delay circuit having a non-bypassable signal loss.
The at least one first delay circuit may include a plurality of first delay circuits, each having an individually bypassable signal loss. Alternatively, the at least one first delay circuit may include a plurality of first delay circuits having a collective bypassable signal loss.
Each bypassable delay circuit may include an input and an output, a selectable bypass path between the input and output, and a selectable reference/delay path between the input and output. Each non-bypassable delay circuit may include an input and an output, and a selectable reference/delay path between the input and output.
The at least one first delay circuit may include at least one input first delay circuit positioned upstream of the at least one second delay circuit, and at least one output first delay circuit positioned downstream of the at least one second delay circuit.
The array of antenna elements may be arranged in a plurality of subarrays of antenna elements. The phased array antenna may include a controller coupled to the plurality of time delay units.
Another aspect is directed to a time delay unit (TDU) for a phased array antenna as described above. The time delay unit may include a circuit substrate, and a plurality of delay circuits carried by the circuit substrate and coupled in series. Each delay circuit may have a controllable respective signal delay value. At least one first delay circuit of the plurality of delay circuits may include a bypassable delay circuit having a bypassable signal loss. At least one second delay circuit of the plurality of delay circuits may include a non-bypassable delay circuit having a non-bypassable signal loss.
Yet another aspect is directed to a method for making a time delay unit (TDU) for a phased array antenna as described above. The time delay unit includes a plurality of delay circuits on a circuit substrate and coupled in series, with each delay circuit having a controllable respective signal delay value. The method may include forming at least one first delay circuit of the plurality of delay circuits, and comprising a bypassable delay circuit having a bypassable signal loss. The method may further include forming at least one second delay circuit of the plurality of delay circuits, and comprising a non-bypassable delay circuit having a non-bypassable signal loss.
The present description is made with reference to the accompanying drawings, in which exemplary embodiments are shown. However, many different embodiments may be used, and thus the description should not be construed as limited to the particular embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete. Like numbers refer to like elements throughout, and prime notations may be used to indicate similar elements in different embodiments.
Referring initially to
The combined number of bypassable delay circuits 60(1)-60(N) and non-bypassable delay circuits 70(3)-70(N−2) adds up to N. The bypassable delay circuits 60(1)-60(N) may be generally referred to as bypassable delay circuits 60, and the non-bypassable delay circuits 70(3)-70(N−2) may be generally referred to as non-bypassable delay circuits 70. In addition, the sub-arrays 30(1)-30(M) may be generally referred to as sub-arrays 30.
The time delay units 40 may advantageously be configured to provide different hierarchical layers of time delays within the phased array architecture. The reconfigurable time delay units 40 avoid the need for custom-made time delay units typically designed on a case-by-case basis. Custom-made time delay units are expensive, non-reconfigurable and generally have long lead times for manufacture.
The hierarchical layers of time delays, for example, may include a high delay level and a low delay level. The high delay level is the delay needed between adjacent sub-arrays 30 for overall operation of the phased array antenna 20. The low delay level is the delay needed within each respective sub-array 30 to achieve a phase error requirement of the phased array antenna 20.
As will be described in greater detail below, each time delay unit 40 may advantageously be selectively configured for either the high delay level or for the low delay level. In contrast, a non-reconfigurable time delay unit only supporting the high delay level is not interchangeable with a non-reconfigurable time delay unit only supporting the low delay level. The non-reconfigurable time delay unit for the high delay level would provide too much loss to be used at the low delay level. Similarly, the non-reconfigurable time delay unit for the low delay level would provide too fine a resolution to be used at the high delay level.
Each bypassable delay circuit 60 has a circuit input 61 and a circuit output 67, with selectable paths therebetween, as shown in
The input and output switches 62, 66 may be configured to select either the reference path 63, the delay path 64 or the bypass path 65. To avoid the need for an additional control line to be run for the bypass path 65, the bypassable delay circuit 60 may be hardwired for only the bypass path 65 or may be configured to select between the reference path 63 or the delay path 64. When the bypass path 65 is selected, then the bypassable delay circuit 60 is in a bypass mode. When the bypass path 65 is not selected, then the bypassable delay circuit 60 is switchable between the reference path 63 (i.e., a reference mode) or the delay path 64 (i.e., a delay mode).
A performance chart 80 for the bypassable delay circuit 60, as shown in
In the signal loss graph 81, the reference path 63 corresponds to a dashed line 82, the delay path 64 corresponds to a thin solid line 83, and the bypass path 65 corresponds to a thick solid line 84. Each of the selectable paths has a signal loss value associated therewith. If the reference path 63 is selected or if the delay path 64 is selected, then the signal loss value (dashed line 82 or thin solid line 83) is substantially the same for each of these paths. If the bypass path 65 is selected, then the signal loss value (thick solid line 84) is lower as compared to the signal loss values for the reference path 63 and for the delay path 64. The bypass path 65 advantageously provides a low loss path for the RF signal passing though the bypassable delay circuit 60.
The signal delay graph 86 corresponds to the respective signal delay values for the reference path 63, the delay path 64 and the bypass path 65 within the bypassable delay circuit 60. In the signal delay graph 86, the reference path 63 corresponds to a dashed line 87, the delay path 64 corresponds to a thin solid line 88, and the bypass path 65 corresponds to a thick solid line 89. Each of the selectable paths has a signal delay value associated therewith. The signal delay value corresponding to the reference path 63 (dashed line 87) is less than the signal delay value corresponding to the delay path 64 (thin solid line 88). The signal delay value corresponding to the bypass path 65 (thick solid line 89) is about the same as the signal delay value for the reference path 63.
Each non-bypassable delay circuit 70 has a circuit input 71 and a circuit output 77, with selectable paths therebetween, as shown in
The input and output switches 72, 76 may be configured to select either the reference path 73 or the delay path 74. When the reference path 73 is selected, then the non-bypassable delay circuit 70 is in a reference mode. When the delay path 74 is selected, then the non-bypassable delay circuit 70 is in a delay mode.
A performance chart 90 for the non-bypassable delay circuit 70, as shown in
In the signal loss graph 91, the reference path 73 corresponds to a dashed line 92, and the delay path 74 corresponds to a thin solid line 93. Each of the selectable paths has a signal loss value associated therewith. If the reference path 73 is selected or if the delay path 74 is selected, then the signal loss value (dashed line 92 or thin solid line 93) is substantially the same for each of these paths.
The signal delay graph 96 corresponds to the respective signal delay values for the reference path 73 and the delay path 74 within the non-bypassable delay circuit 70. In the signal delay graph 96, the reference path 73 corresponds to a dashed line 97 and the delay path 74 corresponds to a thin solid line 98. Each of the selectable paths has a signal delay value associated therewith. The signal delay value corresponding to the reference path 73 (dashed line 97) is less than the signal delay value corresponding to the delay path 74 (thin solid line 98).
Referring now to
The high delay level is the delay needed between adjacent sub-arrays 30 for overall operation of the phased array antenna 20. The low delay level is the delay needed within each respective sub-array 30 to achieve a phase error requirement of the phased array antenna 20.
The low delay level is supported by bypassable delay circuits 60(1), 60(2), 60(3) and non-bypassable delay circuits 70(4), 70(5), 70(6). For the low delay level, the respective signal delay values vary from 5 psec to 160 psec. These signal delay values correspond to selection of the delay path 64 in the bypassable delay circuits 60(1), 60(2), 60(3) and the delay path 74 in the non-bypassable delay circuits 70(4), 70(5), 70(6).
Since the signal delay values for the delay paths 64 in the bypassable delay circuits 60(7), 60(8) are not needed for the low delay level, the bypass paths 65 are selected. Even though the RF signal travels from the input 43 to the output 45 of the time delay unit 40, the bypass paths 65 are low loss paths so performance of the time delay unit 40 is minimally effected.
The high delay level is supported by non-bypassable delay circuits 70(4), 70(5), 70(6) and bypassable delay circuits 60(7), 60(8). For the high delay level, the respective signal delay values vary from 40 psec to 640 psec. The signal delay values correspond to selection of the delay path 74 in the non-bypassable delay circuits 70(4), 70(5), 70(6) and the delay path 64 in the bypassable delay circuits 60(1), 60(2), 60(3).
Since the signal delay values for the delay paths 64 in the bypassable delay circuits 60(1), 60(2), 60(3) are not needed for the high delay level, the bypass paths 65 are selected. As above, even though the RF signal travels from the input 43 to the output 45 of the time delay unit 40, the bypass paths 65 are low loss paths so performance of the time delay unit 40 is minimally effected.
The non-bypassable delay circuits 70(4), 70(5), 70(6) are non-bypassable since they are needed for when the time delay unit 40 is configured to support both the high and low delay levels. Here, the non-bypassable delay circuits 70(4), 70(5), 70(6) may be operated using the reference paths 63 or the delay paths 64 depending on the desired signal delay values associated with these delay circuits.
The bypass paths 65 are selected in the bypassable delay circuits 60(1), 60(2), 60(3) since the delay paths 64 are not needed when the time delay unit 40 is configured to support the high delay level. Likewise, the bypass paths 65 are selected in the bypassable delay circuits 60(7), 60(8) since the delay paths 64 are not needed when the time delay unit 40 is configured to support the low delay level.
Another embodiment of the time delay unit 40′ is based on the use of bulk bypassable delay circuits 68′, 69′ as shown in
As the name implies, when the bypass paths 65′ in the bulk bypassable delay circuit 68′ are selected, all three bypass paths are collectively selected. This is the opposite of the bypassable delay circuits 60(1), 60(2), 60(3) where the respective bypass paths 65 are individually selected. Similarly, when the bypass paths 65′ in the bulk bypassable delay circuit 69′ are selected, they are both collectively selected. Again, this is the opposite of the bypassable delay circuits 60(7), 60(8) where the respective bypass paths 65 are individually selected.
The bulk bypassable delay circuits 68′, 69′ provide less flexibility than the bypassable delay circuits 60(1), 60(2), 60(3) and 60(7), 60(8) in the time delay unit 40, but allow for increased performance since less switches are being used in the bulk bypassable delay circuits 68′, 69′.
Each bulk bypassable delay circuit 68′, 69′ includes a single input switch and a single output switch with a bulk bypass path 65′ connected therebetween. Less switches means lower losses for the time delay unit 40′. If the bulk bypass path 65′ is not selected, then the reference path 63′ or the delay path 64′ in the bulk bypassable delay circuits 68′, 69′ are also selected all at the same time, that is, collectively or in bulk.
Referring now to
Referring now to
The time delay unit 240 includes a circuit substrate 242, and delay circuits 270(1)-270(5) carried by the circuit substrate 242 and coupled in series. Each delay circuit 270(1)-270(5) has a respective signal delay value. External bypass connections 280(1)-280(4) are carried by the circuit substrate 242 and are coupled to the delay circuits 270(1)-270(5) to configure a time delay of the time delay unit 240.
The delay circuits 270(1)-270(5) include at least one first delay circuit 270(1), at least one third delay circuit 270(5), and a plurality of second delay circuits 270(2)-270(4) between the at least one first delay circuit 270(1) and the at least one third delay circuit 270(5). For discussion purposes, the at least one first delay circuit 270(1) will be referred to as a first delay circuit 270(1), and the at least one third delay circuit 270(5) will be referred to as a third delay circuit 270(5).
The time delay unit 240 may be an 8-bit time delay unit, for example. Each bit within the 8-bit time delay unit 240 may be referred to as a time delay bit. The size of the time delay unit 240 is not to be limiting since the number of time delay bits will vary in different applications.
The first delay circuit 270(1) is configured as a bulk delay circuit and includes time delay bits 1-3. The second delay circuits 270(2), 270(3), 270(4) are separate from one another. Second delay circuit 270(2) is time delay bit 4, second delay circuit 270(3) is time delay bit 5, and second delay circuit 270(4) is time delay bit 6. The third delay circuit 270(5) is also configured as a bulk delay circuit and includes time delay bits 7-8.
Each of the delay circuits 270(1)-270(5) are non-bypassable delay circuits since they do not include bypass paths as discussed above. The bypass paths are not needed since the first delay circuit 270(1) and the third delay circuit 270(5) may be selectively bypassed via the external bypass connections 280(1)-280(4). As described above, each delay circuit 270(1)-270(5) includes a reference path and a delay path, with the delay path having a signal delay value associated therewith.
Since the first delay circuit 270(1) is a bulk delay circuit and represents time delay bits 1-3, the three reference paths may be collectively selected or the three delay paths may be collectively selected. In contrast, each of the second delay circuits 270(2), 270(3), 270(4) represent a respective time delay bit that includes an individually selectable reference path or an individually selectable delay path. Since the third delay circuit 270(5) is also a bulk delay circuit and represents time delay bits 7-8, the two reference paths may be collectively selected or the two delay paths may be collectively selected.
The time delay unit 240 is configured via the external bypass connections 280(1)-280(4) using first and second external jumpers 290(1), 290(2) to support multiple layers of time delay. In one time delay configuration, the upper time delay bits 7-8 in the third delay circuit 270(5) are bypassed for a first time delay, as illustrated in
In the first time delay, an RF input signal is applied to input 243 of the first delay circuit 270(1). A first external jumper 290(1) is coupled across the first and second external bypass connections 280(1), 280(2). The RF input signal passes through the first delay circuit 270(1) and the second delay circuits 270(2)-270(4). An output of the second delay circuit 270(4) is coupled to the third external bypass connection 280(3). The third external bypass connection 280(3) functions as an RF output to provide an RF output signal for the time delay unit 240. Since the upper time delay bits 7-8 in delay circuit 270(5) are bypassed, a ground is applied to the fourth external bypass connection 280(4) and to an output 245 of the third delay circuit 270(5).
In another time delay configuration for the time delay unit 240, the lower time delay bits 1-3 in the first delay circuit 270(1) are bypassed for a second time delay, as illustrated in
The second external bypass connection 280(2) is configured as an RF input since an RF input signal is applied to the second delay circuit 270(2). A second external jumper 290(2) is coupled across the third and fourth external bypass connections 280(3), 280(4). The RF input signal passes through the second delay circuits 270(2)-270(4) and through the third delay circuit 270(5). The output 245 of the third delay circuit 270(5) functions as an RF output to provide an RF output signal for the time delay unit 240.
In yet another time delay configuration for the time delay unit 240, the lower time delay bits 1-3 are not bypassed and the upper time delay bits 7-8 are not bypassed for a third time delay, as illustrated in
An RF input signal is applied to input 243 of the first delay circuit 270(1). The RF input signal passes through the first delay circuit 270(1), the second delay circuits 270(2)-270(4) and the third delay circuit 270(5). The output 245 of the third delay circuit 270(5) functions as an RF output to provide an RF output signal for the time delay unit 240.
Referring now to
A first switch 294(1)′ is carried by the circuit substrate 242′ and is coupled between the first delay circuit 270(1)′ and the second delay circuit 270(2)′. A first external bypass connection 282(1)′ is coupled to the first switch 294(1)′. The first switch 294(1)′ may be closed or open depending on the desired time delay.
A second switch 294(2)′ is carried by the circuit substrate 242′ and is coupled between the second delay circuit 270(4)′ and the third delay circuit 270(5)′. A second external bypass connection 282(2)′ is coupled to the second switch 294(2)′. The second switch 294(2)′ may be closed or open depending on the desired time delay.
In one time delay configuration, the upper time delay bits 7-8 in the third delay circuit 270(5)′ are bypassed for a first time delay, as illustrated in
The first switch 294(1)′ is closed so that the RF input signal passes through the first delay circuit 270(1)′ and the second delay circuits 270(2)′-270(4)′. The first external bypass connection 282(1)′ is not used. The second switch 294(2)′ is open so that the second external bypass connection 282(2)′ is configured as an RF output to provide an RF output signal for the time delay unit 240′. The output 245′ of the third delay circuit 270(5)′ is grounded.
In another time delay configuration for the time delay unit 240′, the lower time delay bits 1-3 in the first delay circuit 270(1) are bypassed for a second time delay, as illustrated in
With the first switch 294(1)′ open, the first external bypass connection 282(1)′ is configured as an RF input. An RF input signal applied to the first external bypass connection 282(1)′ passes through the second delay circuits 270(2)′-270(4)′. The second switch 294(2)′ is closed so that the RF input signal passes through the second switch 294(2)′ to the third delay circuit 270(5)′. The output 245′ of the third delay circuit 270(5)′ functions as an RF output to provide an RF output signal for the time delay unit 240′.
In yet another time delay configuration for the time delay unit 240′, the lower time delay bits 1-3 are not bypassed and the upper time delay bits 7-8 are not bypassed for a third time delay, as illustrated in
An RF input signal is applied to input 243′ of the first delay circuit 270(1)′. The RF input signal passes through the first delay circuit 270(1)′, the second delay circuits 270(2)′-270(4)′ and the third delay circuit 270(5)′. The output 245′ of the third delay circuit 270(5)′ functions as an RF output to provide an RF output signal for the time delay unit 240′.
Referring now to
Many modifications and other embodiments will come to the mind of one skilled in the art having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is understood that the foregoing is not to be limited to the example embodiments, and that modifications and other embodiments are intended to be included within the scope of the appended claims.
