Patent Application
20160049538
The invention relates to a back contact solar cell, and more generally photo-voltaic cells, with base and emitter regions at the back surface of the cell, i.e. at the surface that will be directed way from the sun, and a front floating emitter layer at the front surface.
It is known to passivate the front surface of such a photo-voltaic cell by using a front floating emitter (FFE). Electrical passivation of a surface comprises the suppression of recombination losses at or near surfaces. A front floating emitter (FFE) is a non-contacted, electrically floating layer at the front surface of the semi-conductor substrate of the photo-voltaic cell with the same doping type as the emitter, i.e. opposite doping type relative to the bulk of the substrate. A cell with such a passivation is known for example from an article by H. Haverkamp et al, titled “Screen printed interdigitated back contact solar cells with laser fired contacts”, Proceedings, EU-PVSEC 2006 Dresden.
The front floating emitter (FFE) provides for passivation by reducing the product of the densities of positive and negative mobile charge carriers at the surface, so that contributions to the recombination rates that depend on that product are reduced. However, other recombination mechanisms like Auger recombination increase with increased doping level in the doping profile that provides for the increased doping level at the surface. Hence, the doping level of the FFE is a compromise. Figure la illustrates this by means of a plot of solar cell efficiency, as a function of doping level, represented by the dark electrical conductivity of the FFE, for a typical prior art solar cell design. This electrical conductivity is a measure of doping level, because it depends on the density of free charge carriers. The efficiency (eta) is a ratio of electrical output power to incoming solar light power. For very small doping levels (not shown) the efficiency drops due to decreased suppression of minority charge carrier density at the surface. The drop in efficiency for higher doping levels is the result of recombination processes like Shockley-Read-Hall and Auger recombination. Electrical conductivity values from a number of prior art publications have been indicated in this figure (Dicker et. al “Analysis of rear contacted solar cell structures for cost-effective processes and materials”, Proceedings IEEE_PVSC—2000 page numbers 387-390, Schumacher J. O. Schumacher, “Numerical simultation of silicon solar cells with novel cell structures”, Ph.D. Thesis 2000 University of Konstanz page number 136, Chan “Simplified interdigitated back contact solar cells”, Silicon PV 2012, Energy Procedia 27 (2012) pages 543-548). The sub-optimal outlying value is an inference from an example from Dicker where, for reasons of simplifying the processing, a front floating emitter with the same electrical conductivity as the back surface as used.
Unlike the front surface, the back surface of such a back contact photo-voltaic cell needs to contain base regions (or more specifically back surface field regions) in addition to emitter regions with contacts on the base and emitter regions. Base regions have net doping of the same electrical conductivity type as the substrate and emitter regions have net doping of the opposite electrical conductivity type. Back surface field regions have enhanced doping compared to the substrate. Typically, interdigitated strip shaped regions are used, forming alternate base and emitter strips regions. Because of electrical shading efficiency depends on the width of the base strips. Figure lb illustrates efficiency as a function of base strip width for a typical solar cell. Conventionally, narrow base strips are used to obtain optimal efficiency. The widths used by Dicker and Chan are indicated in figure lb by way of example.
Although the narrow width prevents the loss of efficiency due to electrical shading, this comes at a price. The narrow width of the base regions increases processing costs, because it imposes strict manufacturing tolerances. Furthermore, the narrower the width, the more base (back surface field))-emitter pairs are needed on the back surface, which also decreases efficiency. Also the difference between the widths of the base and emitter regions may make it necessary to use different electrode designs, which also complicates manufacturing.
U.S. Pat. No. 7,339,110 discloses a solar cell with interdigitated back surface field regions and emitter regions printed on the back surface. Cells with a floating front surface field are described extensively, but the possibility of using a front floating emitter is mentioned as well. In an example with a floating front surface field, emitter regions with a width of 0.7 millimeters are used. U.S. Pat. No. 7,339,110 mentions a number alternatives for the floating front surface field, including a floating junction on the front surface, to provide for good passivation of the silicon-silicon dioxide interface on the front surface. A sheet resistivity of 100 Ohms per square (10 milliSiemens square) is disclosed as an example for this floating junction layer.
Among others, it is an object to provide for a more efficient photo-voltaic cell wherein wider base regions are used on the back surface.
A photo-voltaic cell according to claim 1 is provided. Herein back surface field regions with a width of more than 0.6 millimeter and more preferably more than 0.75, 0.8 or even more than one millimeter are used. A front floating emitter layer with an average electrical conductivity value much higher than needed for minimizing surface recombination is used, selected dependent on the width of the back surface field regions. It has been found that use of such an average electrical conductivity value in the front floating emitter layer can be used to realize wide back surface field regions without a strong loss of efficiency. In an embodiment, the front floating emitter layer may extend continuously in the lateral directions of the front surface. Alternatively, it may be interrupted, e.g. to form regions over the back surface field regions, or a front floating emitter pattern over the back surface field regions to the edges of the over the back surface field regions.
In an embodiment the average electrical conductivity of the front floating emitter layer is at least an electrical conductivity value C=a*W−b, wherein W is the width of the back surface field region in millimeter, with coefficients a=5.54 milliSiemens square/millimeter and b=1.0 milliSiemens square. Preferably the average front floating emitter layer sheet conductance is less than 25 milliSiemens square.
Preferably the bulk of semi-conductor substrate (also called the base) has n-type electrical conductivity type. Preferably sheet resistance of the bulk is at least 138 Ohm per square, for example 2 Ohm centimeter for a 145 micrometer thick wafer.
In an embodiment, the photo-voltaic cell comprises first conductors on the back surface field regions and second conductors on the back surface emitter regions, the first and second conductors having substantially equal width. This may be used to minimize the costs of providing the conductors.
In an embodiment, back surface field regions at the back surface of the substrate with a same width as the back surface emitter areas are used. This may be used to simplify the layout. Preferably the back surface emitter areas with widths between 0.2 and 2 of the width of the back surface field regions, and preferably between 0.5 and 1.5.
Small widths of the surface emitter areas decrease efficiency. The emitter width may be selected to optimize efficiency.
In an embodiment, the substrate comprises a floating front surface field layer abutting the front surface of the substrate, the floating front surface field layer lying between the front surface and the front floating emitter layer. The front surface field layer is layer with the same conductivity type as the bulk of the substrate, i.e. a conductivity type opposite to that of the front floating emitter layer. During manufacturing, these layers may be realized for example by using successive doping steps for the front floating emitter layer and the floating front surface field layer. In this embodiment the floating front surface field layer functions to reduce of surface recombination and the front floating emitter layer functions to provide lateral transport of photo-generated minority charge carriers from the substrate (these being majority charge carriers in the front floating emitter layer). By separating these functions a higher efficiency can be realized.
Preferably, the front floating emitter above the base contains openings (as illustrated in
In a further embodiment, conductive connections through the front floating emitter layer from the front floating surface field layer to the bulk of the substrate. This increases efficiency by helping to transport majority charge carriers from the bulk of the substrate above the back surface emitter regions to locations over the back surface field regions, via the front floating surface field layer. These conductive connections may be quite small, for example with a diameter of no more than twice a diffusion length of the minority charge carriers in the bulk of the substrate.
Preferably conductive connections are also provided in the front floating emitter layer above the back surface emitter regions. These openings may extend over substantially the entire back surface emitter regions. This promotes collection of majority charge carriers from the bulk of the substrate to the front floating surface field layer. In a preferred embodiment the front floating surface field layer extends over all positions over the back surface emitter regions. But an improvement may already be realized if the front floating surface field layer extends over part of the back surface field region or to a position over its edge.
In an embodiment, the front floating emitter layer has parts with a relatively high first electrical conductivity and parts with relatively low second electrical conductivity. The second electrical conductivity may be optimized to minimize surface recombination and the first electrical conductivity may be used to realize more than a threshold average surface electrical conductivity above the back surface field regions.
This may be used to optimize efficiency. The parts with the first electrical conductivity preferably extend from the locations above a center of the back surface field regions to its edges. An A or any layout pattern may be used for the parts with the first electrical conductivity, such as a set of parallel lines. The combined use of parts with higher and lower conductivity may even make it possible to use a lower average conductivity than for a front floating emitter layer with constant conductivity.
In an embodiment, the front floating emitter layer is provided only over the back surface field regions, or it may have a lower second electrical conductivity value over the back surface emitter regions than a first electrical conductivity over the back surface field regions. The second electrical conductivity may be optimized to minimize surface recombination and the first electrical conductivity may be used to realize more than a threshold average surface electrical conductivity above the back surface field regions. This may be used to optimize efficiency.
The photo-voltaic cell according to any one of the preceding claims, wherein the front floating emitter layer comprises first regions of relatively higher first electrical conductivity value selected dependent on the width of said one of the back surface field regions and second regions of relatively lower second electrical conductivity value, the first regions extending from positions over said one of the back surface field regions at least substantial to an edge of said one of the back surface field regions or beyond the edge. For the purpose of selecting the average electrical conductivity of the front floating emitter layer the higher first electrical conductivity value may be selected, alternatively an average of the first and second electrical conductivities may be selected.
These and other advantages and objects will become apparent from a description of exemplary embodiments, by reference to the following figures.
a shows a plot of cell efficiency as a function of FFE electrical conductivity
b shows a plot of cell efficiency as a function of base width
b-d show contour plots with contours of constant efficiency values
Shading loss occurs in a photovoltaic cell with base regions (or more specifically back surface field regions) and emitter regions on the back surface and a front surface field or no special semi-conductor layer at the front surface and with contacts on the base and emitter regions. When current is drawn from the photovoltaic cell, the current through the emitter regions is a result of photo-excitation of minority charge carriers, mainly in the substrate. The minority charge carriers excited above the emitter regions flow vertically to the emitter regions below, but minority charge carriers excited above the base regions need to flow laterally to the emitter regions. The decreasing efficiency of the cell with increasing width of such photo-voltaic cells corresponds to the effect that for minority charge carriers excited at positions above a base region, the fraction of the minority charge carriers excited at the position that will be lost to recombination increases with distance of the position to the nearest edge of the base region. At positions far from the nearest edge this fraction approaches one. Apart from surface recombination effects, this bulk recombination effect of minority charge carriers that flow laterally is substantially the same for cells with front surface field regions and front emitter regions and cells without a special front surface.
Therefore, the usual design criterion for the width of the base regions in such photo-voltaic cells with interdigitated back surface field and emitter regions is that the back surface field regions (base regions) are just so wide that no significant shading loss occurs when a short circuit or optimal power point output current is drawn. That is, contemplating a position above the back surface field region that is furthest from the nearest emitter region (e.g. the centre midway between emitter regions adjacent the back surface field region), the design criterion ensures that the fraction of those minority charge carriers that are excited at that position due to recombination for minority charge carriers is e.g. less than a predetermined value of e.g. 90% and preferably less than half for minority charge carriers generated above the centre of the back surface field region.
In practice this comes down to a maximum contemplated width of the base regions (back surface field regions) of less than 0.6 millimeter in solar energy production cells.
The present invention uses larger widths and more preferably more than 0.75, 0.8 or even more than one millimeter. A width may be used at which minority charge carrier loss due to recombination for minority charge carriers flowing laterally through the substrate semi-conductor above the back surface field region would be e.g. more than 90% or more than half of the minority charge carriers generated above the centre of the back surface field region if a front surface field region or no special semi-conductor region would be used at the front surface above the substrate.
Alternatively, it may be textured, e.g. with valleys and pyramid shaped protrusions.
As used herein “floating” is used for electrically floating, i.e. without substantial electrical connection of the front floating emitter layer to the back surface field regions 26 and emitter regions 28 other than by the bulk of substrate 20. As will be described, a front surface field layer may be provided between the front floating emitter layer 24 and front surface 22a. Both in this case and the case that front floating emitter layer 24 reaches to front surface 22a, the front floating emitter layer 24 will be said to lie at front surface 22a.
Back surface field regions 26 and emitter regions 28 may be realized by providing for diffusion and/or implantation of doping into the back surface of semi-conductor substrate 20, or as added doped material on that back surface, so that the emitter regions form hetero junctions at the contact with semi-conductor substrate 20. Such areas in or on semi-conductor substrate 20 will be referred to as areas at the surface of semi-conductor substrate 20.
An isolating layer (not shown) may be provided between conductor tracks 27 on one hand and back surface field regions 26 and emitter regions 28 on the other hand, with electrical connections through the isolating layer to the back surface field regions 26 and emitter regions 28 at a part of the conductor tracks 27. Contact between conductor tracks 27 and back surface field regions 26 and emitter regions 28 may lead to increased recombination. But by using electrical connections through the isolating layer only at a fraction of the total area of conductor tracks 27, efficiency can be optimized independent of the width of conductor tracks 27.
Having wide tracks has the advantage that it reduces the time needed for obtaining a desired conductor track conductivity by depositing conductor tracks 27 using an incremental deposition processes such as sputtering or plating. In contrast, a layout wherein back surface field regions 26 would be much narrower than the emitter regions 28 would mean that more deposition time and material would be needed.
Preferably, the width of conductor tracks 27 is at least 80% of the width of back surface field regions 26 and emitter regions 28. Preferably, the width of conductor tracks 27 is the same on surface field regions 26 and emitter regions 28
In the cell as shown, back surface field regions 26 and emitter regions 28 have substantially equal width. A width W=1.6 millimeter may be used for example, or more generally, a width in a range of 0.75 to 3 millimeter. An advantage of using back surface field regions 26 and emitter regions 28 with equal width is that conductor tracks 27 of equal width can be used on back surface field regions 26 and emitter regions 28. Also the thickness of conductor tracks 27 can be the same.
If the width of the emitter regions 28 would be made very small, this could reduce efficiency. Narrow emitter regions 28 would allow only small areas for charge carrier flow from the front surface floating emitter to the back surface emitter, and a “base” voltage in the substrate between the front surface floating emitter and the back surface emitter that does not fully facilitate charge carrier flow from the front surface floating emitter and the back surface emitter. Increasing the emitter region width results in a part of the substrate above the emitter region 28 with a “base” voltage that improves vertical minority charge carrier flow from the front surface floating emitter to the back surface emitter (minority charge, that is, of the polarity that is minority charge carrier in the semi-conductor substrate, but majority charge carrier in the front surface floating emitter to the back surface emitter). Back surface emitter regions of equal width as the back surface field regions are preferred. With back surface field regions of more than 0.6 and preferably more than 0.75 or 1 millimeter, the back surface emitter regions preferably at least have widths between 0.2 and 2 times the width of the back surface field regions, and preferably between 0.5 and 1.5.
In embodiments, a silicon substrate 20 is used, with a thickness of between 50 and 250 micrometer (e.g. 180 micrometer) between front surface 22a and back surface 22b and a resistance of more than 0.012 Ohm meter. In embodiments, back surface field regions 26 have a width W between 0.75 and 3 millimeter. Herein the width W is the side to side distance along the smallest direction of the strips, or more generally the smallest distance between opposite parallel sides between which an electrode is located. In embodiments, back surface field regions 26 and emitter regions 28 have substantially equal width (e.g. less than 10% difference). In embodiments, front floating emitter layer 24 has an electrical conductivity of more than 10 milli-Siemens square conductance. Electrical conductivity depends on doping density in floating emitter layer 24 and the thickness of this layer from the surface to a junction depth (the depth where the doping densities of opposite electrical conductivity types are equal). The process of creation of the layer provides for a relation between doping density and thickness. In practice the thickness may be between 0.5 and 1 micrometer for example. Preferably, substrate 20 is of n-electrical conductivity type silicon, e.g. phosphor doped and the front floating emitter layer 24 is of p-electrical conductivity type, e.g. boron doped.
In prior art back contact photo-voltaic cells with a front floating emitter p-electrical conductivity type substrates are mostly used, with thicker and less resistive substrates (more than 200 micron thick and less than 0.0125 Ohm meter resistivity).
For such p-type substrates, the prior art uses phosphor doped front floating emitters, with resistance values of less than 10 milli-Siemens square. The back surface field regions are less than 0.4 millimeter wide and the emitter regions are at least five times as wide as the back surface field regions in order to reduce the effect of electric shading.
Front floating emitter depth and doping density vary with electrical conductivity of the front floating emitter layer 24.
In the simulation a passivation that eliminates Shockley Reed Hall recombination was assumed. The residual recombination at the surface is due to Auger recombination which increases with carrier density. In practice, a degree of Shockley Reed Hall recombination is inevitable, the degree of Shockley Reed Hall recombination depending on the manufacturing process. The Shockley Reed Hall recombination will have the effect that efficiency will go down with increasing FFE electrical conductivity for higher FFE electrical conductivity, instead of levelling off as in
This is illustrated in
The circles (C) show the effect without Shockley Reed Hall recombination and the squares (B) show the effect with Shockley Reed Hall recombination. As can be seen, the efficiency will have a maximum as a function of FFE electrical conductivity, the exact position of the maximum being dependent on the manufacturing process.
As shown in
Taking account of the elimination of Shockley Reed Hall recombination, the top plot in
The leftmost points in
However,
The threshold doping concentration value needed to avoid strong loss of efficiency shifts upwards with increasing width of the back surface field regions 26. In a band of width-electrical conductivity points on both sides of the line of optimum doping-with concentrations, the efficiency decreases much less with increasing width of surface field regions 26.
b-d show contour plots with contours of constant simulated cell efficiency values for a number of different efficiency values at 0.1% spacing in a plane wherein the width of the back surface field regions 26 and the electrical conductivity of the front floating emitter layer 24 are plotted along the horizontal and vertical axes respectively.
b-d shows plots for a substrate with bulk resistivities of 1.2 Ohm cm, 3.8 Ohm cm and 12 Ohm cm respectively (0.012, 0.038 and 0.12 Ohm meter). As can be seen from these contour plots, there is a marked qualitative difference in the behavior at the conventional small back surface field region widths of 0.4 millimeter and larger back surface field region widths. Whereas there is already a decrease in efficiency with increased FFE conductivity for small base surface field width even without manufacturing dependent recombination losses, the efficiency keeps increasing or saturates with increased FFE conductivity for back surface field widths of more than about 1.25 millimeter.
As a result, the decrease of efficiency with increasing back surface field width (the density of the contour lines) is much smaller for higher FFE conductivity values above about 10 milliSiemens square (mS·sq) FFE conductivity value.
The discovery that the efficiency hardly decreases with increasing width of the back surface field regions 26, if only one adapts the electrical conductivity value in accordance with the width can be applied by making photo-voltaic cells with larger width back surface field regions 26 than were previously contemplated (e.g. previously up to 400 micrometer wide back surface field regions 26). Widths of at least 600 micrometer, and more preferably more than one 750 micrometer or more than one millimeter and up to two or three millimeter may be used. With a correspondingly adapted front floating emitter electrical conductivity widths of one millimeter lead only to a reduction of efficiency from 22.8% to 22.4% and widths of two millimeter lead only to a reduction of efficiency to 22.1%.
In return, the increased width makes it possible to use conductor tracks 27 of less different width than when conventional narrow back surface fields are used. Preferably conductor tracks 27 of equal width of the same conductor material are used, for example aluminum. Preferably, back surface field regions 26 and emitter regions of equal width are used, for example both 1.6 millimeter wide or both between one and three millimeter wide.
Empirically it has been found from the simulations that threshold electrical conductivity values C for the front floating emitter layer that avoid strong loss in conductivity satisfy the relation C=a*W−b, wherein W is the width of the back surface field region in millimeters, with coefficients a=5.54 milliSiemens square/millimeter and b=1.0 milliSiemens square
Further simulation has shown that this band does not substantially change with substrate thickness over a range of 90-180 micrometer, although the values of the efficiency on the contours may be different (e.g. all higher or all lower). Hence, the effect may also be expected outside said range. Similarly, different values of the dark sheet conductivity of the substrate between 1.5 milliSiemens square and 15 milliSiemens square did not change the band, although the values of the efficiencies on the contours may be different. This means that the effect is useful for industrially used substrates where such variations occur. Because of the consistency of the effect it may also be expected outside this range. Similarly, it was found that no substantial change occurred in the dependence on back surface field width and FFE conductivity when the distance between back surface field regions and emitter regions was varied between 75 en 375 micron, although the absolute level of the efficiency changes.
Hence, a similar dependence may also be expected outside said range.
Although an example of a silicon substrate has been given, it is expected that a similar effect will occur for other types of substrate. Hence also for such substrates efficiency values near those for cells with narrow back surface field regions are possible if a front floating emitter with an electrical conductivity selected dependent on the width of the back surface field regions is used. The optimal electrical conductivity may be selected by using a given layout of the back surface and determining efficiency values for cells with front floating emitters with different electrical conductivity values. The electrical conductivity value with the best efficiency, or at least no more than a predetermined deviation from the best efficiency (e.g. no more than 0.2% less) may then be used for production.
The length of the back surface field regions 26 (i.e. their size in the direction transverse to the direction along which the width is defined) is not expected to have a significant effect, as long as it is larger than the width, preferably at least twice as large. Although strip shaped areas with straight parallel edges have been shown by way of illustration, it should be appreciated that areas of any other shape may be used, in which case the width W of a back surface field region 26 is defined as twice the distance of a point in the back surface field region 26 to the closest edge of the back surface field region 26, where a point with the largest such distance is used. In principle, a combination of back surface field region 26 with mutually different widths may be used, different parts of the front floating emitter layer 24 having different electrical conductivity in accordance with the width of the underlying back surface field regions 26. Preferably all back surface field regions 26 have the same width, or at most a minority in terms of overall back surface field area has a different width, for example only back surface field regions 26 nearest to the edges of the photo-voltaic cell.
The front floating emitter layer may be created for example by depositing a doping source material (e.g. a boron containing glass in the case of an n-type substrate) on the front surface, followed by a heating step to cause emitter doping to diffuse into the substrate. The electrical conductivity of the front floating emitter layer may be controlled by selection of the temperature of the heating step and/or its duration. The electrical conductivity of the front floating emitter layer may also be adjusted by means of a subsequent etch back step, wherein material is etched from the front surface. In this case, the duration of the etch back step may be set to control a change of the electrical conductivity.
The size of the back surface field regions may be controlled by a patterning process.
One example is a screen printing process with a screen pattern corresponding to the desired width. Another process may use photolithography with photo-masks that define the size. For example, back surface field doping source material (e.g. a material containing phosphor in the case of an n-type substrate) may be applied in a pattern to the back surface, followed by a heating step to cause back surface field doping to diffuse into the substrate, thereby locally inverting the net doping polarity in the emitter layer.
A tentative explanation of the source of the effect is that photo-generated minority charge carriers from the bulk of substrate 20 above the back surface field regions 26 migrate to front floating emitter layer 24 and are transported laterally through front floating emitter layer 24 to locations over or near back surface emitter regions 28. Improved electrical conductivity of the front floating emitter layer 24 increases this effect. The result is a reduction in losses due to electrical shading. This introduces a third effect in the compromise between lower and higher doping levels of front floating emitter layer 24, in addition to the effects of one type charge carrier density suppression and the onset of other recombination mechanisms. As is illustrated by
Front surface field layer 50 and front floating emitter layer 24 have mutually opposite electrical conductivity type. During manufacture, front surface field layer 50 may be created for example by using an additional diffusion step with doping material of the appropriate electrical conductivity type (n or p type dependent on whether an n-type of p-type substrate 20 is used respectively, e.g. phosphor or boron), later than the step wherein the doping of the front floating emitter layer 24 is first diffused. In this embodiment, front surface field layer 50 performs the function of suppressing minority charge carrier density at the surface in order to reduce surface recombination. However, front floating emitter layer 24 still functions to make it possible to use a wider back surface field region when the electrical conductivity of front floating emitter layer 24 is selected in correspondence with the width of the back surface field region. Preferably, vias through the floating emitter layer 24 are provided (regions with the same conductivity type as front surface field layer 50).
When a front surface field layer is used in addition to the front floating emitter, floating emitter layer 24 may be omitted in areas of the front surface that lie above emitter regions at the back surface of the substrate.
a shows an embodiment (not to scale) wherein parts of the substrate that form connection openings from the front surface field layer through the front floating emitter layer 24 to the bulk of substrate 20 are provided at locations above back surface field regions 26. The number and size of the openings is illustrative only (not to scale). It should be appreciated that the openings will have a limited size in a direction perpendicular to the plane of the cross-section, so that currents through the front floating emitter to points above the edges of back surface field regions 26 are not prevented. As used herein a connection opening is a part of the substrate wherein the electrical conductivity type remains the same as that in the bulk of substrate up to the front surface. The size of each connection opening is preferably so small that no point in the connection openings is more than the effective diffusion length of the minority charge carriers (e.g. at most one millimeter) away from the edge of the connection openings. The connection openings function to transport photo-generated majority charge carriers from front surface field layer 50 to substrate 20 and from there to back surface field regions 26, thereby increasing efficiency. Connection openings may be created for example by using masked areas on the front surface in one or more steps wherein the front floating emitter layer 24 is created, or by local diffusion of doping at the locations of the connection openings to reverse the net doping polarity in the connection openings.
Furthermore, as shown in
Although the front floating emitter layer 24 may extend as a uniform blanket over the entire front surface of the substrate, this is not necessary.
a shows an embodiment comprising the front floating emitter layer with locally enhanced doping of the opposite electrical conductivity type compared to the substrate. A top view of the front surface is shown, but back surface field regions 26 and their edges (dashed lines 71) are indicated for reference. On the front surface regions (shown as dashed areas) of relatively higher front floating emitter conductance are provided extending continuously over back surface field regions 26 and beyond their edges 71. Further front regions 72 of relatively lower front floating emitter conductance are provided above part of the back surface emitter regions (not indicated), between the front surface regions with relatively higher front floating emitter conductance. Alternatively, a front floating emitter region may be omitted at the location of these further front regions 72.
If a non-uniform floating emitter layer 24 is used, the average conductivity of the front floating emitter layer 24 above the back surface field regions 26 is preferably set in the band shown in
Lines 60 need not be straight, nor need they run perpendicularly to the edges. Lines 60 may extend transversely from positions above the edge of a back surface field region into the area above that back surface field region (as used herein transversely includes perpendicularly, but also other angles to the edge provide that the lines reach substantially into the area above the back surface field region, e.g. at least halfway the opposite edge). Lines that extend perpendicularly are preferred. It suffices that they reach at least substantially to the edges or beyond. In this example lines 60 make it possible to use wider back surface field regions. The electrical conductivity in lines 60 may be deviate from the threshold suggested for a blanket layer in
In another embodiment front floating emitter layer 24 may be replaced by a front surface field layer, or a mix of front floating emitter regions and front surface field regions, each between the bulk of substrate 20 and the front surface, in parts of the front surface that lie above the emitter regions at the back surface. In these parts front floating emitter layer 24 contributed much less to efficiency. Use of front surface field regions that extend from points above the back surface emitter regions towards the edge of these back surface emitter regions may even increase efficiency by reducing potential gradients above the back surface emitter regions. In a further embodiment a grid of conductors, such as conductors made of a conventional transparent conductive oxide (TCO), or metal conductors may be used. A mix of floating emitter regions and front surface field regions may be created for example by using masked areas on the front surface in one or more steps wherein the front floating emitter layer is created, or by local diffusion of doping at the locations of the connection openings to reverse the net doping polarity in the connection openings. In an embodiment of a process of manufacturing the photo-voltaic cell comprises creating emitter layers in the substrate adjacent the front surface and the back surface using common steps, in combination with a separate step to create a pattern of back surface field regions at the back surface. This may result in a photo-voltaic cell wherein the front floating emitter and the emitter regions at the back surface have the same doping profile. It has been found that the doping profiles for near optimum results from the front floating emitter can be used for providing effective emitters areas at the back surface.
In an alternative embodiment, the emitter layers at the front surface and the back surface may be created using separate steps. This makes it possible to optimize the front floating emitter doping (as shown in
| Number | Date | Country | Kind |
|---|---|---|---|
| 2010382 | Mar 2013 | NL | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/NL14/50128 | 3/3/2014 | WO | 00 |
