Patent Application
20050133081
The present invention relates to solar cells, in particularly a discrete semiconductor device including solar cells that are integrated with a transistor.
State of the art high efficiency photovoltaic (“PV”) solar cells have been introduced as a component in a die (chip) or wafer. A typical solar cell producer uses semiconductor manufacturing processes that are specialized to produce the PV solar cells. The same producer sells the solar cells in the form of chips or wafers. Each solar cell is formed on a single chip or wafer. The buyer of these cells then assembles them in large panels in a series or series-and-parallel combination to produce a higher output power than is possible from one monolithic solar cell.
A solar cell, in its basic form, is a p/n junction (a diode) that generates 0.4 to 0.7 volt when light shines on it. The high efficiency cells produce the higher voltage range, which is about 0.65 to 0.7 volt. Accordingly, a user of these cells generally has to connect them in series to generate a higher, more useful voltage. A plurality of such solar cell arrays are connected in parallel to produce higher output current, thereby generating higher electrical power.
For a six-volt output, 10 PV cells are generally connected in series. Each chip has to be isolated from each other and connected in a scheme, as shown in
One proposed solution has been to use a dielectric isolation (DI) technology. This technology provides a monolithic chip or substrate having a higher voltage output without using connecting wires, conductor pads, and other external components. The DI technology may be used to provide a monolithic substrate having a plurality of solar cells. At first, a photoresist layer is provided on a front side of a silicon substrate. The photoresist is patterned and etched to expose certain parts of the silicon substrate. The exposed parts are etched to form a plurality of grooves on the substrate. The photoresist is then removed.
The substrate is doped with impurities to form a buried layer. An oxide layer is formed on the buried layer. A polysilicon layer is deposited on the oxide layer to a thickness of 500 microns or more. The substrate is then flipped over and grinded to remove excess portions of silicon on the backside.
The DI technology requires deposition of a thick layer of polysilicon and then mechanical coarse grinding techniques, which is both costly and results in a high degree of defects. Also, it is difficult to make a small-sized solar cell devices using the DI technology due to its coarse grinding step.
The present invention relates to a photo voltaic (PV) device having a plurality of PV solar cells integrated with at least one transistor, e.g., MOSFET. The PV device is formed on a single or monolithic semiconductor substrate. The output voltage of the PV device may be customized to a desired level by appropriately connecting a given number of the PV cells in series during fabrication steps of the PV device. Similarly, the output current is also customized to a desired level by appropriately connecting the PV cells in parallel during the fabrication of the PV device. These series and parallel connections are obtained by patterning the interconnect (or metal) layer that is deposited on top of the solar cells.
By using microelectronic techniques disclosed herein, a smaller-sized PV device that outputs a relatively high voltage (e.g., 3-6 volts) is obtained. In the present embodiment, a relatively small die-sized PV device can be packaged in a simple package, like the ones used in discrete semiconductor devices, e.g., LEDs, transistor, diodes etc., with a transparent plastic encapsulation.
As used herein, a packaged device including a PV die is referred to as a “packaged PV device.” The packaged PV device is a discrete device that includes one or more PV dice that share a common package. One or more semiconductor devices or components (e.g., LED, transistor, capacitor, charge pump, diode, etc.) may also be included in the same package with the solar cells. The semiconductor component may be integrated with the solar cells on a monolithic substrate or wire-bonded (or otherwise connected) to the monolithic substrate. As used herein, a “PV device” generally refers to a component including at least one die having one or more PV cells, but may also be used to refer to a packaged PV device. The terms “PV cell” and “solar cell” are used interchangeably and refer to a component that is able to generate a current or voltage when exposed to visible light (not limited to sunlight) or other electromagnetic radiation.
In one embodiment, a packaged PV device has a plurality of pins, e.g., two pins, and can be used as a discrete component in a desired circuit or product. Such a discrete product (or a single packaged product) contains one or more small, packaged PV devices with high voltage outputs. Each PV device or die generates about 0.6 to 0.7 volt of output. The discrete product enables the operation of portable electronic devices with off-line battery chargers, namely using light energy to charge the battery. With the use of such a discrete product, wireless electronic devices or instruments may be mounted virtually anywhere and operated without a fixed power line. These electronic devices can be powered using solar energy using the high efficiency PV devices described herein.
Modem IC's often requires very low operating or quiescent currents, which the present PV devices can power by charging the battery or energy storage capacitors in the IC's as part of an electronic device. The present PV device of the present invention may be used in various electronic devices, e.g., remote sensors, which are wireless and free of the need to be connected to a power line. Also, the PV dice themselves can be used as part of batteries to trickle charge the batteries internally if a PV device is implemented as part of the battery. To charge the batteries, a PV device of the desired voltage needs to be selected. For 1.5 volt batteries, a PV device having 3 PV cells that are integrated to provide about 1.8 volt is needed in the present implementation. The number of PV cells that need to be connected in series depends on the voltage output desired for a PV device.
In one embodiment, a photovoltaic (PV) cell device comprises a first semiconductor substrate; a second semiconductor substrate bonded to the first semiconductor substrate; an insulating layer provided between the first and second substrates to electrically isolate the first substrate from the second substrate; a plurality of PV cells defined on the first substrate, each PV cell including a n-type region and a p-type region; a plurality of vertical trenches provided in the first substrate to separated the PV cells, the vertical trenches terminating at the insulating layer; a plurality of isolation structures provided within the vertical trenches, each isolation structure including a first isolation layer including oxide and a second isolation layer including polysilicon; and an interconnect layer patterned to connect the PV cells to provide X number of PV cells in series and Y number of PV cells in parallel. The n-type regions are formed by performing ion implantation of arsenic to provide shallow junction depths for the n-type regions, so that PV cell device is optimized for sunlight. Each trench has an opening whose width is greater than 5,000 angstroms. Each trench may have a width of about 2 microns or more, or about 3 microns or more.
In another embodiment, a photovoltaic (PV) device comprising a silicon-on-insulator (SOI) substrate including a first substrate, a second substrate, and an insulating layer provided between the first and second substrates; a plurality of tubs defined using the first substrate, each tub being isolated from an adjacent tub using the insulation layer and an isolation structure; a first PV array including a plurality of PV cells to generate a first voltage when light is shined on the first PV array; a second PV array including a plurality of PV cells to generate a second voltage when the light is shined on the second PV array; a transistor defined on one of the tubs and coupled to the first and second PV arrays, wherein the first PV array is configured to provide a turn-on voltage to the transistor when the second PV array is generating the second voltage. The device includes no more than two leads extending outwardly from a package of the device. The device includes no more than six leads extending outwardly from the package of the device.
In another embodiment, a packaged photovoltaic (PV) device includes a structure including a first substrate, a second substrate, and an insulating layer provided between the first and second substrates; a plurality of tubs defined using the first substrate, each tub being isolated from an adjacent tub using the insulation layer and an isolation structure extending orthogonal to the insulation layer; a first PV array including a plurality of PV cells to generate a first voltage when the light is shined on the first PV array; a component defined on at least one tub and coupled to the first PV array, the component including a first node coupled to the first PV array and a second node configured to be coupled to a load; and a packaged enclosing the first PV array and the component, wherein the component is configured to be turned on when the first PV array is generating the first voltage, so that the generated first voltage can be transferred from the first node to the second node, wherein each PV cell of the first PV array is defined in a corresponding one of the plurality of tubs.
In another embodiment, a method for forming a photovoltaic (PV) device includes providing a structure including a first substrate, a second substrate, and an insulating layer provided between the first and second substrates; forming a plurality of tubs using the first substrate, each tub being isolated from an adjacent tub using the insulation layer and an isolation structure extending orthogonal to the insulation layer; forming a first PV array including a plurality of PV cells to generate a first voltage when light is shined on the first PV array; forming a second PV array including a plurality of PV cells to generate a second voltage when the light is shined on the second PV array; forming a transistor defined on at least one tub and coupled to the first and second PV arrays; and enclosing the first and second PV arrays and the transistor in a package.
The present invention relates to photo voltaic (PV) devices having solar cells formed on a monolithic substrate, e.g., silicon substrate or crystal.
The PV device 400 includes a plurality of tubs or cells 402, 404, and 406. The tubs are formed on a first silicon substrate 412 that overlies an oxide layer 414. A second silicon substrate (not shown) is provided below the oxide layer. The PV device 400 is made on a wafer bonded structure or SOI structure in the present implementation but other types of substrate may also be used.
Each tub is a PV or solar cell, which is a type of pn junction diode that generates electrical current when visible light or other electromagnetic radiation is shined thereon or photons are directed toward the surface thereof. The bodies of the tubs are p-type regions 416, 418, and 420. These regions have dopant concentration of about 4 e14 to 7 e14 Boron, and maybe referred to as p− regions. N-type regions 422, 424, and 426 are formed on the upper side of the p-type regions. These have dopant concentration of >5 e19 Arsenic and may be referred to n+ or emitter regions and can be adjusted both in junction depth and resistivity to be optimized for different wavelengths of light.
For example, in one implementation, the n+ regions are formed using ion implantation of arsenic to provide shallow junction depth of about 1 micron or less. The junction depth preferably should be no more than 2 microns deep to minimize photon recombination therein and provide highly efficient PV cells. The junction depth in question and the tub depth are configured for optimal performance under sunlight and fluorescent light.
A metal interconnect 432 connects the tubs 402, 404, and 406 in series to obtain a high voltage output. The metal interconnect is formed by depositing a metal layer, e.g., aluminum, and then etching it to obtain a desired connection pattern. The metal layer can be patterned to obtain a desired number of tubs in series connection to provide a desired voltage output. Similarly, the metal layer may be patterned to obtain a desired number of tubs in parallel connection to provide a desired level of current output.
The silicon tubs are separated by isolation structures 442 formed within a plurality of trenches. Each trench has an opening whose width is greater than 5,000 angstroms, or at least 2 microns. In one implementation, the width of the opening is about 3 microns or more. The trenches are vertically (anisotropically) etched in the present embodiment, but may be sloped in other applications.
The sidewalls of the trenches are doped to provide gettering sites 444. A silicon dioxide layer 446 is formed on the gettering sites. Undoped polysilicon is deposited in the trenches and chemically mechanically polished (CMP) to form polysilicon plugs 448 that are used to fill the trenches. In the present implementation, polysilicon plugs are used to reduce the stress on the structure that may otherwise be too great if an oxide plug or the like is used due to a relatively large width of the trench.
In addition to the isolation structures 442, the tubs 402, 404, and 406 are electrically isolated from each other by forming them on the oxide layer 414 that has been previously formed to bond the first and second substrates according to the SOI technology.
Using the above SOI technology, the resultant die can be scaled up for higher current by incorporating a larger PV diode area for more current output and more PV isolated elements in series for more voltage output. By using silicon substrates that are high quality single crystal silicon, the PV elements produce electrical power at higher efficiency than the DI technology.
Another advantage to the PV device based on SOI technology is derived from utilization of a vertical (anisotropic) etch technology. The resultant vertical trenches enables formation of tubs having a greater 3D volumetric tub area for a given diode size, particularly when compared to a PV device obtained using the DI technology. This is because the DI technology generally uses KOH etching, which is isotropic in nature, to form the trench. As a result sloping sidewalls are obtained in the DI technology.
As explained above, the PV devices are formed on a SOI or wafer bonded structure (WBS) in the present implementation. A plurality of PV devices defined on the WBS are then cut into a plurality PV dice.
One issue associated with using MOSFET is the necessity for providing a gate turn-on voltage to turn it on when light is shined on the PV array, so that the MOSFET is turned on and the voltage or current generated by the PV array is provided to the load. The MOSFET solution requires additional circuitry to provide the turn-on voltage for the gate of the MOSFET.
Since the MOSFET is integrated with the PV array on a monolithic substrate or WBS, the resultant die is small and can be packaged as a single, discrete device. The package includes plastic encapsulation that may be transparent. The PV device has two pins according to one embodiment.
Such a discrete product that contains small, packaged PV devices with high voltage output enables the operation of portable devices with an off line battery chargers—namely using light energy to charge up the battery. Accordingly, the present embodiment enables wireless devices or instruments to be mounted anywhere without a power line to power it since the power is obtained from light via the high efficiency PV devices.
One feature of the present embodiment is the flexibility to add more integrated circuit elements to the PV device formed on an SOI substrate. An isolated island of the SOI PV die may be incorporated to other analog or digital control circuits in an integrated form as part of the overall PV die. In the present embodiment, a transistor connects the PV array to the load. The transistor, e.g., MOSFET, is used to conduct current from the PV array to the load. The load can be a battery, a capacitor, or any electronic device that is charged or needs electrical power from the PV solar array.
A plurality of cells or tubs 512-518 are defined using the second substrate 506. The second substrate is n-type silicon. The cells are separated from each other by trenches 522. The trenches are filled with oxide and un-doped polysilicon, as explained in
The cells or tubs 512, 514 and 518 are used to define PV cells or solar cells. The cell or tub 516 is used to define a transistor 519, e.g., MOSFET. Each tub may be used to define other types electronic components since it provides an electrically isolated platform. The PV cells are defined in an n-type tubs, so that the NMOS transistor can be formed since NMOS transistors generally provide better performance characteristics than PMOS transistors for power device application. In another implementation, however, the tubs may be p-type regions.
Each PV cell 512, 514, and 518 includes a p-type region 534, which is p+ region. Each PV cell also includes an n+ region that is used to couple the cell to another cell. Conductive interconnects 540 and 542 are used for this purpose. The interconnect 540 connects the cells 512 and 514. The interconnect 542 connects the cell 514 and others (not shown) to the transistor 519 of the cell 516 and provides the necessary voltage to turn on the transistor 519.
The transistor 519 includes a gate 550, a source/drain 552, and a drain/source 554. The gate 550 is coupled to the PV cell 514 to receive the turn-on voltage via the interconnect 542. The source and drain regions provide current to flow from the PV array to the load when the gate is turned on, thereby storing or powering the load. The source and drain regions are formed in p− regions 556 and 558 in the present implementation.
As illustrated in
The PV arrays 902 and 904 are coupled to each other via nodes 930 and 931 in the illustrated embodiment. These two arrays may be electrically isolated in other embodiments. The PV array 906 is electrically isolated from PV arrays 902 and 904. Each output may output different or same voltage according to desired applications.
The PV-SOI devices above are encapsulated in plastic packages according to one embodiment. In another embodiment, the devices are encapsulated in hermetic packages with transparent plastic or glass windows. In another embodiment, the PV SOI die is assembled in an LED package with the LED die next to it. In many application for electronic products, it has been desirable to have an LED as an indicator lamp, or a source of light. In some of these applications, it is desirable also to include the PV device to provide electrical charging power. In such applications, the PV SOI die is provided next to the LED die and packaged as a singled packaged device to reduce the cost of an extra package.
The integrated package feature above uses the LED package for dual purposes: one is to diffuse and spread the LED light out of the package; and another is to concentrate the external incident light into the package onto the PV die. Furthermore, part of the LED emitted light that is not transmitted out and trapped inside the package is converted back to electrical power by the PV die inside that package. Other combinations of co-packaged LEDs and PV SOI dice can be implemented by persons trained in the art according to the teachings of the embodiments described herein.
In one embodiment, to implement the integrated device above, any of the available LED (also referred to optoelectronic packages). One can use discrete, for the single voltage output, and IC packages for the multiple voltages output, in surface mount or for insertion mounting techniques, i.e. SO, or SOT, SIP or DIP forms ( These are standard names of some of the available packages, SO & SOT designate discrete surface mount packages. SIP-single in line package, DIP-dual in line package).
This feature uses the LED package for dual purposes. One is to diffuse and spread the LED light out of the package, and another is to concentrate the external incident light into the package and onto the PV die. Furthermore, part of the LED emitted light that is not transmitted out (but is trapped inside the package) is converted back to electrical power by the PV die inside that package. Other combinations of co-packaged LEDs and PV dice can be implemented according to the application needs.
The embodiment described above may be implemented using any of the available LED or optoelectronic packages. A discrete or IC packages may be used in surface mount technology or insertion mount technology, e.g., in SO, or SOT, SIP or DIP standard packages. SO and SOT relate to discrete surface mount packages. SIP refers tot single in line package, and DIP refers to dual in line package.
The present embodiment provides one or more transparent areas above the LED and PV die or dice for multi-chip features.
The present invention has been described in terms of specific embodiment. Accordingly, the present invention may be implemented in other ways. For example, a plurality of PV arrays are formed in two or more dice and enclosed in the same package. The scope of the present invention should be interpreted based on the appended claims.
The present application claims priority from U.S. Provisional Patent Application No. 60/525,553, filed on Nov. 25, 2003, which is incorporated by reference.
| Number | Date | Country | |
|---|---|---|---|
| 60525553 | Nov 2003 | US |
