Patent Application
20230307481
The present disclosure relates to photodetector arrays (PDAs), and more particularly to PDAs for connection with readout integrated circuits (ROICs).
Power supply integrity is paramount in low-noise analog sensing applications, specifically in ROIC design. However, as additional functionality is included in every pixel pitch of ROICs, more and more components requiring interconnection are required in the ROIC designs. Even with modern CMOS processes with seven or more metal routing layers, real estate for realizing these interconnections is sparse prohibiting the creation of gridded and wide power supply traces to reduce IR (current times resistance) drop.
The conventional techniques have been considered satisfactory for their intended purpose. However, there is an ever-present need for improved systems and methods for PDA and ROIC functionality. This disclosure provides a solution for this need.
A photodetector array (PDA) system includes a dielectric passivation layer defining a front side of a material stack. An absorption layer is included as part of the material stack and is located deeper in the stack relative to the dielectric passivation layer. An array of pixels is included, each having a respective diffusion feature between the dielectric passivation layer and the absorption layer. The diffusion features are operatively connected to the absorption layer for photodetection. A metal trace runs between respective diffusion features. The metal trace is at a depth in the stack closer to the front side of the stack than the absorption layer. The dielectric passivation layer electrically insulates the metal trace from a front side surface of the stack. The metal trace is accessible for connection to a read out integrated circuit (ROIC).
The metal trace can be a first metal trace in an array of metal traces offset from an array defined by the pixel diffusion features. The metal trace can be layered on a stack of multiple sub-layers of the dielectric passivation layer. The metal trace can be separated from the front side surface of the stack by multiple sub-layers of the dielectric passivation layer. The metal trace can be embedded within multiple sub-layers of the dielectric passivation layer. The metal trace can include a stack of multiple sub-layers of metal material.
A second metal trace can run parallel to the first metal trace. The second metal trace can have a depth in the stack that is equal to that of the first metal trace. A portion of the dielectric layer can insulate between the first and second metal traces. It is also contemplated that the first metal trace can have a depth in the stack that is shallower than that of the second metal trace, wherein the first and second metal traces overly one another, and wherein a portion of the dielectric layer insulates between the first and second metal traces. These two metal traces can run at an angle relative to one another, e.g. perpendicular.
In a PIN type architecture, the dielectric passivation layer can be layered on a cap layer. The diffusion features can extend through the cap layer and into the absorption layer. In an APD type architecture, the dielectric passivation layer can be layered on a cap layer, and the diffusion features can be seated within the cap layer, which can be layered on a field control layer, which can be layered on a grading layer, which can be layered on the absorption layer. A contact layer or InP substrate can be layered on a back side surface of the absorption layer. An antireflective (AR) coating can be layered on a backside of the contact layer or InP substrate.
Each diffusion feature can be electrically connected to a hybridization bump configured to connect the respective diffusion feature to a readout integrated circuit (ROIC). An aperture can be defined through the dielectric passivation layer to the metal trace at a plurality of positions along the metal trace. A plurality of hybridization bumps can be each electrically connected to the metal trace through respective apertures through the dielectric passivation layer. The hybridization bumps of the diffusion components can form a first grid array. The hybridization bumps of the metal trace and of a plurality of parallel metal traces can form a second grid array that is offset from the first grid array. Both the hybridization bumps of the diffusion features and of the metal trace and plurality of metal traces can be planar with the PDA for connection to the ROIC.
A ROIC can be electrically connected to each of the hybridization bumps of the diffusion features and the metal trace. A power supply of the ROIC can connect to the metal trace through one of the hybridization bumps of the metal trace. The ROIC can include hybridization bumps that connect electrically with the hybridization bumps of the metal trace and diffusion features. It is also contemplated that the ROIC can include contact pads, wherein the hybridization bumps of the metal trace and diffusion features electrically connect directly to the contact pads of the ROIC.
A capacitor of the ROIC can be electrically connected to receive power from the power supply through the metal trace. An active component such as a transistor of the ROIC, and/or an active component of the ROIC, such as a capacitor, resistor, or inductor, can be electrically connected to receive power from the power supply through the metal trace.
These and other features of the systems and methods of the subject disclosure will become more readily apparent to those skilled in the art from the following detailed description of the preferred embodiments taken in conjunction with the drawings.
So that those skilled in the art to which the subject disclosure appertains will readily understand how to make and use the devices and methods of the subject disclosure without undue experimentation, preferred embodiments thereof will be described in detail herein below with reference to certain figures, wherein:
Reference will now be made to the drawings wherein like reference numerals identify similar structural features or aspects of the subject disclosure. For purposes of explanation and illustration, and not limitation, a partial view of an embodiment of a focal plane array (FPA) system in accordance with the disclosure is shown in
The FPA system 100 includes a dielectric passivation layer 102 defining a front side 104 of a photodiode array (PDA) stack 101. The dielectric passivation layer 102 includes multiple layers of oxides and nitrides. The PDA stack 101 in
With continued reference to
While
With reference now to
With reference now to
A plurality of functional components 148 of the ROIC 130 are electrically connected to receive power from the power supply 142 through the metal traces 120. Active devices such as transistors and passive devices such as capacitors, resistors, and inductors of the ROIC 130 can be electrically connected to receive power from the power supply 142 through the metal trace 120. In this way, two ROIC components can be electrically connected without needing to provide real estate on the ROIC 130 for the metal traces 120 that connect the two components. This can be used, for example to provide global power distribution from the power source 142 to other functional components in the ROIC 130.
A considerable potential benefit of systems and methods as disclosed herein is the additional global routing capability on the ROIC afforded by having additional metal layers on the photodetector array (PDA) layer. The additional global routing has several potential benefits. It can be utilized for signal interconnection and propagation across the integrated assembly. Additionally, it can be utilized to grid power supply lines to reduce the resistance of said supply lines improving supply integrity across the pixel array. This is an advance on a very important problem in image sensors. Reducing the resistance of the pixel power supply is often the last consideration in designing imaging arrays because one first needs to ensure that the desired pixel functionality is realized through the interconnection of all of the pixel circuitry and signal distribution across the pixel array. Power supply integrity is a secondary consideration although a high resistance power grid can affect pixel-level performance.
The methods and systems of the present disclosure, as described above and shown in the drawings, provide for electrical pathways through a PDA for interconnecting components of a ROIC, which can leave more room in the ROIC for functional components in the ROIC. While the apparatus and methods of the subject disclosure have been shown and described with reference to preferred embodiments, those skilled in the art will readily appreciate that changes and/or modifications may be made thereto without departing from the scope of the subject disclosure.
