Patent Application
20230387333
The present disclosure relates to photonics, and more specifically, to photodetector structures and related methods.
A “PIN photodetector” is a diode with an undoped intrinsic semiconductor region between a p-typed semiconductor and an n-type semiconductor region. PIN photodetector performance may be inhibited by dark current, which is a small electric current that flows through photosensitive devices even when no photons are entering the device and is a primary source of noise in photonic sensors. Dark current, when present, may have negative effects on photodetector performance.
An aspect of the disclosure is directed to a photodetector structure, including: a first semiconductor layer on a first portion of a doped well in a substrate; an insulative collar laterally surrounding the first semiconductor layer, the insulative collar on the first portion of the doped well between the first semiconductor layer and a second portion of the doped well; and a second semiconductor layer over the first semiconductor layer, the insulative collar laterally surrounds the second semiconductor layer.
Another aspect of the disclosure includes a photodetector structure, including: a first semiconductor layer on a first portion of a doped well in a substrate, the first semiconductor layer including epitaxial silicon; an insulative collar laterally surrounding the first semiconductor layer, the insulative collar on the first portion of the doped well between the first semiconductor layer and a second portion of the doped well; a second semiconductor layer over the first semiconductor layer, the second semiconductor layer including epitaxial germanium, the insulative collar laterally surrounds the second semiconductor layer; a third semiconductor layer over the second semiconductor layer, the third semiconductor layer including epitaxial silicon; and a doped semiconductor material over the third semiconductor layer and the insulative collar, the doped semiconductor material having an opposite doping polarity relative to the doped well.
An aspect of the disclosure related to a method of forming a photodetector structure, the method including: forming a first semiconductor layer on a first portion of a doped well in a substrate; forming an insulative collar laterally surrounding the first semiconductor layer, the insulative collar on the first portion of the doped well between the first semiconductor layer and a second portion of the doped well; and forming a second semiconductor layer over the first semiconductor layer, the insulative collar laterally surrounds the second semiconductor layer.
The foregoing and other features of the disclosure will be apparent from the following more particular description of embodiments of the disclosure.
The embodiments of this disclosure will be described in detail, with reference to the following figures, wherein like designations denote like elements, and wherein:
It is noted that the drawings of the disclosure are not necessarily to scale. The drawings are intended to depict only typical aspects of the disclosure, and therefore should not be considered as limiting the scope of the disclosure. In the drawings, like numbering represents like elements between the drawings.
In the following description, reference is made to the accompanying drawings that form a part thereof, and in which is shown by way of illustration specific illustrative embodiments in which the present teachings may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present teachings, and it is to be understood that other embodiments may be used and that changes may be made without departing from the scope of the present teachings. The following description is, therefore, merely illustrative.
It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or “over” another element, it may be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there may be no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it may be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.
Reference in the specification to “one embodiment” or “an embodiment” of the present disclosure, as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the phrases “in one embodiment” or “in an embodiment,” as well as any other variations appearing in various places throughout the specification are not necessarily all referring to the same embodiment. It is to be appreciated that the use of any of the following “/,” “and/or,” and “at least one of,” for example, in the cases of “A/B,” “A and/or B” and “at least one of A and B,” is intended to encompass the selection of the first listed option (a) only, or the selection of the second listed option (B) only, or the selection of both options (A and B). As a further example, in the cases of “A, B, and/or C” and “at least one of A, B, and C,” such phrasing is intended to encompass the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of the third listed option (C) only, or the selection of the first and the second listed options (A and B), or the selection of the first and third listed options (A and C) only, or the selection of the second and third listed options (B and C) only, or the selection of all three options (A and B and C). This may be extended, as readily apparent by one of ordinary skill in the art, for as many items listed.
A photodetector structure according to embodiments of the disclosure may provide, e.g., a stack of undoped semiconductor layers on a first portion of a doped well. The photodetector structure may include an insulative collar horizontally between a stack of undoped semiconductor layer and a second portion of a doped well. The photodetector structure may include a doped semiconductor material on a stack of undoped semiconductor layers and an insulative collar. The stack of undoped semiconductor layers may form an intrinsic region between the doped well having a first doping polarity and the doped semiconductor material having a second doping polarity opposite the first doping polarity.
In some embodiments, a stack of undoped semiconductor layers may include a first silicon layer on a first portion of a doped well, a germanium layer over the first silicon layer, and a second silicon layer over the germanium layer. The first silicon layer and the second silicon layer may include epitaxial silicon (epi-Si), and the germanium layer may include epitaxial germanium (epi-Ge).
In some embodiments, a photodetector structure may include a first contact structure electrically coupled to a doped semiconductor material and a second contact structure electrically coupled to a doped well. The second contact structure may bias the doped well to reduce dark currents from forming in the photodetector, and thus improve performance as compared to other photodetector structures.
Referring to
For purposes of reference, a doped well 104 within substrate 102 of preliminary structure 50 is illustrated. Preliminary structure 50 may include one or more trench isolation structures 106 within substrate 102. Each trench isolation structure 106 may include a trench etched into substrate 102 and filled with an insulating material such as oxide, insulative semiconductor, etc., to isolate one region of the substrate from an adjacent region of the substrate. Substrate 102 may include a variety of doped wells therein for formation of different polarity photodetector structures. Doped well 104 includes a first dopant type formed using any appropriate n-type or p-type dopant and may be formed using any now known or later developed technique (e.g., in-situ doping or ion implantation). As described herein, subsequent processing of preliminary structure 50 may include forming a second doped region (
Preliminary structure 50 may include an insulative layer 108 over substrate 102. Insulative layer 108 may be formed of, e.g., any now known or later developed insulative material such as but not limited to oxides. Insulative layer 108 may be formed using deposition and/or any other technique to form a material on substrate 102.
As used herein, “depositing” may include any now known or later developed techniques appropriate for the material to be deposited including but are not limited to: chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), semi-atmosphere CVD (SACVD) and high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reaction processing CVD (LRPCVD), metalorganic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser assisted deposition, thermal oxidation, thermal nitridation, spin-on methods, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, evaporation.
Referring now to
As discussed herein, insulative layer 108 may be removed, in part, by etching. Etching generally refers to the removal of material from a substrate (or structures formed on the substrate) and is often performed with a mask in place so that material may selectively be removed from certain areas of the substrate, while leaving the material unaffected, in other areas of the substrate. There are generally two categories of etching, (i) wet etch and (ii) dry etch. Wet etch is performed with a solvent (such as an acid) which may be chosen for its ability to selectively dissolve a given material (such as oxide), while leaving another material (such as polysilicon) relatively intact. This ability to selectively etch given materials is fundamental to many semiconductor fabrication processes. A wet etch will generally etch a homogeneous material (e.g., oxide) isotropically, but a wet etch may also etch single-crystal materials (e.g., silicon wafers) anisotropically. Dry etch may be performed using a plasma. Plasma systems can operate in several modes by adjusting the parameters of the plasma. Ordinary plasma etching produces energetic free radicals, neutrally charged, that react at the surface of the wafer. Since neutral particles attack the wafer from all angles, this process is isotropic. Ion milling, or sputter etching, bombards the wafer with energetic ions of noble gases, which approach the wafer approximately from one direction, and therefore this process is highly anisotropic. Reactive ion etching (RIE) operates under conditions intermediate between sputter and plasma etching and may be used to produce deep, narrow features, such as shallow trench isolation (STI) trenches. In this case, a RIE may be used, for example.
Referring now to
Turning to
Referring now to
First undoped semiconductor layer 118 may include semiconductor material such as, but not limited to, epitaxial silicon (epi-Si). Second undoped semiconductor layer 120 may include semiconductor material such as, but not limited to, epitaxial germanium (epi-Ge). Third undoped semiconductor layer 122 may include semiconductor material such as, but not limited to, epitaxial silicon (epi-Si). Stack of undoped semiconductor layers 124 therefore may include a first silicon layer, a germanium layer, and a second silicon layer, e.g., first undoped semiconductor layer 118, second undoped semiconductor layer 120, and third undoped semiconductor layer 122.
The term “undoped semiconductor,” as used herein, refers to an intrinsic semiconductor material without any significant dopant species present (i.e., I-Type). Each of the undoped semiconductor layers 118, 120, 122 include intrinsic semiconductor material without any significant dopant species present. Stack of undoped semiconductor layers 124 may form an intrinsic region between two doped semiconductor regions having opposite doping polarity to form a PIN photodetector structure with insulative collar 116.
Turning to
Doped semiconductor material 126 may include a doped semiconductor material formed using any appropriate n-type or p-type dopant and may be formed using any now known or later developed technique (e.g., in-situ doping or ion implantation). Doped semiconductor material 126 may include n-type dopant such as but not limited to: phosphorous (P), arsenic (As), antimony (Sb). Doped semiconductor material 126 may include p-type dopants such as but not limited to: boron (B), indium (In) and gallium (Ga). Any necessary thermal process may be carried out to drive in the dopants. Doped semiconductor material 126 may include an opposite doping polarity relative to doped well 104. Similar n-type or p-type dopants may be used for doped well 104. For example, doped semiconductor material 126 may include a n-type dopant and doped well 104 may include a p-type dopant. In other embodiments, doped semiconductor material 126 may include a p-type dopant and doped well 104 may include a n-type dopant.
Turning now to
Photodetector structure 100 includes doped semiconductor material 126 over stack of undoped semiconductor layers 124, insulative collar 116, and insulative layer 108. Doped semiconductor material 126 may include polysilicon (poly-Si) having an opposite doping polarity relative to doped well 104. Doped semiconductor material 126 may include n-type or p-type dopants. Stack of undoped semiconductor layers 124 forms an intrinsic region between doped well 104 and doped semiconductor material 126 to form a PIN photodetector. Photodetector structure 100 includes contact structure 132 electrically coupled to doped semiconductor material 126. Contact structure 132 extends through nitride cap 128 and insulative layer 130. Contact structure 132 may couple photodetector structure 100 to one or more other electronic components (not shown). Photodetector structure 100 may be part of a photonics integrated circuit (PIC) that includes one or more other electrical devices (not shown).
As further shown by
As further shown by
Embodiments of the present disclosure provide technical and commercial advantages, and some examples of such advantages are described herein. Embodiments of the disclosure may improve operational performance for photodetector structures by lowering dark current and improve quantum efficiency. Insulative collar 116 may improve dark current relative to photodetector structures without insulative collar 116. Second contact structure 134 may bias doped well 104 to distribute electrical potential uniformly, or substantially uniformly, throughout photodetector structure 100 relative to unbiased doped wells having electrical potential concentrated within a portion of an intrinsic region.
The photodetector structure 100 as described above receives optical signals, e.g., infrared, from a transmission source (not shown). The transmission source may include light-transmissive materials configured to direct optical signals to photodetector structure 100. Photodetector structure 100 coverts those optical signals into electrical signals using doped well 104, stack of undoped semiconductor layers 124, and doped semiconductor 126. These electrical signals may be transmitted from photodetector structure 100 to one or more other electrical devices (not shown) through contact structure 132.
The method as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing structures as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input structure, and a central processor.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. “Optional” or “optionally” means that the subsequently described event or circumstance may or may not occur, and that the description includes instances where the event occurs and instances where it does not.
Approximating language, as used herein throughout the specification and claims, may be applied to modify any quantitative representation that could permissibly vary without resulting in a change in the basic function to which it is related. Accordingly, a value modified by a term or terms, such as “about”, “approximately” and “substantially”, are not to be limited to the precise value specified. In at least some instances, the approximating language may correspond to the precision of an instrument for measuring the value. Here and throughout the specification and claims, range limitations may be combined and/or interchanged, such ranges are identified and include all the sub-ranges contained therein unless context or language indicates otherwise. “Approximately” or “substantially” as applied to a particular value of a range applies to both values, and unless otherwise dependent on the precision of the instrument measuring the value, may indicate+/−10% of the stated value(s).
The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the disclosure in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosure. The embodiment was chosen and described in order to best explain the principles of the disclosure and the practical application, and to enable others of ordinary skill in the art to understand the disclosure for various embodiments with various modifications as are suited to the particular use contemplated.
