Patent Application
20240088190
The present invention relates to a photoelectric conversion apparatus, a device, and a method for manufacturing a photoelectric conversion apparatus.
In a photoelectric conversion apparatus such as an image sensor, a back-illuminated photoelectric conversion apparatus may be used for miniaturization and multifunctionality. Japanese Patent Laid-Open No. 2018-088488 describes a back-illuminated sensor chip in which an avalanche photodiode element is provided for each pixel.
When forming a back-illuminated photoelectric conversion apparatus, a semiconductor layer in which pixels are arranged is thinned, and a light receiving surface is formed. In order to improve the characteristics of the photoelectric conversion apparatus, it is necessary to improve the flatness of the light receiving surface and the uniformity of the film thickness of the semiconductor layer when the semiconductor layer is thinned.
Some embodiments of the present invention provide a technique that is advantageous for improving the characteristics of a photoelectric conversion apparatus.
According to some embodiments, a photoelectric conversion apparatus comprising a semiconductor layer that includes a pixel region in which a plurality of pixels each comprising a photoelectric conversion element are arranged, wherein a plurality of wiring layers are arranged on a side of a main surface on the opposite side to a light receiving surface of the semiconductor layer, a plurality of wiring patterns are arranged in a wiring layer closest to the main surface among the plurality of wiring layers, and a pattern density of the wiring patterns arranged in a peripheral region between the pixel region and an outer edge of the semiconductor layer among the plurality of wiring patterns is 35% or more in an arbitrary 100 μm2 region of the peripheral region, is provided.
According to some other embodiments, a method for manufacturing a photoelectric conversion apparatus, the method comprising: preparing a semiconductor layer comprising a pixel region in which a plurality of pixels each including a photoelectric conversion element are arranged; thinning the semiconductor layer from a side of a light receiving surface on an opposite side to a main surface where a plurality of wiring layers are arranged, wherein a plurality of wiring patterns are arranged in a wiring layer closest to the main surface among the plurality of wiring layers, in the thinning, a film thickness of the semiconductor layer is measured by using reflected light of light irradiated onto the light receiving surface, and a pattern density of the wiring patterns arranged in a peripheral region between the pixel region and an outer edge of the semiconductor layer among the plurality of wiring patterns is 35% or more in an arbitrary 100 μm2 region of the peripheral region, is provided.
Further features of the present invention will become apparent from the following description of exemplary embodiments (with reference to the attached drawings).
Hereinafter, embodiments will be described in detail with reference to the attached drawings. Note, the following embodiments are not intended to limit the scope of the claimed invention. Multiple features are described in the embodiments, but limitation is not made to an invention that requires all such features, and multiple such features may be combined as appropriate. Furthermore, in the attached drawings, the same reference numerals are given to the same or similar configurations, and redundant description thereof is omitted.
With reference to
A wiring structure 1010 is arranged on a main surface 151 of the semiconductor layer 100 located on the semiconductor layer 200 side, and constitutes a semiconductor component 1001 together with the semiconductor layer 100, the transistors 120 arranged on the main surface 151 of the semiconductor layer 100, and the like. A wiring structure 1020 including a plurality of wiring layers is arranged on the side of a main surface 251 of the semiconductor layer 200 located on the semiconductor layer 100 side, and constitutes a semiconductor component 1002 together with the semiconductor layer 200 and the like. The main surface 251 of the semiconductor layer 200 is the surface of the semiconductor layer 200 opposite to a light receiving surface 252. The light receiving surface 252 is also a light receiving surface of the photoelectric conversion apparatus 930.
In this embodiment, the semiconductor layer 200 has a thickness of, for example, about 3 to 9 μm. The semiconductor component 1001 and the semiconductor component 1002 overlap each other and are bonded to each other at a bonding interface 400. In the Z direction in which the semiconductor layer 100 and the semiconductor layer 200 are stacked, an insulating film 112 of the semiconductor component 1001 (the wiring structure 1010) and an insulating film 212 of the semiconductor component 1002 (the wiring structure 1020) are stacked so as to be positioned between the semiconductor layer 100 and the semiconductor layer 200. In the wiring structure 1010, each of a plurality of conductive portions 113 is arranged in a respective one of a plurality of recesses provided in the insulating film 112. In the wiring structure 1020, each of a plurality of conductive portions 213 is arranged in a respective one of a plurality of recesses provided in the insulating film 212. The semiconductor component 1001 and the semiconductor component 1002 are bonded to each other by the conductive portions 113 arranged in the recesses provided in the insulating film 112 and the conductive portions 213 arranged in the recesses provided in the insulating film 212.
A plane intersecting the Z direction is defined as an X-Y plane. The Z direction and X-Y plane may intersect orthogonally. The X-Y plane may be a surface parallel to at least one of the main surface 151 of the semiconductor layer 100 and the main surface 251 of the semiconductor layer 200. An X direction and a Y direction may be orthogonal to each other, parallel to at least one of the main surface 151 of the semiconductor layer 100 and the main surface 251 of the semiconductor layer 200.
The conductive portions 213 include a pad 321 surrounded by the insulating film 212 in the X-Y plane, and a plug 322 coupled to the pad 321 so as to be positioned between the pad 321 and the semiconductor layer 200 in the Z direction. The plug 322 is connected to a conductive layer 211 located between the plug 322 and the semiconductor layer 200 in the Z direction. The conductive layer 211 is proximate to the plug 322.
The semiconductor component 1001 is a semiconductor component (semiconductor chip) including the semiconductor layer 100 and the wiring structure 1010. The semiconductor component 1002 is a semiconductor component (semiconductor chip) including the semiconductor layer 200 and the wiring structure 1020. The wiring structure 1010 and the wiring structure 1020 each include a plurality of stacked wiring layers and a plurality of stacked insulating films, as will be described later. Therefore, the structure in which the wiring structure 1010 and the wiring structure 1020 are bonded to each other may be referred to as the wiring structure portion in the photoelectric conversion apparatus 930. The photoelectric conversion apparatus 930 is configured by bonding the semiconductor component 1001 and the semiconductor component 1002.
The structure between the semiconductor layer 100 and the semiconductor component 1002 (between the semiconductor layer 100 and the wiring structure 1020) is the wiring structure 1010. The wiring structure 1010 includes the conductive portions 113 described above and a conductive layer 111. The wiring structure 1010 may include, in addition to the conductive portions 113 and the conductive layer 111, plugs 110, a wiring layer 107, plugs 108, a wiring layer 105, plugs 104, and the like arranged between the conductive layer 111 and the semiconductor layer 100. In addition, the wiring structure 1010 may include the insulating film 112 described above, and, in addition to the insulating film 112, may include the insulating films 109, 106, and 103 arranged between the insulating film 112 and the semiconductor layer 100. However, the configuration of the wiring structure 1010 is not limited to the structure illustrated in
The structure between the semiconductor layer 200 and the semiconductor component 1001 (between the semiconductor layer 200 and the wiring structure 1010) is the wiring structure 1020. The wiring structure 1020 includes the conductive portions 213 described above and the conductive layer 211. The wiring structure 1020 may include, in addition to the conductive portions 213 and the conductive layer 211, plugs 210, a wiring layer 207, plugs 208, a wiring layer 205, plugs 204, and the like arranged between the conductive layer 211 and the semiconductor layer 200. In addition, the wiring structure 1020 may include the insulating film 212 described above, and, in addition to the insulating film 212, may include the insulating films 209, 206, and 203 arranged between the insulating film 212 and the semiconductor layer 200. However, the configuration of the wiring structure 1020 is not limited to the structure illustrated in
The conductive layers 111 and 211 may be referred to as wiring layers, but in this example, the wiring layers adjacent to plugs 312 and 322 are referred to as conductive layers 111 and 211 in order to distinguish them from other wiring layers. The plug 208 connects the wiring layer 205 and the wiring layer 207, and the plug 210 connects the wiring layer 207 and the conductive layer 211. The conductive portion 213 may have a damascene structure embedded in a recess provided in the insulating film 212. At least a portion of the conductive portion 213 is connected to the conductive layer 211. In the present embodiment, the conductive portion 213 has a dual damascene structure and includes the pad 321 and the plug 322. The semiconductor component 1001 and the semiconductor component 1002 are electrically connected by the conductive portions 113 and the conductive portions 213.
A plurality of wiring patterns 601 are arranged in the wiring layer 205 which is the closest to the main surface 251 of the semiconductor layer 200 among the plurality of wiring layers 205 and 207 arranged in the wiring structure 1020. In this embodiment, the pattern density of the wiring patterns 601 arranged in a peripheral region 1051 between the pixel region 1052 and the outer edge of the semiconductor layer 200 among the plurality of wiring patterns 601 is 35% or more in an arbitrary 100 μm2 region of the peripheral region 1051. Details of the pattern density of the wiring patterns 601 will be described later.
The main components of the conductive portion 113 and the conductive portion 213 may be copper, but the present invention is not limited thereto, and the main components of the conductive portion 113 and the conductive portion 213 may be gold or silver. The main components of the insulating film 112 and the insulating film 212 may be silicon compounds such as silicon oxide, silicon nitride, and silicon oxynitride. In addition, the insulating film 112 and the insulating film 212 may have a multi-layer structure made of a plurality of materials, such as a stacked structure in which a layer (for example, a silicon nitride layer) that suppresses metallic diffusion and a silicon oxide layer or a low-k material layer are stacked. By arranging a layer that suppresses diffusion of metal, it is possible to suppress the influence of diffusion of metal caused by a bonding deviation between the conductive portion 113 and the conductive portion 213 caused by alignment deviation or the like occurring at the time of bonding the semiconductor component 1001 and the semiconductor component 1002. Further, for example, the main components of the insulating film 112 and the insulating film 212 may be resin.
Here, the conductive portions 113 and the insulating film 112 are collectively referred to as a bonding member 411, and the conductive portions 213 and the insulating film 212 are collectively referred to as a bonding member 421. The bonding member 411 included in the semiconductor component 1001 is bonded to the bonding member 421 included in the semiconductor component 1002. From the semiconductor layer 100 to the semiconductor layer 200, the plug 104, the wiring layers 105 and 107, the conductive layer 111, the conductive portions 113 and 213, the conductive layer 211, the wiring layers 207 and 205, and the plug 204 are electrically continuous. These constitute a conductive pattern (inter-layer wiring pattern) between the semiconductor layer 100 and the semiconductor layer 200. For example, one end of the inter-layer wiring pattern may be connected to the gate electrode of the transistor 120, and the other end thereof may be connected to the source/drain of the transistor 120. Further, for example, one end and the other end of the inter-layer wiring pattern may be connected to the source/drain of the transistor 120.
In the photoelectric conversion apparatus 930, the wiring structure 1010 and the wiring structure 1020 are bonded to each other. More specifically, the wiring structure 1010 and the wiring structure 1020 are bonded at the bonding interface 400 formed by the bonding member 411 of the wiring structure 1010 and the bonding member 421 of the wiring structure 1020. The bonding interface 400 includes a surface of the bonding member 411 and a surface of the bonding member 421.
An element isolation portion 101 and the plurality of transistors 120 are provided on the main surface 151 of the semiconductor layer 100. The main surface 151 of the semiconductor layer 100 may be referred to as the surface of the semiconductor layer 100. In the photoelectric conversion apparatus 930, an integrated circuit including the transistors 120 arranged in the semiconductor layer 100 may include a signal processing circuit such as an analog signal processing circuit, an A/D conversion circuit, a noise removing circuit, or a digital signal processing circuit that processes a signal outputted from the photoelectric conversion elements 222. That is, at least some of the plurality of transistors 120 may constitute a digital signal processing circuit for digitally processing signals output from the plurality of photoelectric conversion elements 222 of the semiconductor layer 200. Further, the semiconductor layer 100 may be referred to as a “semiconductor substrate”.
The element isolation portion 101 may have a shallow trench isolation (STI) configuration, and define element regions (active regions) of the semiconductor layer 100. The plurality of transistors 120 may constitute, for example, a CMOS circuit. The source/drain 121 of the transistor 120 may comprise a silicide layer 122, such as cobalt silicide or nickel silicide. Therefore, the conductive portion 113 is electrically connected to the semiconductor layer 100 via the silicide layer 122. More specifically, the plug 104 which is electrically connected to the conductive portion 113 is in contact with the silicide layer 122 formed between the interlayer insulating film 103 and the semiconductor layer 100 through a salicide process or the like. When the conductive portion 113 is electrically connected to the semiconductor layer 100 via the silicide layer 122, the contact resistance may be lower than when the conductive portion 113 is electrically connected to the semiconductor layer 100 without the silicide layer. A gate electrode 102 of the transistor 120 may include a silicide layer, a metal layer, and a metal compound layer. As the gate insulating film of the transistor 120, in addition to silicon oxide, silicon nitride, or the like, a metal oxide such as hafnium oxide or the like may be used.
On the main surface 251 of the semiconductor layer 200, an element isolation portion 201, gate electrodes 202, photoelectric conversion portions 220, a floating diffusion 221, and the like are provided. The photoelectric conversion portion 220 includes a photodiode and a photogate. The photodiode may be an avalanche photodiode. The main surface of the semiconductor layer 200 on which a plurality of transistors are provided is the main surface 251 of the semiconductor layer 200. The main surface 251 of the semiconductor layer 200 may be referred to as the surface of the semiconductor layer 200. As described above, the main surface of the semiconductor layer 200 opposite to the main surface 251 is the light receiving surface 252 on which light is incident in the photoelectric conversion apparatus 930. Further, the semiconductor layer 200 may be referred to as a “semiconductor substrate”.
The element isolation portion 201 has, for example, an STI structure and defines element regions (active regions) of the semiconductor layer 200. The gate electrode 202 transfers the electric charge of the photoelectric conversion portion 220 to the floating diffusion 221. The semiconductor layer 200 may also be provided with a pixel circuit that converts the electric charge generated by the photoelectric conversion portion 220 into a pixel signal. The pixel circuit may include a reset transistor, an amplification transistor, a selection transistor, and the like. A pixel signal corresponding to the electric charge transferred to the floating diffusion 221 is generated by the amplification transistor. The potential of the floating diffusion 221 is reset to the reset potential by the reset transistor. The photoelectric conversion element 222 described above may include the photoelectric conversion portion 220, the gate electrode 202, the floating diffusion 221, and a pixel circuit thereof.
The conductive portion 113 is electrically connected to the semiconductor layer 100 via the silicide layer 122, as described above. Meanwhile, the conductive portion 213 is electrically connected to the semiconductor layer 200 without going through the silicide layer. In the present embodiment, the plug 204 electrically connected to the conductive portion 213 is in contact (ohmic contact) with an impurity region of the semiconductor layer 200 formed without going through a salicide process. However, the present invention is not limited thereto, and the plug 204 may be electrically connected to the semiconductor layer 200 via a silicide layer such as titanium silicide or tungsten silicide locally formed under the plug 204.
In the present embodiment, the semiconductor component 1001 includes a digital circuit and the semiconductor component 1002 includes an analog circuit, but the semiconductor component 1001 may include an analog circuit and the semiconductor component 1002 may include a digital circuit. The photoelectric conversion portion 220 provided in the semiconductor layer 200 is connected to the floating diffusion 221 via the gate electrode 202. The floating diffusion 221 is connected to the gate electrode of a source follower transistor of the above-described pixel circuit. An analog pixel signal is output from the source of the source follower transistor. The pixel circuit including the gate electrode 202 and the source follower transistor may be an analog circuit included in the semiconductor component 1002. The analog pixel signal is A/D converted into a digital pixel signal by an A/D conversion circuit. The digital pixel signal is processed by a digital signal processing circuit (DSP). The digital signal processing circuit, which performs image processing, may be an image processing circuit (ISP). The digital signal processing circuit may be a circuit arranged in the semiconductor component 1001. Other examples of a digital circuit arranged in the semiconductor component 1002 include an interface circuit for low voltage differential signaling (LVDS), a mobile industry processor interface (MIPI), and the like.
In the photoelectric conversion apparatus 930 of the present embodiment, a dielectric film 500 including a dielectric 511, a dielectric 512, and a dielectric 513 is arranged on the light receiving surface 252 of the semiconductor layer 200. The dielectric film 500 may have a stacked structure including the plurality of dielectrics 511 to 513 as illustrated in
As the dielectric 511, a metal oxide having a negative fixed charge may be used. By arranging the dielectric 511 having a negative fixed charge in the vicinity of the semiconductor layer 200, noise caused by electronics generated in the vicinity of the semiconductor layer 200 can be reduced. As the dielectric 511 having a negative fixed charge, for example, a material such as hafnium oxide, aluminum oxide, zirconium oxide, titanium oxide, tantalum oxide, or ruthenium oxide is used. For example, the dielectric 511 may be hafnium oxide or aluminum oxide. The thickness of the dielectric 511 may be, for example, 5 nm to 20 nm. In the configuration illustrated in
The dielectric 512 may function as an antireflection layer. When the dielectric 512 is used as an antireflection layer, the thickness of the dielectric 512 may be greater than the thickness of the dielectric 511. When the dielectric 512 is used as an antireflection layer, the thickness of the dielectric 512 may be, for example, within 20 nm to 100 nm. As the dielectric 512, a metal oxide layer such as hafnium oxide, aluminum oxide, zirconium oxide, titanium oxide, tantalum oxide, or ruthenium oxide may be used. In addition, a silicon compound such as silicon oxide, silicon nitride, or silicon oxynitride may be used for the dielectric 512. Since tantalum oxide has the highest dielectric constant among these dielectrics, tantalum oxide may be used for the dielectric 512 that functions as an antireflection layer.
For the dielectric 513, a material having a lower refractive index than the dielectric 512 is used to provide the dielectric 512 with appropriate antireflection performance. As the dielectric 513, a silicon compound such as silicon oxide, silicon nitride, or silicon oxynitride may be used, or a resin material may be used.
A color filter 514 and microlenses 515 are arranged on the dielectric film 500. Further, for example, a light-shielding film for forming optical black (OB) regions may be provided between the dielectric film 500 and the color filter 514 and the microlens 515 using a metal such as tungsten. Further, for example, the dielectric film 500 or the color filter 514 may be provided with a light shielding wall for separating light between the photoelectric conversion elements 222.
Next, an advantage of the present embodiment will be described with reference to
In the process of thinning the semiconductor layer 200, for example, machine grinding is performed while measuring the film thickness of the semiconductor layer 200 using reflected light of light irradiated onto the light receiving surface 252 of the semiconductor layer 200. That is, the semiconductor layer 200 is thinned while the film thickness of the semiconductor layer 200 is monitored according to a reflection spectrum of the light entering from the light receiving surface 252 of the semiconductor layer 200 and reflected by the wiring layers 205 and 207, the conductive layers 211 and 214, and the like. Thereby, the flatness of the light receiving surface 252 and the film thickness uniformity of the semiconductor layer 200 can be determined. Here, the thinning process is not limited to the machine grinding method, and a CMP method or a wet etching method may be used. In either method, the thickness of the semiconductor layer 200 is measured by using reflected light of light irradiated onto the light receiving surface 252, and thereby the end of the thinning of the semiconductor layer 200 can be detected.
A cross section of the photoelectric conversion apparatus 930 according to the present embodiment is illustrated in
In the present embodiment, the pattern density of the wiring patterns 601 arranged in the wiring layer 205 closest to the main surface 251 of the semiconductor layer 200 is improved. On the other hand, as illustrated in
Further, for example, the difference between the pattern density in an arbitrary 100 μm2 region of the wiring patterns 601 arranged in the pixel region 1052 among the plurality of wiring patterns 601 arranged in the wiring layer 205 which is the closest to the main surface 251 of the semiconductor layer 200, and the pattern density in an arbitrary 100 μm2 region of the wiring patterns 601 arranged in the peripheral region 1051 among the plurality of the wiring patterns 601 may be 5% or less. In the pixel region 1052 and the peripheral region 1051, the pattern density of the wiring patterns 601 arranged in the wiring layer 205 which is the closest to the semiconductor layer 200 does not significantly differ. As a result, the signal caused by the wiring patterns 601 arranged in the wiring layer 205 included in the reflection spectrum does not significantly differ between the pixel region 1052 and the peripheral region 1051, and therefore the accuracy of monitoring the film thickness of the semiconductor layer 200 can be stabilized. In addition, variations in thinning caused by a density difference between the underlying patterns of the pixel region 1052 and the peripheral region 1051 can be suppressed.
Next, an example of arrangement of the wiring patterns 601 will be described with reference to
In the configuration illustrated in
Here, the wiring pattern 601a may be a dummy pattern. The dummy pattern may be, for example, a floating wiring pattern that is not connected to another wiring pattern. The dummy pattern may be, for example, a wiring pattern in which one end is connected to a signal line or the like, but the other end is not connected to another wiring pattern or the like. The dummy pattern may be a pattern that is not used for applications such as signal transmission and power supply. A dummy pattern is arranged as the wiring patterns 601 in a region where there are few wiring patterns used for signal transmission, power supply, or the like. As a result, as described above, the thickness of the semiconductor layer 200 in the thinning process can be accurately controlled.
In the configuration illustrated in
Next, another example of arrangement of the wiring patterns 601 will be described with reference to
As illustrated in
As illustrated in
Next, another example of arrangement of the wiring patterns 601 will be described with reference to
As illustrated in
Incidentally, as illustrated in
That is, prior to the dicing process, the plurality of wiring patterns 601 arranged in the wiring layer 205 which is closest to the main surface 251 of the semiconductor layer 200 may include wiring patterns 601f arranged in the scribe region 1053. In such a case, prior to the dicing process, pattern density of wiring patterns 601f arranged in a scribe region 1053 among the plurality of wiring patterns 601 arranged in the wiring layer 205 closest to the main surface 251 of the semiconductor layer 200 may be 35% or more in an arbitrary 100 μm2 region. As a result, the pattern density of the wiring patterns 601 arranged in the wiring layer 205 in the scribe region 1053 is improved, and the thickness of the semiconductor layer 200 can be controlled in the thinning process with high accuracy.
Also, prior to the dicing process, the plurality of wiring patterns 601 arranged in the wiring layer 205 which is the closest to the main surface 251 of the semiconductor layer 200 may include wiring patterns 601 which are arranged to straddle adjacent chips (the photoelectric conversion apparatus 930). Here, the scribe region 1053 after dicing may constitute a part of the peripheral region 1051. Therefore, in this case, after dicing, a wiring pattern 601 may be in contact with the outer edge of the semiconductor layer 200.
An application example of the photoelectric conversion apparatus 930 of the present embodiment will be described with reference to
Hereinafter, the device 9191 including the photoelectric conversion apparatus 930 illustrated in
The device 9191 may include at least one of the optical apparatus 940, the control apparatus 950, the processing apparatus 960, the display apparatus 970, the storage apparatus 980, and the mechanical apparatus 990. The optical apparatus 940 corresponds to the photoelectric conversion apparatus 930. The optical apparatus 940 is, for example, a lens, a shutter, or a mirror. The control apparatus 950 controls the photoelectric conversion apparatus 930. The control apparatus 950 is, for example, a semiconductor apparatus such as an ASIC.
The processing apparatus 960 processes a signal outputted from the photoelectric conversion apparatus 930. The processing apparatus 960 is a semiconductor apparatus such as a CPU or an ASIC for constituting an AFE (analog front end) or a DFE (digital front end). The display apparatus 970 is an EL display apparatus or a liquid crystal display apparatus that displays information (images) obtained by the photoelectric conversion apparatus 930. The storage apparatus 980 is a magnetic device or a semiconductor device that stores information (images) obtained by the photoelectric conversion apparatus 930. The storage apparatus 980 is a volatile memory such as an SRAM or a DRAM, or a nonvolatile memory such as a flash memory or a hard disk drive.
The mechanical apparatus 990 includes a movable portion such as a motor or an engine, or a propulsion portion. In the device 9191, a signal outputted from the photoelectric conversion apparatus 930 is displayed on the display apparatus 970 or transmitted to the outside by a communication apparatus (not illustrated) included in the device 9191. For this, the device 9191 may further comprise the storage apparatus 980 and the processing apparatus 960 separately from the storage circuit and the arithmetic circuit included in the photoelectric conversion apparatus 930. The mechanical apparatus 990 may be controlled based on a signal outputted from the photoelectric conversion apparatus 930.
The device 9191 is suitable for an electronic device such as an information terminal (for example, a smartphone or a wearable terminal) having a capture function or a camera (for example, an interchangeable lens camera, a compact camera, a video camera, or a surveillance camera). The mechanical apparatus 990 in the camera may drive components of the optical apparatus 940 for zooming, focusing, and shutter operations. Alternatively, the mechanical apparatus 990 in the camera may move the photoelectric conversion apparatus 930 for an image stabilization operation.
In addition, the device 9191 may be a transport device such as a vehicle, a ship, or an airplane. The mechanical apparatus 990 in the transportation equipment may be used as a moving apparatus. The device 9191 serving as a transportation device is suitable for transporting the photoelectric conversion apparatus 930 or for assisting and/or automating driving (steering) by an image capture function. The processing apparatus 960 for assisting and/or automating driving (steering) can perform processing for operating the mechanical apparatus 990 as a moving apparatus based on information obtained by the photoelectric conversion apparatus 930. Alternatively, the device 9191 may be a medical device such as an endoscope, a measurement device such as a distance measuring sensor, an analytical device such as an electron microscope, or an office device such as a copying machine.
The embodiments described above can be appropriately modified without departing from the technical idea. The disclosure of the present specification includes not only the description in the present specification but also all matters that can be understood from the present specification and the drawings attached to the present specification. The content disclosed in this specification includes a complementary set of concepts described in this specification. That is, for example, if there is a description in this specification that “A is B”, even if the description that “A is not B” is omitted, the present specification should be treated as disclosing “A is not B”. This is because the case where “A is B” is being described is premised upon the fact that the case where “A is not B” is being considered.
While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.
This application claims the benefit of Japanese Patent Application No. 2022-143101, filed Sep. 8, 2022, which is hereby incorporated by reference herein in its entirety.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2022-143101 | Sep 2022 | JP | national |
