Patent Application
20240414454
The present invention relates to a photoelectric conversion apparatus, a substrate, and an apparatus.
There is a solid-state imaging device including a delta-sigma (ΔΣ) analog-to-digital conversion circuit. International Publication No. 2019/069614 discloses a solid-state imaging device capable of supporting a wide input voltage range by providing two capacitors, each of which stores a signal from a pixel, and outputting the weighted average of the voltages stored in two capacitors.
In some cases, signals having different voltages are read out from one pixel, and each signal undergoes analog-to-digital conversion and is output. Due to readout and conversion of different signals, the length of time required for the readout and conversion poses sometimes a problem.
One disclosed embodiment has been made in consideration of the above-described problem, and provides a technique advantageous in shortening the time required for readout and analog-to-digital conversion of signals from a pixel.
According to one aspect of the disclosure, there is provided a photoelectric conversion apparatus that comprising: a pixel including a photoelectric conversion element, and configured to output two signals having different amplitudes based on incident light to the photoelectric conversion element; a sampling and holding unit configured to sample and hold each of the two signals output from the pixel; and an oversampling analog-to-digital conversion circuit configured to sequentially perform analog-to-digital conversion of each of the sampled and held signals, wherein a period for performing analog-to-digital conversion of a signal having a smaller amplitude among the two signals is set shorter than a period for performing analog-to-digital conversion of a signal having a larger amplitude among the two signals.
Further features of the present invention will become apparent from the following description of exemplary embodiments with reference to the attached drawings.
Hereinafter, embodiments will be described in detail with reference to the attached drawings. Note, the following embodiments are not intended to limit the scope of the claimed invention. Multiple features are described in the embodiments, but limitation is not made to an invention that requires all such features, and multiple such features may be combined as appropriate. Furthermore, in the attached drawings, the same reference numerals are given to the same or similar configurations, and redundant description thereof is omitted.
In this specification, an “amplitude” is sometimes used as an expression indicating the magnitude of a signal. The amplitude indicates the differential voltage between a reference signal and a signal to be described.
In the circuit substrate 2, current sources 40, sampling and holding units 50, converters 60, a controller 70, a data processor 90, and an output unit 100 are arranged. The current source 40 is arranged in correspondence with each vertical signal line 30. The current source 40 supplies, via the vertical signal line 30, a bias current to the pixel 10 selected to read out a signal. The vertical signal line 30 transfers a signal corresponding to signal charges generated by the photoelectric conversion element of the pixel 10 from the pixel 10 to the sampling and holding unit 50.
The sampling and holding unit 50 samples and holds the signal generated by the photoelectric conversion element of each pixel 10 from the pixel region 5 via the vertical signal line 30. In this embodiment, the sampling and holding unit 50 includes two sampling and holding circuits. The first sampling and holding circuit samples and holds a signal which corresponds to the reset level upon resetting the photoelectric conversion element. The second sampling and holding circuit samples and holds a signal which corresponds to an image signal obtained when a photoelectric conversion operation is performed in the photoelectric conversion element. Each of the first sampling and holding circuit and the second sampling and holding circuit is provided to each vertical signal line 30.
The converter 60 includes an analog-to-digital conversion circuit that performs analog-to-digital conversion of the signal output from the sampling and holding unit 50. The converter 60 is provided in correspondence with each vertical signal line 30. Here, as the analog-to-digital conversion circuit, a slope analog-to-digital conversion circuit, a successive approximation type analog-to-digital conversion circuit, a delta-sigma (42) analog-to-digital conversion circuit, or the like is used, but the analog-to-digital conversion circuit is not limited thereto. An oversampling analog-to-digital conversion circuit is preferably used.
The controller 70 supplies, to the converter 60, a control signal Adres and a clock signal Clk, which will be described later. The data processor 90 processes a digital signal output from the converter 60. The data processor 90 can perform digital processing such as correction processing or interpolation processing on the digital signal output from the converter 60. The output unit 100 externally outputs the signal processed by the data processor 90.
The other of the main electrodes of the photoelectric conversion element 400 is electrically connected to the gate electrode of the amplification transistor 430 via the transfer transistor 410. A node 420, to which the gate electrode of the amplification transistor 430 is electrically connected, functions as a floating diffusion. The floating diffusion can operate as a charge-voltage converter that converts the signal charges generated by the photoelectric conversion element 400 into a signal voltage.
A transfer signal TX is supplied to the gate electrode of the transfer transistor 410. When the transfer transistor 410 is set in a conductive state in accordance with the transfer signal TX, the signal charges accumulated in the photoelectric conversion element 400 are transferred to the node 420 serving as the floating diffusion.
The reset transistor 455 is connected between a power supply potential 460 and the node 420. Note that the expression that “a transistor is connected between A and B” represents a state in which one of the main electrodes (source and drain) of the transistor is connected to A and the other of the main electrodes is connected to B. The gate electrode of the transistor is connected to neither A nor B.
A reset signal RES is supplied to the gate electrode of the reset transistor 455. When the reset transistor 455 is set in a conductive state in accordance with the reset signal RES, the potential of the node 420 serving as the floating diffusion is reset to the power supply potential 460, and the charges held by the floating diffusion are swept out. The pixel is reset by this reset operation.
The gate electrode of the amplification transistor 430 is connected to the node 420, one of the main electrodes thereof is connected to the power supply potential 460, and the other of the main electrodes thereof is connected to the selection transistor 440. The gate electrode of the amplification transistor 430 serves as the input section of a source follower circuit that reads out the signal obtained from the photoelectric conversion by the photoelectric conversion element 400. The other of the main electrodes of the amplification transistor 430 is connected to the vertical signal line 30 via the selection transistor 440. The amplification transistor 430 and the current source 40 connected to the vertical signal line 30 form a source follower that converts the voltage of the node 420 into the potential of the vertical signal line 30.
The selection transistor 440 is connected between the amplification transistor 430 and the vertical signal line 30. A selection signal SEL is supplied to the gate electrode of the selection transistor 440. When the selection transistor 440 is set in a conductive state in accordance with the selection signal SEL, the pixel 10 is set in a selected state. In the selected state, the signal is output from the pixel 10 to the vertical signal line 30 via the amplification transistor 430.
The circuit arrangement of the pixel 10 is not limited to the arrangement shown in
In the pixel 10, when the control signal RES is applied, the potential of the node 420 is reset by the reset transistor 455. When the pixel is reset, a signal at the reset level corresponding to the reset level upon resetting the photoelectric conversion element 400 can be output from the pixel 10. In addition, after the photoelectric conversion element 400 photoelectrically converts incident light, a data signal that can correspond to an image signal, which is generated by performing photoelectric conversion in accordance with the incident light to the photoelectric conversion element 400, can be output from the pixel.
The sampling and holding unit 50 includes a first sampling and holding circuit 210 and a second sampling and holding circuit 211. As will be described later, the first sampling and holding circuit 210 samples and holds the signal at the reset level output from the pixel when the photoelectric conversion element 400 is reset. The second sampling and holding circuit 211 samples and holds a data signal generated in accordance with incident light to the photoelectric conversion element. The output of the sampling and holding unit 50 is input to the converter 60 via a switch 252. The switch 252 is controlled to be turned on/off by a signal Adin.
The first sampling and holding circuit 210 includes a capacitor 120 and an inverting amplifier 220. A switch 110 controls the connection between the vertical signal line 30 and the capacitor 120 in accordance with a control signal Smp_n. The inverting amplifier 220 can be formed by a combination of a common source amplifier circuit and a source follower circuit. The inverting amplifier 220 includes transistors 130, 140, 150, 160, and 230, switches 170, 180, and 190, and a current source 200. The switch 170 is connected between the input and output of the common source amplifier circuit formed by the transistors 130, 140, 150, and 160, and controlled by a control signal Smpa_n. The signal from the inverting amplifier 220 can be output in accordance with a control signal Hld_n.
The second sampling and holding circuit 211 can have almost the same arrangement as the first signal sampling and holding circuit 210, but is different from the first sampling and holding circuit 210 mainly in that switches 112 and 192 and a capacitor 122 are added. The second sampling and holding circuit 211 includes capacitors 121 and 122, each of which holds the signal from the vertical signal line 30, and an inverting amplifier 221. A switch 111 and the switch 112 control the connection between the vertical signal line 30 and the capacitors 121 and 122 in accordance with control signals Smp_s1 and Smp_s2, respectively.
Similar to the inverting amplifier 220, the inverting amplifier 221 can be formed by a combination of a common source amplifier circuit and a source follower circuit. The inverting amplifier 221 includes transistors 131, 141, 151, 161, and 231, switches 171, 181, and 191, the switch 192, and a current source 201. The switch 171 is connected between the input and output of the common source amplifier circuit formed by the transistors 131, 141, 151, and 161, and controlled by a control signal Smpa_s. The signal from the inverting amplifier 221 is output in accordance with a control signal Hld_s1 or Hld_s2.
A resistor 240 is arranged between the output terminal of the first sampling and holding circuit 210 and the output terminal of the second sampling and holding circuit 211. Consider a case where the first sampling and holding circuit 210 outputs a signal at the reset level, and the second sampling and holding circuit 211 outputs a data signal. Let Vn be the potential at the output terminal of the first sampling and holding circuit 210, that is, the potential of the signal at the reset level, and Vs be the potential at the output terminal of the second sampling and holding circuit 211, that is, the potential of the data signal. Let R be the resistance value of the resistor 240. Accordingly, a current I flowing through the resistor 240 is expressed as:
The current I is input to the converter 60. At this time, the current I flowing through the resistor 240 is proportional to the difference between the potential Vn of the signal at the reset level of the pixel signal and the potential Vs of the data signal. Hence, correlated double sampling (CDS) is performed at the stage in which the current I is input to the converter 60.
The current corresponding to the differential voltage between the output terminal of the first sampling and holding circuit 210 and the output terminal of the second sampling and holding circuit 211 is input to the converter 60 via the switch 252 controlled by the signal Adin.
The converter 60 includes an oversampling analog-to-digital conversion circuit, for example, a ΔΣ analog-to-digital conversion circuit. The ΔΣ analog-to-digital conversion circuit includes a first integrator, a second integrator, a quantizer 370, and a decimation filter 380. In the converter 60, the first integrator is formed by an integral capacitor 320. The second integrator is formed by a voltage-current conversion circuit (Gm cell) 330, which converts a voltage into a current, and an integral capacitor 360. A digital-to-analog converter 305 including a current source 300 and a switch 310 is connected the input node of the first integrator.
In accordance with a digital signal via the second integrator and the quantizer 370, the digital-to-analog converter 305 controls the current to the first integrator. A digital-to-analog converter 345 including a current source 340 and a switch 350 is connected to the input node of the second integrator. The digital-to-analog converter 345 controls the current to the second integrator in accordance with the result obtained by quantizing the output of the second integrator by the quantizer 370. The clock signal Clk is input to the quantizer 370, and the quantization operation is performed in synchronization with the clock signal Clk.
In the converter 60, the quantizer 370 performs an operation of feeding back the preceding quantization value to the second integrator and the first integrator through the digital-to-analog converters 305 and 345. In this manner, by passing the preceding quantization value through the integrators twice while feeding it back to the digital-to-analog converters 305 and 345, a secondary noise shaping characteristic can be obtained. Furthermore, by removing high-frequency noise by the decimation filter 380 arranged at the succeeding stage of the quantizer 370, an accurate analog-to-digital conversion output can be obtained. Note that a switch 390 is connected between the inverting input terminal and output terminal of the Gm cell 330. The switch 390 is controlled by the control signal Adres. By turning on the switch 390, each node of the first integrator and the second integrator can be set in a reset state.
With reference to
In the period from time t1 to time t2, the control signal RES shown in
In the period from time t1 to time t4, the control signal Adin is at low level so that the switch 252 is in the OFF state. Thus, the second sampling and holding circuit 211 is not connected to the converter 60. Furthermore, the control signal Adres is at high level so that the switch 390 is in the ON state. Thus, the input and output terminals of the Gm cell 330 is short-circuited, and each node of the first integrator and the second integrator is in the reset state in the converter 60. The clock signal Clk is at low level, and the quantizer 370 is in a state of not performing the quantization operation.
In the period from time t5 to time t6, the control signal TX shown in
Accordingly, the potential of the vertical signal line 30 changes to a potential Vs1 of the first data signal. In addition, at time t5, the control signals Smpa_s and Smp_s1 are set at high level, and the switches 111 and 171 are turned on in the second sampling and holding circuit 211 for data signal. Then, at time t7 when the control signal Smpa_s transitions from high level to low level, the switch 171 is turned off, and the potential Vs1 corresponding to the first data signal is sampled and accumulated in the capacitor 121. Then, at time t8, the control signal Smp_s1 transitions from high level to low level, and the switch 111 is turned off to disconnect the capacitor 121 from the vertical signal line 30.
Note that the voltage across the switch 171 upon turning off the switch 171 at time t7 is always approximately the same regardless of the potential of the vertical signal line 30. Therefore, charge injection caused by turning off the switch 171 does not occur, so an error voltage is not generated with respect to the potential Vs1 of the first data signal accumulated in the capacitor 121. Further, when turning off the switch 111 at time t8, both ends of the capacitor 121 are in a high impedance state. Accordingly, there is no influence caused by turning off the switch 111. In this manner, generation of an error voltage with respect to the potential Vs1 of the first data signal can be suppressed.
In the period from time t9 to time t10, the control signal TX shown in
Then, at time t11 when the control signal Smpa_s transitions from high level to low level, the potential Vs2 of the second data signal is sampled and accumulated in the capacitor 122. Then, at time t12, the control signal Smp_s2 transitions from high level to low level, and the switch 112 is turned off to disconnect the capacitor 122 from the vertical signal line 30.
Note that the voltage across the switch 171 upon turning off the switch 171 at time t11 is always approximately the same regardless of the potential of the vertical signal line 30. Therefore, an error voltage is not generated with respect to the potential Vs2 of the second data signal accumulated in the capacitor 122 by charge injection caused by turning off the switch 171. Further, when turning off the switch 112 at time t12, since both ends of the capacitor 122 are in a high impedance state, there is no influence caused by turning off the switch 112. In tins manner, generation of an error voltage with respect to the potential Vs2 of the second data signal can be suppressed.
At time t13, the control signal Hld_n is set at high level and the switches 180 and 190 are turned on, so that the capacitor 120 outputs the potential Vn of the signal at the reset level in the first sampling and holding circuit 210. Simultaneously, at time t13, the control signals Hld_s1 and Hld_s are also set at high level and the switches 181 and 191 are turned on, so that the capacitor 121 outputs the potential Vs1 of the first data signal in the second sampling and holding circuit 211. Simultaneously, at time t13, the control signal Adin is also set at high level, so that the sampling and holding unit 50 is connected to the converter 60. Furthermore, simultaneously, at time t13, the control signal Adres is set at low level, the switch 390 is turned off, and the reset state of each node of the first integrator and the second integrator is canceled.
As has been described above, the input current to the converter 60 is a current corresponding to the difference between the potential Vn of the signal at the reset level at the output terminal of the first sampling and holding circuit 210 and the potential Vs1 of the first data signal at the output terminal of the second sampling and holding circuit 211. The converter 60 performs analog-to-digital conversion of the current corresponding to the difference between the potential Vn and the potential Vs1.
In the period from time t13 to time t14, a clock operation driven by the clock signal Clk is enabled, and a quantization operation is performed by the quantizer 370 in each clock cycle. As has been described above, by passing the preceding quantization value through the integrators twice while feeding it back to the digital-to-analog converters 305 and 345 in each clock cycle, a secondary noise shaping characteristic can be obtained. Furthermore, by removing high-frequency noise by the decimation filter 380 arranged at the succeeding stage of the quantizer 370, an accurate analog-to-digital conversion output can be obtained.
At time t14, the analog-to-digital conversion of the signal corresponding to the potential Vs1 of the first data signal of the second sampling and holding circuit 211 is completed. Simultaneously, the control signal Adin is set at low level to turn off the switch 252. With this, the sampling and holding unit 50 is disconnected from the converter 60. Furthermore, simultaneously, at time t14, the control signal Adres is set at high level and the switch 390 is turned on, so that each node of the first integrator and the second integrator is reset.
Furthermore, simultaneously, at time t14, the clock operation driven by the clock signal Clk is temporarily stopped. In the period from time t14 to time t15, the sampling and holding unit 50 is disconnected from the converter 60, the reset state of each node of the first integrator and the second integrator is reset by the control signal Ares, and the state in which the clock operation is stopped is set as indicated by the clock signal Clk. In this manner, the period from time t13 to time t14 where the clock signal is supplied is the analog-to-digital conversion period, and the period from time t14 to time t15 is the analog-to-digital conversion stop period or the analog-to-digital converter reset period.
As has been described above, in the analog-to-digital conversion period, the sampling and holding unit 50 is connected to the converter 60, and a signal current can be input from the sampling and holding unit 50 to the converter 60. In addition, in the analog-to-digital conversion period, the control signal Adres is at low level, and the reset state of each node of the first integrator and the second integrator is canceled. Furthermore, in the analog-to-digital conversion period, the clock operation driven by the clock signal Clk is enabled.
At time t15, the control signal Adin is set at high level, and the sampling and holding unit 50 is connected to the converter 60. In addition, when the control signal Hld_s2 is set at high level and the switch 192 is turned on at time t15, the capacitor 122 outputs the potential Vs2 of the second data signal in the second sampling and holding circuit 211. With this, a current corresponding to the difference between the potential Vn of the signal at the reset level at the output terminal of the first sampling and holding circuit 210 and the potential Vs2 of the second data signal at the output terminal of the second sampling and holding circuit 211 is input to the converter 60. The converter 60 performs analog-to-digital conversion of this current. In the period from time t15 to time t16, the control signal Adres is set at low level, and the clock operation driven by the clock signal Clk is enabled. During this period, as in the case of the first data signal, analog-to-digital conversion of the signal corresponding to the potential Vs2 of the second data signal of the second sampling and holding circuit 211 is performed.
Here, the potential Vs1 of the first data signal and the potential Vs2 of the second data signal are signals corresponding to different accumulation times (exposure times). Therefore, the amplitudes are not the same except for a dark state where exposure is not performed. Since the exposure period (time t2 to time t10) of the second data signal is longer than the exposure period (time t2 to time t6) of the first data signal, unless the amount of incident light to the photoelectric conversion element 400 largely changes, the potential Vs2 has a larger amplitude than the potential Vs1. In this embodiment, the analog-to-digital conversion period of the potential Vs1 of the first data signal is set shorter than the analog-to-digital conversion period of the potential Vs2 of the second data signal. More specifically, in
With this, during the period from time t13 to time t14, the number of clock cycles of the clock signal Clk is decreased, thereby reducing the oversampling rate. The oversampling analog-to-digital conversion circuit can perform analog-to-digital conversion even if the number of cycles is changed and the period required for analog-to-digital conversion is shortened. A possible negative effect of this is that the gradation of analog-to-digital conversion decreases due to an increase in noise. However, decreasing the gradation of analog-to-digital conversion of the signal on the small amplitude side is allowable. Therefore, by shortening the analog-to-digital conversion period of the signal on the small amplitude side, this embodiment can suppress speed reduction of the analog-to-digital conversion while ensuring the accuracy of analog-to-digital conversion of the signal on the large amplitude side.
Note that in
Note that the resistor 240 between the output terminal of the first sampling and holding circuit 210 and the output terminal of the second sampling and holding circuit 211 may be a variable resistor. That is, the level to the converter 60 may be adjustable in accordance with the resistance value. The resistance value of the resistor 240 is changed between the period from time t13 to time t14 in which the potential Vs1 of the first data signal is read from the capacitor 121 and the period from time t15 to time t16 in which the potential Vs2 of the second data signal is read from the capacitor 122. By changing the resistance value, noise reduction or power reduction corresponding to the amplitude level can be implemented. This will be described below.
If the resistance value is made relatively smaller in the period from time t13 to time t14 than in the period from time t15 to time t16, the noise of the first data signal can be reduced by reducing the thermal noise generated by the resistor 240. On the other hand, if the resistance value in the period from time t13 to time t14 is made relatively larger than in the period from time t15 to time t16, the output current to the converter 60 can be decreased, thereby implementing power reduction.
In addition, in this embodiment, by sharing the second sampling and holding circuit 211 between the capacitor 121 and the capacitor 122, it is possible to read out the respective potentials Vs1 and Vs2 of two data signals (the first data signal and the second data signal) without increasing the operating power. Further, as has been described above, the error voltage with respect to the respective potentials Vs1 and Vs2 of two data signals can be suppressed, so that degradation of the image quality in HDR image capturing can be suppressed.
Furthermore, since the respective potentials Vs1 and Vs2 of two data signals are read out using the common resistor 240, level fluctuations caused by temperature and process variations are easily synchronized. With this, for example, superimposition of different variations on the respective potentials Vs1 and Vs2 of the data signals can be suppressed, thereby suppressing degradation of the image quality of an HDR image.
Note that, as shown in
A pair of the first sampling and holding circuit 210 and the second sampling and holding circuit 211 is referred to as the first sampling and holding unit, and a pair of the third sampling and holding circuit 215 and the fourth sampling and holding circuit 216 are referred to as the second sampling and holding unit. It is assumed that the first sampling and holding unit is arranged in correspondence with a pixel in a predetermined row, and the second sampling and holding unit is arranged in correspondence with a pixel in another row. The first sampling and holding unit and the second sampling and holding unit can perform an analog-to-digital conversion operation and a sampling and holding operation in overlapping periods. With this, the readout operation period can be further shortened. This will be described later.
In
A more detailed description will be given using the timing chart of
Note that at this time, the switches 250, 251, and 252 are set in the ON state and the switches 255, 256, and 257 are set in the OFF state. Furthermore, in this embodiment, at time t4, sampling of a potential Vn′ of the signal at the reset level of the pixel in the next row to the third sampling and holding circuit 215 is started. In this manner, the first sampling and holding circuit 210 and the second sampling and holding circuit 211 are connected to the converter 60 and analog-to-digital conversion is performed. In the period overlapping the analog-to-digital conversion, readout of signals of the next pixel to the third sampling and holding circuit 215 and the fourth sampling and holding circuit 216 is started. In the above manner, the first sampling and holding unit and the second sampling and holding unit can perform the analog-to-digital conversion operation and the sampling and holding operation in the overlapping periods. With this, further speed reduction of the readout operation can be suppressed.
A photoelectric conversion apparatus according to this embodiment will be described with reference to the schematic view of
In the timing chart of
In the period from time t13 to time t14, analog-to-digital conversion of the difference signal between the first data signal and the signal at the reset level is performed, and in the period from time t15 to time t16, analog-to-digital conversion of the difference signal between the second signal and the signal at the reset level is performed. By calculating the difference between the first data signal and the second data signal by a data processor 90 at the succeeding stage, a digital signal for the signal generated by each of the photoelectric conversion elements 400 and 401 can be obtained. A period S1_AD required for analog-to-digital conversion of the first data signal is set shorter than a period S2_AD required for analog-to-digital conversion of the second data signal. With the operation as described above, pixel signals for two rows can be read out in a unit readout period, and the time required for readout can be shortened.
In this embodiment, as in the first embodiment, the period from time t13 to time 14 is set shorter than the period from time t15 to time t16. With this, the time required for readout can be shortened while ensuring the accuracy of analog-to-digital conversion of the signal on the large amplitude side.
The photoelectric conversion elements 400 and 401 may be a pair of photoelectric conversion elements formed under the same microlens arranged in correspondence with the pixel. In this case, by two photoelectric conversion elements 400 and 401, a phase difference signal corresponding to the image phase difference caused by incident light to the photoelectric conversion elements 400 and 401 can be generated. In this case, the first data signal may be used as an autofocus (AF) signal, and the second data signal may be used as an image signal. In this case, the period required for analog-to-digital conversion of the autofocus (AF) signal can be set shorter than the period require for analog-to-digital conversion of the image signal. Although the analog-to-digital conversion accuracy of the autofocus signal becomes lower than the analog-to-digital conversion accuracy of the image signal, the analog-to-digital conversion accuracy of the image signal can be ensured. In addition, the time required for readout can be shortened.
Assume that the first data signal is a signal corresponding to one photoelectric conversion element, and the second data signal is a signal corresponding to two photoelectric conversion elements. The range of the signal amplitude of the first data signal is smaller than the range of the signal amplitude of the second data signal corresponding to two photoelectric conversion elements. This is because two photoelectric conversion elements can hold a larger amount of photo charges than one photoelectric conversion element. The photoelectric conversion elements 400 and 401 may be photodiodes having different areas. Since a large photodiode and a small photodiode can hold different amounts of photo charges, they output signals having different ranges of the signal amplitudes, as in the example of the phase difference detection pixel described above.
Note that, also in this embodiment, as shown in
Note that, in the first embodiment, a description has been given while taking, as an example, the case where one converter 60 is connected to one sampling and holding unit 50, but the present invention is not limited to this. For example, as shown in
In the period from time t1 to time t2, each of the sampling and holding units 50 to 53 samples the signal at the reset level. In the period from time t2 to time t3, each of the sampling and holding units 50 to 53 samples the first data signal. In the period from time t3 to time t4, each of the sampling and holding units 50 to 53 samples the second data signal. In the period from time t4 to time t8, the multiplexer 500 sequentially connects the sampling and holding units 50 to 53 to the converter 60, thereby serially performing analog-to-digital conversion of the first data signals from the sampling and holding units 50 to 53, respectively.
In the period from time t8 to time t12, the multiplexer 500 sequentially connects the sampling and holding units 50 to 53 to the converter 60, thereby serially performing analog-to-digital conversion of the second data signals from the sampling and holding units 50 to 53, respectively. In this case, the effect of shortening the analog-to-digital conversion period of the first data signal increases fourfold. Accordingly, the time required for readout can be further shortened. In addition, by setting the sampling and holding period and the analog-to-digital conversion period so as to overlap each other as in the third embodiment, the period required for readout and conversion can be further shortened.
The following is a description of an apparatus 1000 that includes a semiconductor apparatus 1100 including a package 1020 on which a semiconductor chip 1110 including a semiconductor integrated circuit is mounted, as shown in
The apparatus 1000 can include at least one of an optical apparatus 1040, a control apparatus 1050, a processing apparatus 1060, a display apparatus 1070, a storage apparatus 1080, and a mechanical apparatus 1090. The optical apparatus 1040 is implemented by, for example, a lens, a shutter, and a mirror. The control apparatus 1050 controls the semiconductor chip 1110. The control apparatus 1050 is, for example, a semiconductor device such as an ASIC.
The processing apparatus 1060 processes a signal output from the photoelectric conversion apparatus included in the semiconductor chip 1110. The processing apparatus 1060 is a semiconductor device such as a CPU or an ASIC for forming an Analog Front End (AFE) or a Digital Front End (DFE). For example, an image may be generated based on event signals E. The display apparatus 1070 is an Electroluminescent (EL) display device or a liquid crystal display device that displays an information image obtained by the semiconductor chip 1110. The storage apparatus 1080 is a magnetic device or a semiconductor device that stores the information image obtained by the semiconductor chip 1110. The storage apparatus 1080 is a volatile memory such as an SRAM or a DRAM, or a nonvolatile memory such as a flash memory or a hard disk drive.
The mechanical apparatus 1090 includes a moving or propulsion unit such as a motor or an engine. In the apparatus 1000, the signal output from the semiconductor chip 1110 is displayed on the display apparatus 1070 or transmitted to an external apparatus by a communication apparatus (not shown) included in the apparatus 1000. Hence, the apparatus 1000 may further include the storage apparatus 1080 and the processing apparatus 1060 in addition to the memory circuits and arithmetic circuits included in the semiconductor chip 1110. The mechanical apparatus 1090 may be controlled based on the signal output from the semiconductor chip 1110.
In addition, the apparatus 1000 is suitable for an electronic apparatus such as an information terminal (for example, a smartphone or a wearable terminal) which has a shooting function or a camera (for example, an interchangeable lens camera, a compact camera, a video camera, or a surveillance camera). The mechanical apparatus 1090 in the camera can drive the components of the optical apparatus 1040 in order to perform zooming, an in-focus operation, and a shutter operation. Alternatively, the mechanical apparatus 1090 in the camera can move the optical apparatus 1040 in order to perform an anti-vibration operation.
Furthermore, the apparatus 1000 can be a transportation apparatus such as a vehicle, a ship, or an airplane. The mechanical apparatus 1090 in the transportation apparatus can be used as a moving apparatus. The apparatus 1000 as the transportation apparatus is suitable for an apparatus that transports the semiconductor chip 1110 or an apparatus that uses a shooting function to assist and/or automate drive steering. The processing apparatus 1060 for assisting and/or automating drive steering can perform, based on the information obtained by the semiconductor chip 1110, processing for operating the mechanical apparatus 1090 as a moving apparatus. Alternatively, the apparatus 1000 may be a medical apparatus such as an endoscope, a measurement apparatus such as a distance measurement sensor, an analysis apparatus such as an electron microscope, an office apparatus such as a copy machine, or an industrial apparatus such as a robot.
Note that the forms of the imaging device and the photoelectric conversion apparatus are not limited to those described above. For example, the pixel 10 is not limited to the form shown in
While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.
This application claims the benefit of Japanese Patent Application No. 2023-093307 filed Jun. 6, 2023, which is hereby incorporated by reference herein in its entirety.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2023-093307 | Jun 2023 | JP | national |
