1. Field of the Invention
The present invention relates to a photoelectric conversion device, a photoelectric conversion system, and a method for driving the photoelectric conversion device.
2. Description of the Related Art
Japanese Patent Application Laid-Open No. 2005-348041 describes an imaging device including an adding circuit and a non-adding circuit. The adding circuit outputs sum signals resulting from addition of signals output from a plurality of pixels. The non-adding circuit outputs signals output by the plurality of pixels without the addition. In Japanese Patent Application Laid-Open No. 2005-348041, the adding circuit and the non-adding circuit are provided only in one region per a pixel array including the plurality of pixels.
Japanese Patent Application Laid-Open No. 2003-18465 describes an imaging device that operates in an adding mode and a non-adding mode. In the adding mode, sum signals resulting from addition of signals output by a plurality of pixels are generated in a region including a plurality of pixels. The sum signals are output from this region to a signal line. In the non-adding mode, a signal is output from each pixel to the signal line.
An aspect of the invention is a photoelectric conversion device, including a light receiving region having a plurality of regions, and first and second signal lines, the regions each including unit cells and a signal output section, the unit cells each including a plurality of photoelectric converters and a cell output section, wherein the cell output section outputs to the first signal line first signals each based on a signal of each of the plurality of photoelectric converters and a second signal based on a sum signal resulting from addition of signals of the plurality of photoelectric converters, the second signal is input from the first signal line to the signal output section, and the signal output section outputs the second signal to the second signal line.
Another aspect of the invention is a photoelectric conversion device, including a light receiving region having a plurality of regions, and first and second signal lines, the regions each including unit cells, an adder section, and a signal output section, the unit cells each including a plurality of photoelectric converters and a cell output section, wherein the cell output section outputs to the first signal line first signals each based on a signal of each of the plurality of photoelectric converters, the first signals are input from the first signal line to each of the adder sections, the adder sections each generate a sum signal resulting from addition of signals of the plurality of photoelectric converters and output the sum signal to each of the signal output sections, and the signal output sections output second signals based on the sum signals to the second signal line.
Still another aspect of the invention is a method for driving a photoelectric conversion device including a plurality of regions provided in a light receiving region and first and second signal lines, the regions each including unit cells, a signal holding section, and a signal output section, the unit cells each including a plurality of photoelectric converters and a cell output section, the method including: outputting to the first signal line by each of the cell output sections of first signals each based on each of signals of the plurality of photoelectric converters and a second signal based on a sum signal resulting from addition of signals of the plurality of photoelectric converters; holding by each of the signal holding sections of the second signals; and outputting to the second signal line by the signal output sections of signals based on the second signals held by the signal holding sections, wherein the signal holding section of one of the regions performs holding the second signal in a period, and the signal holding section of the other one of the regions performs holding the second signal in at least one part period overlapped with the period.
Further features of the present invention will become apparent from the following description of exemplary embodiments (with reference to the attached drawings).
The imaging device in Japanese Patent Application Laid-Open No. 2005-348041 has difficulty in generating the sum signals fast because of the one region including the adding circuit.
In the imaging device in Japanese Patent Application Laid-Open No. 2003-18465, the signal line that receives the sum signals from the region including the plurality of pixels is identical with the signal line that receives the non-sum signals from the region. In the adding mode, the sum signals are output from part of the plurality of pixels to the signal line. Nodes of output switches of the pixels that do not output the sum signals are connected electrically to the signal line. Thus, parasitic components of the output switches of the pixels that do not output the sum signals increase the drive load of the signal line in the non-adding mode. The increased drive load results in a prolonged period from when the pixels start outputting the sum signals to the signal line until the potential of the signal line changes to the potential of the sum signal. Thus, the imaging device in Japanese Patent Application Laid-Open No. 2003-18465 is problematic in that it cannot read the sum signals fast.
Techniques to be described herein have been achieved in light of the problems described above.
Some embodiments will now be described with reference to the drawings.
The photoelectric conversion device 1 outputs a signal based on light from a subject to the calculation section 2. The signal output by the photoelectric conversion device 1 to the calculation section 2 is subjected to analog-to-digital conversion by the A/D converter 4. The memory 5 holds a digital signal resulting from the conversion by the A/D converter 4. Operations of the photoelectric conversion device 1 and the A/D converter 4 are controlled by the system controller 7. The memory 5 also outputs the held signal to the light metering processor 6. The light metering processor 6 meters the subject in a way that is based on the output signal. The system controller 7 controls the constituents of the calculation section 2 and the photoelectric conversion device 1.
The pixel portion 11 includes a plurality of pixels arranged in a matrix. The pixels are provided with photoelectric converters. The primary scan circuit 12 controls reading of an electric charge accumulated in each photoelectric converter, adding of signal electric charges accumulated in the photoelectric converters, and resetting of the photoelectric converters on a basis of per row of the pixel portion 11. Under the control of the primary scan circuit 12, the pixel portion 11 outputs reset level signals and photoelectric conversion signals based on the light from the subject. The readout circuit 13 performs CDS (Correlated Double Sampling) processing on the signals of the pixel portion 11 read by the primary scan circuit 12. Specifically, the readout circuit 13 outputs a signal of difference between a reset level signal and a photoelectric conversion signal. The reset level signal includes offsets inherent to an electrical path from the pixel portion 11 to the readout circuit 13. Through the CDS processing, the readout circuit 13 outputs the photoelectric conversion signals with reduced noise to the output amplifier 15. The secondary scan circuit 14 allows photoelectric conversion signals, which have been subjected to the CDS processing and held in the readout circuit 13, to be output from the readout circuit 13 to the output amplifier 15 sequentially. The output amplifier 15 amplifies a photoelectric conversion signal, which has been subjected to the CDS processing and output by the secondary scan circuit 14 from the readout circuit 13, and outputs the signal as an output signal Vout to the calculation section 2. The output signal Vout is the signal based on the light from the subject and output by the photoelectric conversion device 1 to the calculation section 2. The TG 16 is given an external clock signal CLK. The TG 16 controls operations of the primary scan circuit 12, the readout circuit 13, and the secondary scan circuit 14.
The signal Vout illustrated in
The pixel portion 11 includes a plurality of regions 21. The pixel portion 11 illustrated in
A photodiode of each pixel 24 in the pixel portion 11 illustrated in
The cell section 22 includes a plurality of pixels 24. The pixels 24 each include a photodiode 101 and a transistor 102 that transfers an electric charge accumulated in the photodiode 101. With reference to
A gate of the transistor 102 is connected to the control line 30, which is connected to the primary scan circuit 12 in
A main node of the transistor 105 receives voltage from a power supply line VL2. Another main node of the transistor 105 is connected electrically to the input node of the transistor 103.
Each transistor 102 of the pixels 24 indicated with R1, Gb1, R3, and Gb3 in
In
The transistors 102 in an identical row are connected electrically via a common one of the control lines 30, 31, 32, and 33. The transistors 104 in an identical row are connected electrically via the common control line 34. The transistors 105 in an identical row are connected electrically via the common control line 35.
The input nodes of transistors 103 in an identical column are connected electrically via a transistor 106.
The unit signal processor 23 is provided with columns of a capacitive element 108, and transistors 107 and 109. Each column of the capacitive element 108 and the transistors 107 and 109 is provided in association with a column of the unit cells. The unit signal processor 23 also includes an output amplifier 110.
With reference to
At the time t0, the TG 16 allows the signals φRES1 and φRES2 to achieve the H level. Then, the TG 16 allows the signals φTX1 to φTX8 to achieve the H level. This resets the potentials of the input nodes of the transistors 103 and the photodiodes 101 of all the pixels 24 included in two rows and four columns of the unit cells 100 illustrated in
At a time t1, the TG 16 allows the signals φTX1 to φTX8 to achieve the L level. This resets the signal electric charge of the photodiode 101 of each pixel. An exposure period for each pixel 24 in the unit cells 100 is a period from the time t1 until one of the signals φTX input into each pixel 24 is allowed to achieve the H level. In
At a time t2, the TG 16 allows the signal φRES1 to achieve the H level to turn on the transistors 105 connected electrically with the control line 35. This resets the potentials of the input nodes of the transistors 103 connected electrically to the transistors 105 controlled through the control line 35.
At a time t3, the TG 16 allows the signal φSEL1 to achieve the H level. This enables the transistors 104 controlled through the control line 34 to output reset level signals to the first signal lines L11.
At a time t4, the TG 16 allows the signal φTX1 to achieve the H level. This enables signal electric charges accumulated by the photodiodes 101 of the pixels 24 indicated with R1, Gr1, R2, and Gr2 in
At a time t5, the TG 16 allows the signal φSEL1 to achieve the L level.
At a time t6, the TG 16 allows the signal φRES1 to achieve the H level. This resets the potentials of the input nodes of the transistors 103 connected electrically to the transistors 105 controlled through the control line 35.
At a time t7, the TG 16 allows the signal φSEL1 to achieve the H level. This enables the transistors 104 controlled through the control line 34 to output reset level signals via the first signal lines L11 to the readout circuit 13.
At a time t8, the TG 16 allows the signal φTX2 to achieve the H level. This enables signal electric charges accumulated by the photodiodes 101 of the pixels 24 indicated with Gb1, B1, Gb2, and B2 in
At a time t9, the TG 16 allows the signal φSEL1 to achieve the L level.
The TG 16 then allows signals φTX3 and φTX4 to achieve the H level sequentially in a manner similar to the operation performed from the time t6 to the time t9. This enables photoelectric conversion signals based on signal electric charges of the respective pixels 24 in the unit cells 100 including the transistors 104 controlled through the signal φSEL1 to be output to the readout circuit 13.
Then, at a time t16, the horizontal synchronizing signal HD is allowed to achieve the H level. In this way, the TG 16 allows the secondary scan circuit 14 to scan a plurality of the readout circuits 13. Thus, each of the readout circuit 13 outputs photoelectric conversion signals subjected to the CDS processing to the output amplifier 15 sequentially. The photoelectric conversion signals subjected to the CDS processing refers to signals of difference between the reset level signals and the photoelectric conversion signals.
Then, in a period from a time t18 through the time t32, the TG 16 performs an operation similar to that performed between the time t1 to the time t16 by controlling the signal φSEL2 instead of the signal φSEL1.
With reference to
At a time t0, the TG 16 allows the signal φCON to achieve the H level. This turns on the transistors 106 illustrated in
At a time t1, the TG 16 allows the signals φRES1 and φRES2 to achieve the H level. This resets the potentials of the input nodes of the transistors 103 connected electrically to transistors 105 controlled through the control lines 35 and 43.
At a time t2, the TG 16 allows the signal φSEL1 to achieve the H level. This enables the transistors 104 controlled through the control line 34 to output reset level signals to the first signal lines L11.
At a time t3, the TG 16 allows the signals φTX1, φTX3, φTX5, and φTX7 to achieve the H level. This enables the input nodes of the transistors 103 in the unit cells 100 in first and third columns in
At the time t3, the TG 16 also allows the signal φMEM to achieve the H level. This enables the capacitive elements 108 to each hold the signals based on the sum signals output to one of the first signal lines L11 in a column in association with each of the capacitive elements 108. The capacitive elements 108 according to this embodiment are each a signal holding section that holds a signal based on a sum signal. A signal held by each signal holding section is referred to as a held signal.
At a time t4, the TG 16 allows the signal φMEM to achieve the L level.
At a time t5, the TG 16 allows the signal φAVE to achieve the H level. This brings the capacitive elements 108 in the columns illustrated in
At a time t6, the TG 16 allows the signal φSEL1 to achieve the L level.
At a time t7, the TG 16 allows the signals φRES1 and φRES2 to achieve the H level. This resets the potentials of the input nodes of the transistors 103 in each unit cell 100.
At a time t8, the TG 16 allows the signal φSEL1 to achieve the H level.
At a time t9, the TG 16 allows the signals φTX2, φTX4, φTX6, and φTX8 to achieve the H level. This enables the input nodes of the transistors 103 in the unit cells 100 in the first and third columns in
At the time t9, the TG 16 also allows the signal φMEM to achieve the H level. This enables the capacitive elements 108 to each hold the signals based on the sum signals output to one of the first signal lines L11 in the respective columns.
At a time t10, the TG 16 allows the signal φMEM to achieve the L level.
At a time t11, the TG 16 allows the signal φAVE to achieve the H level. This brings the capacitive elements 108 in the columns illustrated in
As described above, the readout circuit 13 outputs to the output amplifier 15 the signals resulting from the CDS processing performed on the photoelectric conversion signals based on the signal electric charges of the individual pixels 24. The readout circuit 13 also outputs to the output amplifier 15 the average sum signals output from the unit signal processor 23. In other words, the readout circuit 13 according to the embodiment is a readout section that receives photoelectric conversion signals based on signal electric charges of the individual pixels 24 and signals based on sum signals.
The photoelectric conversion device according to the embodiment is capable of obtaining signals resulting from the CDS processing performed on photoelectric conversion signals based on signal electric charges of the individual pixels 24, and also average sum signals resulting from the averaging of signals based on sum signals of a plurality of columns of the unit cells 100. This allows the photoelectric conversion system according to the embodiment to obtain a high-resolution image and a low-resolution image.
Additionally, with the adder section generating a sum signal, a signal amplitude of a photoelectric conversion signal can be increased to perform light metering for a low-luminance subject. This allows the photoelectric conversion device according to the embodiment to have an improved S/N ratio for photoelectric conversion signals, in comparison with a case in which signal electric charges of the plurality of pixels 24 are not added up. Thus, the photoelectric conversion system including the photoelectric conversion device according to the embodiment is capable of improving the accuracy of the light metering processing, in comparison with a case in which a photoelectric conversion device does not generate a sum signal of the plurality of pixels 24.
Meanwhile, in the case of the light metering for a high-luminance subject, the accuracy of the light metering processing deteriorates when sum signals are saturated. In such a case, the light metering processing can be performed with photoelectric conversion signals that are based on individual signal electric charges of the plurality of pixels 24 and output by the readout circuit 13.
Thus, the photoelectric conversion device according to the embodiment is capable of performing the light metering processing in desirable manners for subjects in a wider luminance range, in comparison with a case in which only photoelectric conversion signals based on individual signal electric charges of the plurality of pixels 24 are output or with a case in which only average sum signals are output.
Additionally, the photoelectric conversion device according to the embodiment is capable of obtaining signals resulting from the CDS processing performed on photoelectric conversion signals based on signal electric charges of the individual pixels 24, and also average sum signals resulting from the averaging of signals based on sum signals of the plurality of columns of unit cells 100. This allows the calculation section 2 to use the signals resulting from the CDS processing performed on the photoelectric conversion signals based on the signal electric charges of the individual pixels 24 to generate an image. The calculation section 2 can use the generated image to detect a capture scene of a subject. Such capture scenes of subjects include a scene with a subject of interest, such as a person's face, a night scene, and a scene including a high-luminance subject, such as the sun. The calculation section 2 then performs the light metering on the subject in a way that is based on the detected capture scene and the average sum signals. Thus, the photoelectric conversion device according to the embodiment is capable of performing desirable light metering in response to a capture scene.
In the photoelectric conversion device according to the embodiment, each unit cell 100 includes the adder section. The photoelectric conversion device according to the embodiment is capable of generating sum signals faster than the imaging device of Japanese Patent Application Laid-Open No. 2005-348041, which is provided with one region including the adding circuit.
The imaging device of Japanese Patent Application Laid-Open No. 2005-348041 includes one region to hold sum signals per the pixel array. In contrast, the photoelectric conversion device according to the embodiment includes the plurality of unit signal processors 23, and the unit signal processors 23 each hold signals based on sum signals. The photoelectric conversion device according to the embodiment allows the unit signal processors 23 to each hold the signals based on the sum signals in a parallel manner. The photoelectric conversion device according to the embodiment also allows the unit signal processors 23 to each output an average sum signal to the readout circuit 13 in a parallel manner. Thus, the photoelectric conversion device according to the embodiment is capable of reading average sum signals from the plurality of regions 21 faster than the imaging device described in Japanese Patent Application Laid-Open No. 2005-348041.
Additionally, the photoelectric conversion device according to the embodiment includes the plurality of unit signal processors 23. Thus, periods in which the capacitive elements 108 in the mutually different unit signal processors 23 hold signals based on sum signals can be overlapped at least partially. Then, the TG 16 allows the signal φAVE, which is output to the plurality of unit signal processors 23, to achieve the H level, so that the plurality of unit signal processors 23 can generate average sum signals in a parallel manner. In this way, a period taken to generate average sum signals for the regions 21 can be reduced in comparison with a case of one unit signal processor 23.
Additionally, the photoelectric conversion device according to the embodiment allows the plurality of unit signal processors 23 to output average sum signals to the second signal lines L21, which are different from the first signal lines L11. The second signal lines L21 are connected electrically to the unit signal processors 23, resulting in smaller parasitic components than those of the first signal lines L11. Thus, the second signal lines L21 have drive loads smaller than those of the first signal lines L11. Because of this, in the case of the photoelectric conversion device according to the embodiment, the unit signal processors 23 are capable of outputting the average sum signals to the readout circuit 13 faster in comparison with a case in which the unit signal processors 23 output the average sum signals through the first signal lines L11.
The imaging device described in Japanese Patent Application Laid-Open No. 2003-18465 needs a capacitive element provided in each pixel in order to obtain average sum signals. Hence, the imaging device described in Japanese Patent Application Laid-Open No. 2003-18465 suffers a reduction in area of a photodiode in each pixel due to the capacitive elements. The photoelectric conversion device according to the embodiment is provided with the capacitive elements 108 separately from the pixels 24. In this way, the area of the photodiode 101 in each pixel 24 is less likely to be reduced in the photoelectric conversion device according to the embodiment in comparison with the configuration of the imaging device described in Japanese Patent Application Laid-Open No. 2003-18465. Thus, the photoelectric conversion device according to the embodiment is capable of improving the sensitivity of the photodiodes 101 to light, in comparison with the configuration of the imaging device described in Japanese Patent Application Laid-Open No. 2003-18465.
As described above with reference to
At a time t1, the TG 16 allows the signal φRES1 to achieve the H level.
At a time t2, the TG 16 allows the signal φSEL1 to achieve the H level. This enables the transistors 104 controlled through the control line 34 to output reset level signals to the first signal lines L11.
At a time t3, the TG 16 allows the signal φTX1 to achieve the H level. This enables the transistors 104 controlled through the control line 34 to output to the first signal lines L11 photoelectric conversion signals based on signal electric charges of the pixels 24 including the transistors 102 controlled through the control line 30.
At a time t4, the signal φSEL1 is allowed to achieve the L level.
The TG 16 then allows photoelectric conversion signals based on signal electric charges of the individual pixels 24 in the unit cells 100 to be output to the first signal lines L11 in a period until a time t15.
At a time t16, the TG 16 allows the signal φRES2 to achieve the H level, and then allows the signals φTX5 to TX8 to achieve the H level. This resets the potentials of the photodiodes 101 of the pixels 24 including the transistors 102 controlled through the control lines 38 to 41.
In other words, the pixels 24 including the transistors 102 controlled through the control lines 30 to 33 perform a rolling shutter operation in the operation illustrated in
As described above, the TG 16 may allow the different unit cells 100 to perform different signal output operations.
Additionally, the readout circuit 13 according to the embodiment may perform the CDS processing on average sum signals input from the unit signal processors 23. In this case, signals resulting from averaging of reset level signals output by the unit cells 100 can be used as the reset level signals used for the CDS processing.
Additionally, the readout circuit 13 outputs average sum signals to the output amplifier 15 in this embodiment. In another example, the readout circuit 13 may output average sum signals to the outside of the photoelectric conversion device without going through the output amplifier 15.
Furthermore, the photoelectric conversion device includes the one output amplifier 15 in the configuration described with reference to
In the present embodiment, an example has been described in which an average sum signal is input into the output amplifier 110. In another example, a signal resulting from addition of held signals of the plurality of capacitive elements 108 may be input into the output amplifier 110. In such a case, a node that adds up the held signals of the capacitive elements 108 in the plurality of columns is the adder section that adds up signals of the plurality of pixels.
In this embodiment, each unit cell 100 includes a plurality of pixels 24. In another example, each unit cell 100 may include one pixel 24, one transistor 103, and one transistor 104. Additionally, the unit signal processor 23 may be configured to add signals output by the transistors 104 of the plurality of unit cells 100.
A photoelectric conversion device according to a second embodiment will now be described with focus on a difference from the first embodiment.
In the photoelectric conversion device according to the first embodiment, the unit signal processors 23 in the regions 21 in an identical column are connected electrically to a common one of the second signal lines L21. The photoelectric conversion device according to this embodiment is different from the photoelectric conversion device according to the first embodiment in that one of second signal lines L21 is provided in association with each region 21. Because of this, the photoelectric conversion device according to this embodiment allows unit signal processors 23 in the regions 21 in an identical column to output average sum signals simultaneously. Thus, the photoelectric conversion device according to this embodiment is capable of reading average sum signals output by the unit signal processors 23 in the plurality of regions 21 still faster than the photoelectric conversion device according to the first embodiment.
A photoelectric conversion device according to a third embodiment will now be described with focus on a difference from the first embodiment.
In the photoelectric conversion device according to this embodiment, a unit signal processor 23 in each region 21 is connected electrically to four second signal lines L21. The four second signal lines L21 are each connected electrically to the unit signal processors 23 in the regions 21.
As illustrated in
With the photoelectric conversion device illustrated in
This allows the photoelectric conversion device according to the embodiment to obtain the signals based on the sum signals of the photodiodes 101 of the pixels 24 provided with the color filters in the same colors.
A photoelectric conversion system according to a fourth embodiment will now be described with reference to
The photoelectric conversion system according to this embodiment uses a signal output by a photoelectric conversion device 154 to generate an image. The photoelectric conversion device 154 may be configured according to any of the first to third embodiments.
The photoelectric conversion system includes a barrier 151, a lens 152, and an aperture 153. The barrier 151 is for protecting the lens. The lens 152 forms an optical image of a subject on the photoelectric conversion device 154 according to the embodiment. The aperture 153 is for varying a quantity of light through the lens 152. The photoelectric conversion system also includes an output signal processor 155 that processes a signal output from the photoelectric conversion device 154. The signal output from the photoelectric conversion device 154 is an imaging signal for generating a capture image that captures the subject. The output signal processor 155 performs various corrections on the imaging signal output from the photoelectric conversion device 154 as appropriate before compressing the signal. The lens 152 and the aperture 153 make up an optical module for concentrating the light onto the photoelectric conversion device 154.
An overall control/calculation section 1510 allows the photoelectric conversion device 154 to perform the operations described in the first to third embodiments. The output signal processor 155 generates an image through the signal output from the photoelectric conversion device 154.
The photoelectric conversion system also includes a buffer memory section 156 for storing temporarily image data and an external interface section 157 for communicating with an external computer and the like. The photoelectric conversion system also includes a removably attachable recording medium 159, such as a semiconductor memory, for recording and reading imaging data and a recording medium control interface section 158 for recording in and reading from the recording medium 159. The photoelectric conversion system also includes the overall control/calculation section 1510 for controlling various calculations and an overall digital still camera.
As described above, the photoelectric conversion system according to the embodiment is capable of generating an image with a signal output by the photoelectric conversion device 154.
Additionally, the output signal processor 155 may use the signal output by the photoelectric conversion device 154 according to the embodiment to perform the light metering processing. In this case, the output signal processor 155 performs the light metering processing to generate light metering data. The output signal processor 155 then outputs the generated light metering data to the overall control/calculation section 1510. The overall control/calculation section 1510 determines an exposure quantity for the photoelectric conversion device 154 based on the input light metering data. The exposure quantity refers to a period in which a shutter of the photoelectric conversion device is open, an aperture quantity of the aperture 153, sensitivity of the photoelectric conversion device 154, and the like.
This allows the photoelectric conversion system to generate an image of a subject captured with an appropriate exposure quantity.
The photoelectric conversion device according to the present invention generates sum signals through addition of signals of the plurality of photoelectric converters in each region provided in the light receiving region and thus is capable of generating the sum signals fast. Furthermore, the photoelectric conversion device according to the present invention includes, in addition to the first signal line to which individual signals of the plurality of photoelectric converters are output, the second signal line to which signals based on the sum signals are output. This allows the photoelectric conversion device according to the present invention to read the signals based on the sum signals fast.
While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.
This application claims the benefit of Japanese Patent Application No. 2013-125720, filed Jun. 14, 2013, which is hereby incorporated by reference herein in its entirety.
Number | Date | Country | Kind |
---|---|---|---|
2013-125720 | Jun 2013 | JP | national |