Claims
- 1. A circuit structure, comprising:
a substrate; a capacitor comprising a first electrically conductive layer fixed to the substrate and a second electrically conductive layer comprising an anchor portion and a free portion, the anchor portion being fixed to the substrate and electrically insulated from the first electrically conductive layer, wherein a stress profile in the second electrically conductive layer biases the free portion away from the first electrically conductive layer; wherein an electrostatic force applied to the second electrically conductive layer causes the free portion to displace towards the first electrically conductive layer, thereby increasing the capacitance of the capacitor; and an electronic device formed on the substrate.
- 2. The circuit of claim 1, further comprising a layer of electrically insulating material disposed between the first electrically conductive layer and the anchor portion.
- 3. The circuit of claim 1, further comprising a dielectric layer disposed on the first electrically conductive layer.
- 4. The circuit of claim 1, further comprising a dielectric layer disposed on the second electrically conductive layer.
- 5. The circuit of claim 1, wherein the free portion is biased away from the first electrically conductive layer along a radius of curvature.
- 6. The circuit of claim 5, wherein a tip of the first portion of the first electrically conductive layer is tapered.
- 7. The circuit structure of claim 1, wherein the electronic device comprises at least one of a resistor, a capacitor and an inductor.
- 8. The circuit structure of claim 1, wherein the electronic device comprises at least one of a transmission line and an antenna.
- 9. The circuit structure of claim 1, wherein the electronic device comprises at least one of a transformer, a filter circuit, a phased-lock loop circuit, a heterodyne circuit, a mixer circuit, a delay line, a super heterodyne circuit, and an oscillator.
- 10. The circuit structure of claim 1, wherein the electronic device comprises at least one of a transistor and a diode.
- 11. The circuit structure of claim 1, wherein the anchor portion is fixed to an insulating layer disposed on a portion of the first electrically conductive layer.
- 12. A circuit structure, comprising:
a substrate; a capacitor comprising a first electrically conductive layer fixed to the substrate; a dielectric layer fixed to a portion of the first electrically conductive layer; and a second electrically conductive layer comprising an anchor portion and a plurality of free portions, the anchor portion being fixed to the dielectric layer, wherein a stress profile in the second electrically conductive layer biases the free portions away from the dielectric layer; wherein an electrostatic force applied to the second electrically conductive layer causes the free portions to displace towards the first electrically conductive layer, thereby increasing the capacitance of the capacitor; and an electronic device formed on the substrate.
- 13. The circuit of claim 12, wherein the free portions are disposed in rows adjacent to one another.
- 14. The circuit of claim 12, wherein the free portions are disposed in columns adjacent to one another.
- 15. The circuit structure of claim 12, wherein the electronic device comprises at least one of a resistor, a capacitor and an inductor.
- 16. The circuit structure of claim 12, wherein the electronic device comprises at least one of a transmission line and an antenna.
- 17. The circuit structure of claim 12, wherein the electronic device comprises at least one of a transformer, a filter circuit, a phased-lock loop circuit, a heterodyne circuit, a mixer circuit, a delay line, a super heterodyne circuit, and an oscillator.
- 18. The circuit structure of claim 12, wherein the electronic device comprises at least one of a transistor and a diode.
- 19. A variable capacitor structure, comprising:
a substrate; a first electrically conductive layer fixed to the substrate and a second electrically conductive layer comprising an anchor portion and a free portion, the anchor portion being fixed to the substrate and electrically insulated from the first electrically conductive layer, wherein a stress profile in the second electrically conductive layer biases the free portion away from the first electrically conductive layer; wherein an electrostatic force applied to the second electrically conductive layer causes the free portion to displace towards the first electrically conductive layer, thereby increasing the capacitance of the capacitor.
- 20. The capacitor of claim 19, wherein the anchor portion is fixed to an insulating layer disposed on a portion of the first electrically conductive layer.
- 21. The capacitor of claim 19, further comprising a dielectric layer disposed on the first electrically conductive layer.
- 22. The capacitor of claim 19, wherein the free portion is biased away from the first electrically conductive layer along a radius of curvature.
- 23. The capacitor of claim 22, wherein a tip of the first portion of the first electrically conductive layer is tapered.
- 24. The capacitor of claim 19, further comprising a layer of electrically insulating material disposed between the first electrically conductive layer and the anchor portion.
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This is a continuation of co-pending U.S. application Ser. No. 09/573,363 filed May 17, 2000, the contents of which are incorporated herein by reference.
[0002] This application is related to U.S. application Ser. No. 09/573,815, filed May 17, 2000, U.S. application Ser. No. 09/975,358 filed Oct. 11, 2001, U.S. application Ser. No. 09/591,262 filed Jun. 9, 2000, and U.S. application Ser. No. 10/004,819 filed Dec. 7, 2001.
Continuations (1)
|
Number |
Date |
Country |
Parent |
09573363 |
May 2000 |
US |
Child |
10154995 |
May 2002 |
US |