This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2023-0112280, filed on Aug. 25, 2023, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.
The disclosure relates to a photonic integrated apparatus, and more particularly, to a photonic integrated apparatus including a photonic device and a waveguide which are monolithically formed on a substrate.
Photonic integrated circuits and/or photonic integrated apparatuses in which photonic devices are integrated may be used in various photonic sensor or photonic connection fields. Photonic devices used in photonic integrated apparatuses include a photonic source that converts electrical energy into photonic energy, a photonic modulator that modulates light, a waveguide that transmits a photonic signal, a photonic antenna or photonic coupler that sends light inside the waveguide to outside of a photonic integrated circuit chip or receives light outside the photonic integrated circuit chip into the waveguide, a photonic detector that converts light energy into electrical energy, etc.
There is a need to increase light coupling efficiency and reduce the volume of photonic integrated apparatus by forming various photonic devices on one substrate.
Provided is a photonic integrated apparatus in which a photonic device and a waveguide are monolithically disposed on one substrate.
Provided is a photonic integrated apparatus that increases light coupling efficiency between a photonic device and a waveguide.
Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments of the disclosure.
According to an aspect of the disclosure, a photonic integrated apparatus includes a substrate; a dielectric layer on the substrate, the dielectric layer defining an opening exposing a part of the substrate; a photonic source contacting a partial area of the substrate through the opening; a waveguide on the dielectric layer, and a photonic steering device on the dielectric layer and configured to steer light emitted from the photonic source to the waveguide.
A partial area of at least one side surface of the photonic source may be in contact with the dielectric layer.
The substrate may include one or more grooves.
The one or more grooves may expose a (111) surface of the substrate.
The photonic source may fill at least one of the one or more grooves.
The photonic source may include a first semiconductor layer in contact with a partial area of the substrate, a second semiconductor layer above and the first semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer, and a portion of the first semiconductor layer may protrude from the dielectric layer.
The first semiconductor layer may include a first sub-semiconductor layer surrounded by the dielectric layer, and a second sub-semiconductor layer on the first sub-semiconductor layer and having a width different from a width of the first sub-semiconductor layer.
The width of the second sub-semiconductor layer may be greater than the width of the first sub-semiconductor layer.
The photonic steering device may focus the light emitted from the photonic source toward the waveguide.
The light emitted from the photonic source may be incident on a curved surface of the photonic steering device.
The photonic steering device may include a convex lens shape.
The photonic steering device may be in contact with at least one of an upper surface or a side surface of the waveguide.
The waveguide may overlap a part of the photonic steering device in a thickness direction of the substrate.
A refractive index of the photonic steering device may be less than or equal to a refractive index of the waveguide.
The substrate may include a semiconductor.
The substrate, the dielectric layer, the photonic source, and the waveguide may have a monolithic structure.
The substrate, the dielectric layer, and the waveguide may be patterned from a silicon on insulator (SOI) substrate.
The photonic integrated apparatus may further include an anti-reflective layer on at least a part of a surface of the photonic source, facing the photonic steering device.
The photonic integrated apparatus may further include a reflective layer on at least a part of a surface of the photonic source not facing the photonic steering device.
The photonic integrated apparatus may further include a reflector on the photonic steering device and configured to reflect incident light emitted from the photonic source.
The photonic integrated apparatus may further include an additional dielectric layer over the waveguide, and an additional waveguide over the additional dielectric layer and configured to transmit the light emitted from the photonic steering device to the waveguide through light coupling.
The above and other aspects, features, and advantages of certain embodiments of the disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:
Reference will now be made in detail to some embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, unless otherwise stated or clear from context, none of the example embodiments are necessarily mutually exclusive to one another. While one or more example embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that the present embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, the embodiments are merely described below, by referring to the figures, to explain aspects.
As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list.
Hereinafter, embodiments will be described with reference to the accompanying drawings. In the drawings, the sizes of elements may be exaggerated for clarity of illustration. The embodiments described herein are for illustrative purposes only, and various modifications may be made therein.
In the following description, when an element is referred to as being “above” or “on” another clement, it may be directly on an upper, lower, left, or right side of the other element while making contact with the other element or may be above an upper, lower, left, or right side of the other element without making contact with the other element. Additionally, spatially relative terms, such as “beneath,” “below,” “lower,” “under,” “above,” “upper,” and the like, may be used herein for ease of explanation to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or in operation, in addition to the orientation depicted in the figures. For example, device may be otherwise oriented, for example, rotated 90 degrees or at other orientations, and the spatially relative descriptors used herein should be interpreted accordingly. The terms of a singular form may include plural forms unless otherwise mentioned. It will be further understood that the terms “comprises” and/or “comprising” used herein specify the presence of stated features or elements, but do not preclude the presence or addition of one or more other features or elements.
An element referred to with the definite article or a demonstrative pronoun may be construed as the element or the elements even though it has a singular form. Operations of methods herein may be performed in any suitable order unless clearly specified herein or contradicted by context.
The disclosure is not limited to the described order of the operations.
Also, terms such as “processor,” “unit,” and/or “module” used herein may be used to denote a unit that has at least one function or operation and is implemented with processing circuitry such as hardware, software, and/or a combination of hardware and software. For example, the processing circuitry more specifically may include (and/or be included in), but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a System-on-Chip (SoC), a programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), etc.
Line connections or connection members between elements depicted in the drawings represent functional connections and/or physical or circuit connections by way of example, and in actual applications, they may be replaced or embodied with various additional functional connections, physical connections, or circuit connections.
Although terms such as “first” and “second” may be used herein to describe various elements or components, these elements or components should not be limited by these terms. These terms are only used to distinguish one element or component from another element or component.
All examples or exemplary terms are just used herein to describe technical ideas and should not be considered for purposes of limitation unless defined by the claims. Additionally, when the terms “about” or “substantially” are used in this specification in connection with a numerical value, it is intended that the associated numerical value includes a manufacturing tolerance (e.g., ±10%) around the stated numerical value. Further, regardless of whether numerical values are modified as “about” or “substantially,” it will be understood that these values should be construed as including a manufacturing or operational tolerance (e.g., ±10%) around the stated numerical values. When referring to “C to D”, this means C inclusive to D inclusive unless otherwise specified.
Referring to
The substrate 101 may include a semiconductor material. For example, the substrate 101 may be an elemental semiconductor substrate such as a silicon (Si) substrate and/or a germanium (Ge) substrate, and/or a compound semiconductor substrate such as GaP, GaAs, InP, GaN, and/or the like. For example, the substrate 101 may include a silicon substrate. However, a material of the substrate 101 is not necessarily limited thereto, and various wafer materials used in a semiconductor manufacturing process may be used as the substrate 101.
One or more grooves G may be disposed in the substrate 101. One groove G is shown in the drawing, but the disclosure is not limited thereto. A plurality of grooves G may be disposed in a surface of the substrate 101. In at least one embodiment, a (111) surface of the substrate 101 may be exposed to the outside through the groove G. In at least one embodiment, the photonic source 110 may be easily grown on the substrate 101 through the groove G described above.
The dielectric layer 102 may be disposed on the substrate 101. The dielectric layer 102 may include oxide. For example, the dielectric layer 102 may be silicon oxide (SiO2), but is not necessarily limited thereto. For example, the dielectric layer 102 may include at least one of an insulating silicon compound and/or an insulating metal compound in addition to silicon oxide. The insulating silicon compound may include, for example, silicon nitride (SixNy), silicon oxynitride (SiON), etc., and the insulating metal compound may include, for example, aluminum oxide (A12O3), hafnium oxide (HfO), and zirconium oxide (ZrO), hafnium silicon oxide (HfSiO), titanium oxide (TiO2), etc.
The dielectric layer 102 may include the opening O that exposes a part of the substrate 101. The groove G formed in the substrate 101 may overlap with the opening O in a thickness direction of the substrate 101. The entire groove G may overlap with the opening O.
The waveguide 120 may be disposed on the dielectric layer 102. The waveguide 120 may include a material with a refractive index greater than that of the dielectric layer 102. In at least one embodiment, the waveguide 120 may include a semiconductor material. For example, the waveguide 120 may include at least one of silicon and/or a nitride semiconductor. The substrate 101, the dielectric layer 102, and the waveguide 120 may be formed as a single Si on Insulator (SOI) substrate. For example, the waveguide 120 may be formed by partially patterning a silicon layer in the SOI substrate.
The photonic source 110 may be disposed to be in contact with the substrate 101. For example, the photonic source 110 may contact the substrate 101 through the opening O of the dielectric layer 102. A partial area of the photonic source 110 is impregnated in the substrate 101. For example, the photonic source 110 may extend in the thickness direction of the substrate 101 while filling the groove G formed in the substrate 101. A partial area of the side surfaces of the photonic source 110 may be surrounded by the dielectric layer 102. For example, the partial area of the side surfaces of the photonic source 110 may be in contact with the dielectric layer 102.
The photonic source 110 may include a first semiconductor layer 111, an active layer 112, and a second semiconductor layer 113.
The first semiconductor layer 111 may include, for example, an n-type semiconductor. However, the first semiconductor layer 111 is not necessarily limited thereto, and in some cases, may include a p-type semiconductor. For example, the first semiconductor layer 111 may include a group III-V n-type semiconductor and/or a group II-VI n-type semiconductor. Here, a nitride semiconductor may include, for example, GaN, InN, AIN, and/or a combination thereof, but is not limited thereto. For example, the first semiconductor layer 111 may include n-GaN.
The active layer 112 may be disposed on the first semiconductor layer 111. The active layer 112 may generate light in a certain wavelength band by combining electrons and holes. The active layer 112 may have a multi-quantum well (MQW) structure. However, the active layer 112 is not necessarily limited thereto, and in some cases, may have a single-quantum well (SQW) structure. The active layer 112 may include a group III-V semiconductor or a group II-VI semiconductor. For example, the active layer 112 may include GaN.
The second semiconductor layer 113 may be disposed on the active layer 112. The second semiconductor layer 113 may have an opposite charge type compared to the first semiconductor layer 111. For example, the second semiconductor layer 113 may include a p-type semiconductor. However, the second semiconductor layer 113 is not necessarily limited thereto, and in some cases, may include an n-type semiconductor. The second semiconductor layer 113 may include a group III-V p-type semiconductor or a group II-VI semiconductor. For example, the second semiconductor layer 113 may include p-GaN.
In general, a photonic integrated circuit including a waveguide may include a compound semiconductor such as silicon or silicon nitride. On the other hand, the photonic source 110 may include a group III-V compound semiconductor and/or a group II-VI compound semiconductor. The photonic source 110 and the photonic integrated circuit include different materials, and thus, the photonic source 110 may be manufactured independently and then connected to the photonic integrated circuit by using an optical fiber, etc. However, the photonic fiber has problems in that light coupling efficiency between the photonic source 110 and the photonic integrated circuit deteriorate, and the volume of the photonic fiber increases.
A photonic source integrated photonic integrated apparatus may be required to implement a compact photonic integrated circuit. To implement the photonic source integrated photonic integrated apparatus, the photonic source 110 may be manufactured separately and then bonded or transferred to the photonic integrated apparatus. However, misalignment may occur during a bonding or transfer process, which may reduce light coupling efficiency.
Alternatively, the photonic source 110 may be manufactured after bonding the base substrate, such as a group III-V, to the photonic integrated apparatus. Areas of the base substrate other than an area where the photonic source 110 is formed are discarded, causing a problem of increased manufacturing costs.
The photonic integrated apparatus according to at least one embodiment may have the photonic source 110 grown directly on the substrate 101. For example, the photonic source 110 may be formed using a selective epitaxial growth method. For example, a lower silicon layer, that is, a partial area of the substrate 101, may be exposed by removing the silicon layer of the SOI substrate and forming the opening O in the dielectric layer 102. As such the crystal lattice of the photonic source 110 may be aligned with the lattice structure of the exposed surface of the substrate 101 from which the photonic source 110 is grown. The one or more grooves G may be formed in the exposed area of the substrate 101. The surface 111 of the substrate 101 may be exposed by the groove G described above. The photonic source 110 may be formed on the (111) surface of the substrate 101 using a selective epitaxial growth method.
Meanwhile, because the substrate 101 and the photonic source 110 have different lattice constants, lattice defects may occur when the photonic source 110 is grown on the substrate 101. The lattice defects described above may impair the quantum efficiency of the photonic source 110. In order to remove the lattice defects described above, a thickness of the epitaxially grown first semiconductor layer 111 may be increased. The thickness of the first semiconductor layer 111 may be greater than a thickness of the dielectric layer 102 so that the first semiconductor layer 111 may be derived from a surface of the dielectric layer 102. Here, the thickness may mean an average thickness of the first semiconductor layer 111.
For example, the first semiconductor layer 111 may include a first sub-semiconductor layer 210 impregnated in the substrate 101, a second sub-semiconductor layer 220 surrounded by the dielectric layer 102, and a third sub-semiconductor layer 230 protruding from the dielectric layer 102. The first to third sub-semiconductor layers 210, 220, and 230 may have different widths. For example, the width of the first sub-semiconductor layer 210 may be smaller than the width of the second sub-semiconductor layer 220, and the width of the second sub-semiconductor layer 220 may be smaller than the width of the third sub-semiconductor layer 230. Here, the width may mean an average width of a layer. The first sub-semiconductor layer 210 may include a tapered area gradually increasing in width towards the second sub-semiconductor layer 220. The third sub-semiconductor layer 230 may include a tapered area gradually increasing in width towards the active layer 112.
Because the photonic source 110 is formed by growing directly on the substrate 101, the substrate 101, the dielectric layer 102, and the photonic source 110 may have a monolithic structure. For example, when the waveguide 120 is formed as the SOI substrate, the substrate 101, the dielectric layer 102, the waveguide 120, and the photonic source 110 may have the monolithic structure.
As the thickness of the first semiconductor layer 111 increases, a height difference between the active layer 112 of the photonic source 110 and the waveguide 120 may increase. In order to mitigate the effects of this height difference, the photonic integrated apparatus according to at least one embodiment may include the photonic steering device 130 that steers the light emitted from the photonic source 110 to the waveguide 120. The photonic steering device 130 may be disposed between the photonic source 110 and the waveguide 120 on the dielectric layer 102. The light incident on the photonic steering device 130 may transmit through the photonic steering device 130 and be focused in a direction of the waveguide 120, thereby increasing light coupling efficiency between the photonic source 110 and the waveguide 120.
The light incident from the photonic source 110 may be incident on a curved surface of the photonic steering device 130. The light incident on the curved surface may be differently refracted according to an angle of incidence, and thus focused while traveling through the photonic steering device 130.
The photonic steering device 130 may include a lens shape configured to enhance focusing of light. For example, the photonic steering device 130 may include a convex shape from the dielectric layer 102. A cross-section of the photonic steering device 130 may have, for example, a circular or oval shape. However, the shape of the photonic steering device 130 is not limited thereto, and may vary depending on a shape and a position of each of the photonic source 110 and the waveguide 120.
A material of the photonic steering device 130 may be similar to a material of at least one of the photonic source 110 and the waveguide 120. In addition, the photonic steering device 130 may include a material having a higher refractive index than the dielectric layer 102. Therefore, there may be little or no absorption of light transmitted through the photonic steering device 130. For example, the refractive index of the photonic steering device 130 may be a value between the refractive index of the photonic source 110 and the refractive index of the waveguide 120. For example, in at least one embodiment, the refractive index of the photonic steering device 130 may be within a range of about 2.5 to about 3.5.
Alternatively, when the waveguide 120 and the photonic steering device 130 are in contact with each other, the refractive index of the photonic steering device 130 may be less than or equal to the refractive index of the waveguide 120. Because the refractive index of the photonic steering device 130 is less than or equal to the refractive index of the waveguide 120, light reflection may be reduced on the interface between the waveguide 120 and the photonic steering device 130, thereby increasing light coupling efficiency.
The photonic steering device 130 may include at least one of an organic material, an oxide, and/or a nitride. In at least one embodiment, the photonic steering device 130 may be formed through a thermal flow process, a gray scale photo process, etc.
Although not shown in
Upon comparing
The anti-reflective layer 114 may be configured to prevent light generated by the photonic source 110a from being reflected from an interface of the photonic source 110a into the photonic source 110a. For example, a wavelength reflected from the interface between the anti-reflective layer 114 and the photonic source 110a may be destructively interfered so that reflectance into the photonic source 110a may be reduced and the transmittance to the outside of the photonic source 110a may be improved. The anti-reflective layer 114 may include at least one of MgF2, SiO2, Al2O3. and/or HfO2, and may be patterned to destructively interfere with the reflected wavelength, but is not limited thereto. This may increase the light emission efficiency of the photonic source 110a.
The reflective layer 115 may reflect the light generated by the photonic source 110a into the interior of the photonic source 110a, thereby preventing the light from being emitted towards a place other than the photonic steering device 130 and/or increasing the energy efficiency of the photonic source 110a. The reflective layer 115 may include a semiconductor material and/or a dielectric material having high reflectivity. For example, the reflective layer 115 may include a group III-V compound semiconductor or a group II-VI compound semiconductor having high reflectivity, e.g., with respect to the wavelength of light generated by the photonic source 110a.
The photonic source 110a in
A partial area of the first waveguide 120 and a partial area of the second waveguide 170 may overlap each other in a thickness direction of the first dielectric layer 102. When a distance between the first waveguide 120 and the second waveguide 170 is less than or equal to a wavelength of light, vertical evanescent coupling may occur in an opposing area of the first waveguide 120 and the second waveguide 120 so that the light may be transmitted between the first waveguide 120 and the second waveguide 170 with little light loss.
When a height difference between the active layer 112 of the photonic source 110 and the first waveguide 120 is large, and when light coupling between the photonic source 110 and the first waveguide 120 is difficult using only the photonic steering device 130, the light may be transmitted with little light loss by adding the second dielectric layer 103 and the second waveguide 170.
A connection structure between the photonic source 110 and the waveguide 120 has been described above. However, the disclosure is not limited thereto. The same may be applied to a connection structure between a photonic detector and a waveguide. The only difference is that the photonic source 110 is a photonic device that converts an electrical signal into light, while the photonic detector is a photonic device that converts light into an electrical signal, and the photonic detector may also include a group III-V compound semiconductor or a group II-VI compound semiconductor.
A photonic steering device 190 may be disposed between the waveguide 120 and the photonic detector 180. The photonic steering device 190 may steer the light received from the waveguide 120 and apply the light to the photonic detector 180.
The photonic steering device 190 may include a lens shape that enhances focusing of the light. For example, the photonic steering device 190 may include a convex shape from the dielectric layer 102. A material of the photonic steering device 190 may be similar to a material of any one of the waveguide 120 and the photonic detector 180. In addition, the photonic steering device 190 may include a material having a higher refractive index than the dielectric layer 102.
Alternatively, when the photonic steering device 190 is in contact with the photonic detector 180, a refractive index of the photonic steering device 190 may be less than or equal to a refractive index of the photonic detector 180. Because the refractive index of the photonic steering device 190 is less than or equal to the refractive index of the photonic detector 180, light reflection may be reduced on an interface between the photonic steering device 190 and the photonic detector 180, thereby increasing light coupling efficiency.
The photonic integrated apparatus may be applied to various fields. For example, the photonic integrated apparatus may be applied to a photonic sensor such as a laser radar (LiDAR) for autonomous driving, a photonic link, a photonic computing apparatus, a photonic memory apparatus, etc.
The branch area 300A may include a plurality of optical splitters 320. The plurality of optical splitters 320 may divide one light traveling along the waveguides 311 into several lights. To this end, one waveguide 311 may be connected to an input terminal of each of the optical splitters 320, and the plurality of waveguides 311 may be connected to an output terminal of the optical splitters 320. As an example,
The phase control area 300B may include a plurality of phase control devices 330 respectively disposed in the plurality of waveguides 311. For example, the plurality of phase control devices 330 may be arranged in a second direction DR2 perpendicular to the first direction DR1. The plurality of lights divided within the branch area 300A may be respectively provided to the plurality of phase control devices 330. Each of the phase control devices 330 may have a variable refractive index that is electrically controlled. Phases of lights passing through the phase control devices 330 may be determined according to a refractive index of each of the phase control devices 330. The phase control devices 330 may independently adjust the phases of the divided lights.
The amplification area 300C may include a plurality of optical amplifiers 340 respectively disposed in the plurality of waveguides 311. The plurality of optical amplifiers 340 may be arranged in the second direction DR2 perpendicular to the first direction DR1. The optical amplifier 340 may increase the magnitude of an optical signal. For example, each of the optical amplifiers 340 may include a semiconductor optical amplifier or an ion-doped amplifier.
The emission area 300D may include a plurality of lattice pattern groups 350. The plurality of lattice pattern groups 350 may be arranged in the second direction DR2. The plurality of lattice pattern groups 350 may each be connected to a plurality of optical amplifiers 340. The lattice pattern groups 350 may respectively emit lights amplified in the amplification region 300C. To this end, the lattice pattern groups 350 may respectively include a plurality of lattice patterns 350a which are arranged periodically. The plurality of lattice patterns 350a may be arranged in the first direction DR1. A direction in which an output light OL emitted by the lattice pattern groups 350 travels may be determined according to a phase difference between the divided lights determined in the phase control area 300B, a distance between the lattice patterns 350a, a height of each of the lattice patterns 350a, and a width of each of the lattice patterns 350a. For example, the direction in which the output light OL travels may include a component in the first direction DR1, a component in the second direction DR2, and a component in a third direction DR3 perpendicular to the first direction DR1 and the second direction DR2.
According to at least one embodiment, a compact photonic integrated apparatus may be implemented by growing a photonic device directly on a substrate.
According to at least one embodiment, a photonic steering device may be disposed between the photonic device and the waveguide, thereby reducing degradation of light coupling due to a height difference between the photonic device and the waveguide.
It should be understood that embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0112280 | Aug 2023 | KR | national |