Patent Application
20220102565
The present invention relates to a photovoltaic cell, a manufacturing method of the photovoltaic cell, and a photovoltaic module.
WO2017/169441 (PTL 1) discloses that an anti-reflection film included in a photovoltaic cell is formed of a silicon rich silicon nitride film.
WO2017/175524 (PTL 2) discloses a technique of adding a capturing additives that captures sodium ions to an encapsulant that encapsulates a photovoltaic cell.
Japanese Unexamined Patent Application Publication (Translation of PCT Application) No. 2008-532311 (PTL 3) discloses a technique of providing a conductive path for extracting charge from the front side of the photovoltaic cell to the bulk.
The development of clean energy sources is desirable from the perspective of global environmental problems such as the depletion of fossil fuels and the increase of carbon dioxide (greenhouse gas) in the atmosphere. As an example, photovoltaic power generation using photovoltaic cells has been commercialized as a new clean energy source.
In particular, in recent years, the use of photovoltaic modules with multiple photovoltaic cells connected to each other has become widespread in households, and large-scale power generation facilities, so-called megawatt-class solar facilities, have been constructed using many photovoltaic modules.
Photovoltaic modules are used outdoors for long periods of time. For this reason, photovoltaic cell modules are required to have long-term reliability in harsh outdoor environments.
In this regard, it has been reported that the power generation efficiency of photovoltaic cells decreases due to potential induced degradation (PID), which is the deterioration of photovoltaic cells. An investigation into the causes of PID and the early establishment of remedial measures are highly desirable.
Other issues and novel features will become apparent from the description herein and the accompanying drawings.
A photovoltaic cell of an embodiment of the present invention includes a back electrode; a first semiconductor layer of a first conductivity type disposed on the back electrode; a second semiconductor layer of a second conductivity type disposed on the first semiconductor layer; an anti-reflection film disposed on the second semiconductor layer, the anti-reflection film being made of an insulating film; a surface electrode extending through the anti-reflection film to reach the second semiconductor layer; and a conductive film disposed on the anti-reflection film so as to cover the surface electrode and electrically connected to the second semiconductor layer, the conductive film being optically transparent.
According to the embodiment, the PID can be suppressed, and as a result the reliability of the photovoltaic cell can be improved.
In all diagrams for describing an embodiment, the same components are basically denoted with the same reference numerals, and reiterated descriptions are omitted. Note that for clarity of the drawing, hatching may be added even in the plan view.
For example, in a photovoltaic power generation system, a plurality of photovoltaic modules is connected in series to increase the system voltage.
As illustrated in
The following describes an actual room for improvement in a photovoltaic module, such as photovoltaic module PVM1 illustrated in
In
As illustrated in
Here, it is known that the power generation efficiency decreases when a high voltage is applied between the module frame MF and the photovoltaic cell CL, and this phenomenon is called “PID”. The “PID” is known to occur especially when semiconductor substrate 1S made of p-type semiconductor material is used and the potential of the photovoltaic cell CL becomes negative relative to the frame potential of the module frame ME
In view of this, a focus is directed to a case where a negative potential relative to module frame MF is applied to photovoltaic cell CL in photovoltaic module PVM1 illustrated in
With reference to the drawings, the following describes a cause of the occurrence of “PID” in a case where a negative potential relative to module frame MF is applied to photovoltaic cell CL.
In
Here, cover glass GS contains cations such as sodium ions. Further, when a negative potential relative to the module frame is applied to the photovoltaic cell, the cations contained in the glass are accumulated at the surface of anti-reflection film ARF through encapsulant MR. At this time, a high electric field indicated with the broken line arrow(s) in
In view of this, in the present embodiment, a configuration for suppressing the migration of cations into the photovoltaic cell is provided based on the knowledge that
“PID” is caused by cations reaching the inside of semiconductor substrate 1S including n-type semiconductor layer NL. The following describes technical ideas of the present embodiment using such a configuration.
As illustrated in
Next,
Photovoltaic cell CL illustrated in
In
Semiconductor substrate 1S is composed of silicon to which a p-type impurity (acceptor) such as boron (B), for example, is introduced, and is a p-type semiconductor layer. Semiconductor substrate 1S, which functions as a p-type semiconductor layer, has a thickness of approximately 200 μm, for example.
In contrast, n-type semiconductor layer NL formed at the surface of semiconductor substrate 1S is a semiconductor layer in which an n-type impurity (donor) such as phosphorus (P), for example, is introduced to silicon, and n-type semiconductor layer NL has a thickness of approximately 0.3 μm, for example. Thus, a pn-junction is formed between semiconductor substrate 1S, which is a p-type semiconductor layer, and n-type semiconductor layer NL.
Note that although not illustrated in the drawings, a random texture structure (irregular structure) of approximately several micrometers is formed at the surface of n-type semiconductor layer NL and the back surface of semiconductor substrate 1S.
Next, as illustrated in
Next, photovoltaic cell CL of the present embodiment includes the plurality of surface electrodes SE that extends through anti-reflection film ARF to reach n-type semiconductor layer NL. That is, each of the plurality of surface electrodes SE and n-type semiconductor layer NL are electrically connected to each other.
Note that while
Surface electrode SE is composed of silver, for example.
Next, as illustrated in
Conductive film CF is in contact with surface electrode SE, and thus conductive film CF and surface electrode SE are electrically connected to each other. Further, as illustrated in
Further, conductive film CF is optically transparent. Specifically, desirably, conductive film CF is composed of a material that is optically transparent at least to visible light and infrared light, which are main components of sunlight, more desirably a material with high transmittance, for example.
Specifically, conductive film CF may be composed of a film including indium and oxygen, or a film including zinc and oxygen. For example, conductive film CF may be composed of a film containing indium oxide doped with tin. It should be noted that conductive film CF is not limited to this, and may be composed of an indium oxide film doped with tungsten, an indium oxide film doped with cerium, an indium oxide film doped with hydrogen, a zinc oxide film doped with aluminum, a zinc oxide film doped with gallium, a tin oxide film doped with fluorine or the like. Conductive film CF having the above-described configuration has a conductivity of 10 siemens/cm or greater, for example. In addition, conductive film CF has a film thickness greater than 0 nm and smaller than or equal to 100 nm, for example. More preferably, conductive film CF has a film thickness of 20 nm to 80 nm.
Photovoltaic cell CL of the present embodiment has the above-described configuration, and an overview of the configuration of photovoltaic cell CL is as follows. Photovoltaic cell CL of the present embodiment includes back electrode BE, semiconductor substrate 1S, which is a p-type semiconductor layer, disposed on back electrode BE, and n-type semiconductor layer NL formed on p-type semiconductor layer. Further, photovoltaic cell CL of the present embodiment includes anti-reflection film ARF formed on n-type semiconductor layer NL and made of an insulating film, surface electrode
SE that extends through anti-reflection film ARF to reach n-type semiconductor layer NL, and optically transparent conductive film CF formed on anti-reflection film ARF so as to cover surface electrode SE and electrically connected to the n-type semiconductor layer NL.
Photovoltaic cell CL of the present embodiment is configured as described above, and its operation is described below with reference to
First, in
Next, the sunlight transmitted through conductive film CF impinges on anti-reflection film ARF. Since anti-reflection film ARF is composed of a silicon oxide film and/or a silicon nitride film that is transparent to visible light and infrared light as main components of sunlight, the sunlight transmitted through conductive film CF so as to impinge on anti-reflection film ARF is also transmitted through anti-reflection film ARF. Here, the film thickness of anti-reflection film ARF is adjusted in such a manner as to reduce the reflection of the sunlight, and thus the reflection of the sunlight at anti-reflection film ARF is suppressed. As a result, the loss of the sunlight transmitted through anti-reflection film ARF can be reduced.
Subsequently, the sunlight transmitted through anti-reflection film ARF enters the inside of photovoltaic cell CL located below anti-reflection film ARF. More specifically, the sunlight enters n-type semiconductor layer NL, the pn-junction part formed in the interface region between n-type semiconductor layer NL and semiconductor substrate 1S (p-type semiconductor layer), and semiconductor substrate 1S.
At this time, for example, the light energy of visible light and infrared light as main components of the sunlight is greater than the band gap of silicon, and therefore electrons in the valence band of silicon are excited into the conduction band by receiving light energy supplied by the sunlight (visible light and infrared light). This results in accumulation of electrons in the conduction band and generation of holes in the valence band. In this manner, irradiation of photovoltaic cell CL with sunlight results in excitation of electrons in the conduction band and generation of holes in the valence band. Further, the conduction band of the n-type semiconductor layer constituting one of the pn-junctions is at a lower electronic energy level than the conduction band of semiconductor substrate 1S, which is the p-type semiconductor layer constituting the other part of the pn-j unction. As a result, electrons excited in the conduction band are moved to n-type semiconductor layer NL, and thus electrons are accumulated in the n-type semiconductor layer NL. On the other hand, holes in the valence band are moved to semiconductor substrate 1S (p-type semiconductor layer) and thus holes are accumulated in semiconductor substrate 1S (p-type semiconductor layer). As a result, an electromotive force is generated between semiconductor substrate 1S, which is a p-type semiconductor layer, and n-type semiconductor layer NL. Further, for example, when a load is connected between surface electrode SE electrically connected to n-type semiconductor layer NL, and back electrode BE electrically connected to semiconductor substrate 1S, electrons flow from surface electrode SE through the load to back electrode BE. In other words, current flows from back electrode BE through the load to the surface electrode SE. In this manner, the load can be driven by operating photovoltaic cell CL.
Next, a manufacturing method of the photovoltaic cell of the present embodiment is described.
First, for example, a semiconductor substrate made of single crystal silicon or polycrystalline silicon with p-type impurities (acceptor) added is prepared. This semiconductor substrate has a flat planar shape (S101).
Next, a texture structure as an anti-reflection structure is formed at the surface (light reception surface) of the semiconductor substrate using a wet etching technique, for example. The texture structure is composed of an irregular structure, and formed to achieve a reflection reduction effect and an incident light confinement effect (S102).
Subsequently, an n-type semiconductor layer is formed on the surface side of the semiconductor substrate by diffusing n-type impurities at the surface of the semiconductor substrate (S103). For example, phosphorus (P) may be used as n-type impurities. As a result, an n-type semiconductor layer is formed in a part of the semiconductor substrate that functions as a p-type semiconductor layer, and the pn-junction part is formed in the interface region between the p-type semiconductor layer and the n-type semiconductor layer.
Thereafter, edge isolation is performed on the semiconductor substrate where the n-type semiconductor layer is formed (S104). Specifically, since n-type semiconductor regions are also formed on the sides of the semiconductor substrate due to the diffusion of phosphorus during the formation of the n-type semiconductor layer on the substrate, edge isolation is performed to remove the n-type semiconductor regions formed on the sides of the semiconductor substrate.
Next, an anti-reflection film is formed on the n-type semiconductor layer formed at the surface of the semiconductor substrate (S105). This anti-reflection film is composed of, for example, a silicon oxide film or a silicon nitride film, and is formed by, for example, a chemical vapor deposition (CVD) method.
Subsequently, a surface electrode is formed at the surface of the anti-reflection film (S106). This surface electrode is made of, for example, silver, and is formed by a printing method using silver paste. Thereafter, a back electrode is formed at the back surface of semiconductor substrate (S107). This back electrode is composed of, for example, aluminum, and is formed by a printing method.
Thereafter, a fire-through process is performed on the semiconductor substrate (S108). The fire-through process is a process in which through an application of a heat treatment of 800° C. or higher to the semiconductor substrate, the surface electrode formed on the anti-reflection film extends through the anti-reflection film and connects to the n-type semiconductor layer formed below the anti-reflection film. Through such a fire-through process, the surface electrode composed of a silver electrode is electrically connected to the n-type semiconductor layer.
Next, a conductive film that covers the surface electrode and is transparent to at least visible light and infrared light as main components of the sunlight is formed on the anti-reflection film (S109). This conductive film is composed of, for example, a film including indium and oxygen and/or a film including zinc and oxygen, and can be formed by using a solution coating method in air or a sputtering or evaporation method in a vacuum, for example.
In the above-described manner, the photovoltaic cell of the present embodiment can be manufactured.
Next, a schematic configuration of photovoltaic module PVM using photovoltaic cell CL of the present embodiment is described with reference to the drawings.
In
Next, features of the present embodiment are described.
A feature of the present embodiment is that conductive film CF that covers surface electrode SE is formed on anti-reflection film ARF as illustrated in
As a result, conductive film CF and n-type semiconductor layer NL have the same potential. This means that no electric field is generated inside anti-reflection film ARF, which is an insulating film sandwiched by conductive film CF and n-type semiconductor layer NL. That is, with a feature of the present embodiment in which conductive film CF that covers surface electrode SE is formed on anti-reflection film ARF, conductive film CF and n-type semiconductor layer NL that sandwich anti-reflection film ARF have the same potential, and as a result the electric field generated inside anti-reflection film ARF can be set to substantially zero.
Further, when the electric field generated inside anti-reflection film ARF can be set to substantially zero, it is possible to prevent cations such as sodium ions from reaching the inside of semiconductor substrate 1S including n-type semiconductor layer NL. Accordingly, in light of the knowledge that “PID” is caused by cations reaching the inside of semiconductor substrate 1S including n-type semiconductor layer NL, when a feature of the present embodiment in which conductive film CF that covers surface electrode SE is formed on anti-reflection film ARF is employed, “PID” can be effectively suppressed and as a result the reliability of the photovoltaic cell can be improved.
The following specifically describes that the above-described feature point can suppress “PID”.
In
In
Here, as illustrated in
As a result, for example, as illustrated in
In this manner, photovoltaic module PVM of the present embodiment can suppress “PID” due to migration of cations such as sodium ions into photovoltaic cell CL. Thus, the present embodiment can improve the reliability of photovoltaic module PVM.
From the viewpoint of suppressing “PID”, it is important to set the electric field generated inside anti-reflection film ARF to substantially zero, and this means that it is important to set conductive film CF and n-type semiconductor layer NL that sandwich anti-reflection film ARF to the same potential. Further, in order to set conductive film CF and n-type semiconductor layer NL that sandwich anti-reflection film ARF to the same potential, it is desirable that the conductivity of conductive film CF be high. A reason for this is that a low conductivity of conductive film CF means a high parasitic resistance of conductive film CF, and then the potential of conductive film CF easily floats from the potential of n-type semiconductor layer NL. In this case, a potential difference is generated between conductive film CF and n-type semiconductor layer NL that sandwich anti-reflection film ARF, and the electric field generated inside anti-reflection film ARF cannot be set to substantially zero. On the other hand, when the conductivity of conductive film CF is high, the parasitic resistance of conductive film CF is low, and the generation of a potential difference between conductive film CF and n-type semiconductor layer NL due to the parasitic resistance can be suppressed.
For example, desirably, the conductivity of conductive film CF is 10 siemens/cm or greater, as an exemplary specific numerical value. In this case, conductive film CF and n-type semiconductor layer NL that sandwich anti-reflection film ARF can be set to substantially the same potential, and it is confirmed that the generation of “PID” can be thus suppressed.
It should be noted that it is not enough to simply increase the conductivity of the conductive film CF. A reason for this is that when the conductivity is increased, the absorption of infrared rays by free electrons in conductive film CF is increased, which results in a decrease in the photoelectric conversion efficiency (decrease in photoelectric current) of the photovoltaic cell, making it difficult to improve the performance of the photovoltaic cell. It should be noted that since the conductivity is expressed as the product of the carrier mobility and the carrier concentration of conductive film CF, the generation of “PID” can be effectively suppressed while suppressing the reduction of the photoelectric current by increasing the conductivity by increasing the carrier mobility while suppressing the increase of the carrier concentration.
Next, measurement results that support the effectiveness of photovoltaic module PVM of the present embodiment in suppressing “PID” are described.
In
More specifically, as illustrated in
As a supplement, after the completion of the predetermined test time, photovoltaic cell module PVM is removed from thermostatic oven 100 and the maximum output retention is measured by using a solar simulator under standard test conditions. After completing the measurement, photovoltaic cell module PVM is introduced into thermostatic oven 100 again to resume the acceleration test.
In
Graph (1) of
In contrast, it can be seen that in the photovoltaic module of the present embodiment illustrated in graph (2) of
In contrast,
In the above-mentioned manner, it can be seen from the results of the acceleration test that the photovoltaic module of the present embodiment suppresses “PID” and can improve the reliability of the photovoltaic cell.
The technical ideas of the present embodiment may be applied to a photovoltaic cell having a passivated emitter rear cell (PERC) structure as well as to photovoltaic cell CL illustrated in
As can be seen from comparison between
Finally, the usefulness of the technical ideas of the present embodiment is described.
A knowledge as a basis of the technical ideas of the present embodiment is that one of the possible causes of PID is the migration of cations such as sodium ions into the photovoltaic cell, which is caused by the electric field applied to the inside the anti-reflection film. Further, on the basis of this knowledge, the present embodiment includes a configuration of suppressing the electric field that is applied to the inside of the anti-reflection film. Specifically, the technical idea of the present embodiment is an idea of setting the electric field generated inside the anti-reflection film to substantially zero by forming the conductive film on the anti-reflection film in a sandwiched manner between the conductive film and the n-type semiconductor layer having the same potential, and the capability of this technical idea for suppressing “PID” is supported as illustrated in
In this regard, for example, PTL 1, which is described in the “Background Art” section, describes the suppression of “PID” by forming the anti-reflection film in the photovoltaic cell from a silicon rich silicon nitride film. However, simply changing the composition of the anti-reflection film is not expected to significantly suppress “PID” because the electric field inside the anti-reflection film cannot be reduced to substantially zero. In other words, in order to effectively suppress “PID,” it is necessary to reduce the electric field generated inside the anti-reflection film to substantially zero, but in the above-mentioned PTL 1, there is no knowledge of reducing the electric field generated inside the anti-reflection film to substantially zero. In other words, while the technology described in PTL 1 focuses on the composition of the anti-reflection film to suppress “PID,” the important knowledge that the electric field applied inside the anti-reflection film is effective against “PID” is neither described nor suggested. That is, the novel knowledge discovered by the inventor captures the essence of suppressing “PID”, and the technical idea in the present embodiment embodied based on this knowledge is superior in that it can significantly suppress “PID”.
Furthermore, PTL 2, which is described in the “Background Art” section, describes a technology for adding a capturing additive that captures sodium ions to the encapsulant that encapsulates the photovoltaic cell. Specifically, although PTL 2 focuses on the fact that sodium ions are the main cause of “PID,” it does not pursue the issue in detail to the point where the problem is that cations represented by sodium ions migrate to the inside of the photovoltaic cell. In the measures described in PTL 2, for example, once the capturing material is saturated, the effect of capturing sodium ions is lost, and the suppression effect on “PID” is limited in that it does not focus on cations other than sodium ions. In contrast, the novel knowledge discovered by the inventor captures the essence for suppressing “PID,” and the technical idea embodied in the present embodiment based on this knowledge is superior in that it can significantly suppress “PID.
FIG. 5C of PTL 3, which is described in the “Background Art” section, describes a technology for forming a conductive layer on an anti-reflection coating. However, PTL 3 neither describes nor suggests the technical idea of the present embodiment of setting the conductive film and the n-type semiconductor layer to the same potential by electrically connecting the conductive film and the n-type semiconductor layer through the surface electrode. Further, PTL 3 does not describe or suggest even the knowledge of reducing the electric field generated inside the anti-reflection film to substantially zero, which is a motivation for achieving the technical idea of the present embodiment. In the first place, the photovoltaic cell in the present embodiment uses a p-type semiconductor substrate, which is inexpensive to manufacture, and the use of the p-type semiconductor substrate raises the problem of the “PID” that occurs when the photovoltaic cell has a negative potential relative to the frame potential. Specifically, PTL 3 uses an n-type silicon wafer as illustrated in FIG. 2 of PTL 3, and the basic configuration differs from that of the present embodiment. The “PID” that is focused on in PTL 3 is the so-called “Surface Polarization Effect,” which is a type of “PID” that occurs when the photovoltaic cell has a positive potential relative to the frame potential, assuming the use of n-type silicon wafers. In contrast, the “PID” focused on in the present embodiment is “PID” that occurs due to the p-type semiconductor substrate, which differs from the “PID” focused on in PTL 3. In other words, the “PID” that is focused on in the present embodiment is the “PID” that occurs when the photovoltaic cell has a negative potential relative to the frame potential. Therefore, it should be additionally noted that the technical idea of the present embodiment is completely different from the technology described in PTL 3.
The inventions made by the inventor are described above in detail based on the embodiments of the inventions, and it goes without saying that the present invention is not limited to the aforementioned embodiments and can be modified in various ways without departing from the gist thereof.
1S Semiconductor substrate
ARF Anti-reflection film
BE Back electrode
BS Back sheet
CF Conductive film
GS Cover glass
MF Module frame
NL N-type semiconductor layer
SE Surface electrode
| Number | Date | Country | Kind |
|---|---|---|---|
| 2019-013756 | Jan 2019 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2019/033299 | 8/26/2019 | WO | 00 |
