Photovoltaic device and making of the same

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a photovoltaic device and the making of the same, particularly relates to a photovoltaic device suitable for manufacturing using the diffusion of impurities and the making of the same.

[0003] 2. Description of the Related Art

[0004] For a photovoltaic device manufactured using the diffusion of impurities, photovoltaic devices having sectional structures shown in FIGS. 13A to 13F are known. The photovoltaic device having the structure shown in FIG. 13D is shown in FIG. 1C on pages from the 45th to the 48th of the 11th E.C. PHOTOVOLTAIC SOLAR ENERGY CONFERENCE) for example.

[0005] A reference number 1 in FIG. 13 denotes a P-type silicon semiconductor substrate, 4 and 8 denote an N-type impurity layer, 6 denotes a P-type impurity layer and 5, 7 and 10 denote an electrode.

[0006] Using the photovoltaic device described in the prior art and shown in FIG. 13D as a typical example, the manufacturing process will be described below, referring to FIGS. 14A to 14D.

[0007] First, as shown in FIG. 14A, a first SiO2 impurity diffusion protecting layer 11 is formed on the surface of a P-type silicon semiconductor substrate 1 using a thermal oxidation process at approximately 100 C. and photolithography, and a P-type impurity layer 6 is formed in an opening (not shown) by gas phase diffusion using gas 3 including P-type impurities in the silicon semiconductor substrate 1 as shown in FIG. 14B.

[0008] Next, as shown in FIG. 14B, the first SiO2 impurity diffusion protecting layer 11 is removed and after a second SiO2 impurity diffusion protecting layer 12 is formed using a thermal oxidation process and photolithography, an N-type impurity layer 4 is formed in an opening (not shown) by gas phase diffusion using gas 3 including n-type impurities in the silicon semiconductor substrate 1 as shown in FIG. 14C. Next, the second SiO2 impurity diffusion protecting layer 12 is removed.

[0009] Afterward, as shown in FIG. 14D, silver electrodes 5 and 7 are formed using screen printing as respective electrodes of the P-type impurity layer 6 and the N-type impurity layer 4.

[0010] In the manufacturing process, the semiconductor substrate 1 is exposed to high temperature of approximately 1000 C. by thermal oxidation when the two types of (the first and second) SiO2 impurity diffusion protecting layers 11 and 12 are formed and the minority carrier lifetime of the semiconductor substrate is deteriorated. Hereby, it is known that a problem that the photo-electric conversion efficiency of the photovoltaic device is remarkably deteriorated is caused.

[0011] This problem exists in not only the photovoltaic device having the structure shown in FIG. 13D but the photovoltaic devices having other structures shown in FIG. 13. It is also known that as the second SiO2 impurity diffusion protecting layer 12 is formed on the P-type impurity layer 6 as shown in FIG. 14B, a problem that impurities in the P-type impurity layer 6 are diffused again in the formation and an impurity profile changes is caused.

[0012] These problems also occur in the photovoltaic devices shown in FIGS. 13C, 13E and 13F in addition to the photovoltaic device shown in FIG. 13D out of the photovoltaic devices shown in FIG. 13 and make the design of the photovoltaic device difficult.

SUMMARY OF THE INVENTION

[0013] Therefore, the object of the invention is to solve these problems of the conventional type, concretely to provide a photovoltaic device and the making of the same that prevent the minority carrier lifetime of a semiconductor substrate from being deteriorated and that have high photo-electric conversion efficiency.

[0014] The object can be achieved by the making of the photovoltaic device including a process for printing or depositing material with a pattern for an impurity diffusion protecting layer on the surface of a semiconductor substrate and forming the impurity diffusion protecting layer and a process for forming a diffusion layer having an inverted pattern of the impurity diffusion protecting layer by diffusing impurities in the semiconductor substrate using the impurity diffusion protecting layer as a mask. For a method of diffusion for forming the diffusion layer having the inverted pattern of the impurity diffusion protecting layer, well-known diffusion technique such as gas phase diffusion using liquid and gas diffusion sources, implantation and further, plasma diffusion can be adopted.

[0015] The photovoltaic device according to the invention is characterized in that the impurity diffusion protecting layer is formed without exposing the semiconductor substrate to high temperature of approximately 1000 C. as in the prior art and is formed by printing or depositing in a pattern, as a result, the minority carrier lifetime of the semiconductor substrate can be prevented from being deteriorated and the photovoltaic device high in photo-electric conversion efficiency is acquired.

[0016] According to the invention, as the patterned impurity diffusion protecting layer can be formed in one process without using a pattern forming process using a thermal oxidation process and a photolithographic process which have been respectively heretofore adopted, the manufacturing process can be greatly simplified.

[0017] It is desirable that paste is made of high-viscosity material including silicon oxide for inorganic material and unnecessary impurities which are easily diffused in a semiconductor substrate made of silicon and others and which have an effect upon a conductive type and impurities such as heavy metal that deteriorates minority carrier lifetime are not included. For the caking additive of the high-viscosity material, an organic or inorganic resin component compatible with pattern formation by screen printing for example is used. A patterned printed or deposited layer is fired at the temperature of approximately 400 C. to be the impurity diffusion protecting layer.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018]
FIG. 1 are manufacturing process drawings schematically showing one sectional structure of a photovoltaic device according to the invention;

[0019]
FIG. 2 are manufacturing process drawings schematically showing one sectional structure of the photovoltaic device according to the invention;

[0020]
FIG. 3 are manufacturing process drawings schematically showing one sectional structure equivalent to a first embodiment of the photovoltaic device according to the invention;

[0021]
FIG. 4 are manufacturing process drawings schematically showing one sectional structure equivalent to a second embodiment of the photovoltaic device according to the invention;

[0022]
FIG. 5 are manufacturing process drawings schematically showing one sectional structure equivalent to the second embodiment of the photovoltaic device according to the invention;

[0023]
FIG. 6 are manufacturing process drawings schematically showing one sectional structure equivalent to a third embodiment of the photovoltaic device according to the invention;

[0024]
FIG. 7 are manufacturing process drawings schematically showing one sectional structure equivalent to a fourth embodiment of the photovoltaic device according to the invention;

[0025]
FIG. 8 are manufacturing process drawings schematically showing one sectional structure equivalent to the fourth embodiment of the photovoltaic device according to the invention;

[0026]
FIG. 9 are manufacturing process drawings schematically showing one sectional structure equivalent to a fifth embodiment of the photovoltaic device according to the invention;

[0027]
FIG. 10 are manufacturing process drawings schematically showing one sectional structure equivalent to a sixth embodiment of the photovoltaic device according to the invention;

[0028]
FIG. 11 are explanatory drawings schematically showing the plane pattern structure of an impurity diffusion protecting layer of the photovoltaic device according to the invention;

[0029]
FIG. 12 are sectional views of a substrate schematically explaining the irregularities of the surface of the substrate of the photovoltaic device according to the invention;

[0030]
FIG. 13 are sectional views showing one manufacturing process of a conventional type photovoltaic device; and

[0031]
FIG. 14 are sectional views showing one manufacturing process of the conventional type photovoltaic device.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0032] According to the invention, as described above, material for an impurity diffusion protecting layer is formed on the surface of a semiconductor substrate in a state in which the material is patterned, the number of heat treatment processes is reduced by forming a diffusion layer having an inverted pattern of the impurity diffusion protecting layer and the minority carrier lifetime of the semiconductor substrate can be prevented from being deteriorated. Further, the manufacturing cost can be also reduced by reducing an etching process.

[0033] Referring to FIGS. 1 and 2, the principle of the invention will be described below.

[0034]
FIG. 1 are process drawings showing one example of the making of a photovoltaic device according to the invention. First, as shown in FIG. 1A, high-viscosity paste including silicon oxide is printed and fired on one surface of a P-type silicon semiconductor substrate 1 in a pattern by screen printing and an impurity diffusion protecting layer 2 is formed. The firing temperature of the printed pattern is low temperature of approximately 400 C. and no deterioration of the minority carrier lifetime in the substrate 1 is caused.

[0035] Next, as shown in FIG. 1B, an N-type impurity layer 4 is selectively formed in a part where no impurity diffusion protecting layer 2 exists by gas phase diffusion using gas 3 including phosphorus which is impurities that function as an N type in silicon.

[0036] Next, as shown in FIG. 1C, the impurity diffusion protecting layer 2 is removed using the solution of a hydrofluoric acid.

[0037] Afterward, as shown in FIG. 1D, an aluminum electrode 5 is formed by printing and firing paste including aluminum in a pattern by screen printing and a P-type impurity layer 6 is formed under the electrode. A silver electrode 7 is formed as an electrode of the N-type impurity layer 4 by screen printing.

[0038] In the conventional type described referring to FIG. 14, the process for forming a film thermally oxidized at approximately 1000 C. on the surface of the semiconductor substrate and the process for forming an oxide film pattern by photolithography (including an etching process) are required, however, in the making according to the invention, as described above, the patterned diffusion layer 4 can be simply formed in only one process for forming the impurity diffusion protecting layer 2 including printing and firing a pattern.

[0039] The photovoltaic device having sectional structure shown in FIG. 2 can be formed by using the making. FIG. 2A is a sectional view showing the photovoltaic device manufactured using the P-type silicon semiconductor substrate 1. In this example, the photovoltaic device has structure that responds to both light 34 incident from the upside in FIG. 2A and light 35 incident on the back. The N-type impurity layer 4 and the electrode for an N type 7 are formed on the upper surface of the substrate, and the P-type impurity layer 6, the electrode for a P type 5 and the N-type impurity layer 4 connected to no electrode are formed on the lower surface (the back).

[0040] The structure of the lower surface shown in FIG. 2A is manufactured according to the making described referring to FIG. 1 and the N-type impurity layer 4 on the upper surface is formed simultaneously when the N-type impurity layer 4 on the lower surface is formed in the process shown in FIG. 1B.

[0041] As PN junction is formed between the N-type impurity layer 4 on the upper surface and the P-type substrate 1 in this structure, it is located in an upper part. Therefore, a response to the light 34 incident from the upside is higher than a response to the light 35 incident on the lower surface. The ratio of the response to the upper surface to the response to the lower surface greatly depends upon the minority carrier lifetime of the substrate 1 and others, and when the minority carrier lifetime of the substrate is long and as a result, the diffusion length of a minority carrier becomes approximately a triple of the thickness of the substrate 1, a response to the light 34 incident from the upside and a response to the light 35 incident on the lower surface become substantially similar. However, in the making according to the invention, as minority carrier lifetime is relatively short in a silicon substrate for a normal photovoltaic device though the deterioration of minority carrier lifetime is reduced by omitting heat treatment (the thermal oxidation of the surface of the substrate) at high temperature in the conventional type making, a response to the light 35 incident on the lower surface is smaller than that to the light 34 incident from the upside.

[0042] Then, a photovoltaic device of a type the conductive type of which is reverse to the structure shown in FIG. 2A, that is, having structure in which a P type and an N type are inverted and which is shown in FIG. 2B is manufactured using an N-type substrate the minority carrier lifetime of which is relatively long though the substrate has similar resistivity.

[0043] As a result, as shown in Table 1, open-circuit voltage and short-circuit current both have a larger value in the photovoltaic device manufactured using the N-type substrate and shown in FIG. 2B, compared with those in the photovoltaic device manufactured using the P-type substrate and shown in FIG. 2A.

[0044] The reason why the open-circuit voltage is high is that the minority carrier lifetime is mainly longer and the reason why the short-circuit current has a large value is that the carrier diffusion length is long. As a result, it proves that the photovoltaic device manufactured using the making according to the invention and having the structure according to the invention shows a higher characteristic by using the N-type substrate than a characteristic in case a P-type substrate is used.

1TABLE 1Open-circuit voltageIrradiationShort-circuit currentof upperIrradiation ofIrradiation ofIrradiation ofsurfacelower surfaceupper surfacelower surfaceP-type594 mV583 mV32.8 mA/cm2 24.0 mA/cm2substrateN-type613 mV604 mV34.9 mA/cm225.03 mA/cm2substrate

[0045] Embodiments

[0046] Referring to the drawings, embodiments of the invention will be concretely described below.

[0047] First Embodiment

[0048] Referring to manufacturing process drawings shown in FIG. 3, an embodiment in which a photovoltaic device according to the invention is manufactured using an N-type substrate will be described below.

[0049] As shown in FIG. 3A, for a substrate 33, an N-type monocrystalline silicon substrate is used and an impurity diffusion protecting layer 2 having the width of 100 μm and having an opening 44 on the lower surface is formed so that pitch 43 between the impurity diffusion protecting layers is 2.5 mm. The impurity diffusion protecting layer 2 is acquired by printing and firing high-viscosity paste including silicon oxide in a pattern by screen printing and as the impurity diffusion protecting layer is mainly made of SiO2, it has electric insulation performance.

[0050] Afterward, a P-type impurity layer 6 is formed on the lower surface by inserting the substrate 33 in the atmosphere at 1000 C. of diffusion gas 3 including boron which is a P-type impurity. A P-type impurity layer 6 is also simultaneously formed on the upper surface.

[0051] Next, as shown in FIG. 3B, after silver paste is printed in the opening 44 of the impurity diffusion protecting layer 2 according to a printing method, it is fired at 780 C. and a second electrode (a silver electrode) 7 for an N type is formed. For the formation of the electrode 7, antimony (Sb) is diffused in the substrate via the opening 44 by including Sb to be an N type in silicon in the silver paste beforehand simultaneously when the paste is fired, the impurity layer 6 is compensated and the N-type impurity layer 4 is formed.

[0052] As the impurity diffusion protecting layer 2 formed on the lower surface of the substrate has electric insulation performance, the electrode 7 and the P-type impurity layer 6 are electrically insulated. The case that antimony (Sb) which is relatively stable and is usable is used to form the N-type impurity layer 4 in the opening 44 is described above, however, it need scarcely be said that another material which has only to be an N type may be also used.

[0053] Further, as shown in FIG. 3C, a desired photovoltaic device is acquired by printing and firing a first electrode for a P type 5 over the upper surface of the substrate 33.

[0054] In the photovoltaic device having the structure described above, the ratio of the impurity diffusion protecting layer 2 to the whole area of the photovoltaic device is approximately 8%. Minority carriers are frequently recombined on an interface between the impurity diffusion protecting layer 2 and the silicon substrate 33. Therefore, when area which the impurity diffusion protecting layer 2 occupies is increased, the characteristics of the photovoltaic device such as open-circuit voltage and short-circuit current are deteriorated. When the occupied area exceeds 20%, the deterioration of open-circuit voltage becomes remarkable. Therefore, the ratio of the area which the impurity diffusion protecting layer 2 occupies is required to be 20% or less of the whole area of the photovoltaic device.

[0055] Short-circuit current out of responses to light incident on the lower surface substantially proportionally decreases as the ratio of the area which the impurity diffusion protecting layer 2 occupies increases. To reduce the manufacturing cost of the photovoltaic device per the quantity of power generation, the yield of short-circuit current to light incident on the lower surface is required to be increased possibly.

[0056] As current generated by the irradiation of the lower surface is less than current generated by the irradiation of the upper surface in most cases, the characteristics of the lower surface are required to be kept higher to equalize characteristics by the irradiation of the upper surface and characteristics by the irradiation of the lower surface and use the upper surface and the lower surface without distinction. For that purpose, it is desirable that the area of a part uncovered with the electrode 7 on the lower surface of the impurity diffusion protecting layer 2 formed on the lower surface is equivalent to 10% or less of the whole area of the photovoltaic device.

[0057] In this embodiment, the width of a part in which the electrode 7 on the lower surface is overlapped with a pair of impurity diffusion protecting layers 2 located on both sides is set to 100 μm. Therefore, the area of the part uncovered with the electrode 7 on the lower surface of a pair of impurity diffusion protecting layers 2 is 100 μm in total.

[0058] As pitch 43 between the impurity diffusion protecting layers 2 is 2.5 mm, the ratio of the area of the part uncovered with the electrode 7 on the lower surface of the impurity diffusion protecting layer 2 formed on the lower surface is equivalent to 4% of the whole area of the photovoltaic device. In comparison between current generated in case a prototype is formed using a wafer the minority carrier lifetime of which is relatively long and is irradiated from the upside using light of the same intensity and current generated in case the prototype is irradiated from the downside, the ratio of the current generated in case the lower surface is irradiated to the current generated in case the upper surface is irradiated is 95%.

[0059] In the above description, the representation of the upper surface and the lower surface is used, however, these are terms used to show positional relation in the drawings showing the sectional structure of the photovoltaic device and in case these photovoltaic devices are actually used or manufactured, they are not always used or manufactured with the upper surface on the upside. In the following description, they are similar.

[0060] Second Embodiment

[0061] Referring to FIGS. 4 and 5, a second embodiment will be described below. First, FIG. 4 show a case that a two-stage emitter is manufactured using a P-type silicon substrate 1.

[0062] First, as shown in FIG. 4A, an impurity diffusion protecting layer 2 including phosphorus (P) that shows a conductive type of an N type in the silicon substrate is formed on the upper surface of the substrate 1 having a P-type diffusion layer 6 on the lower surface beforehand by printing and firing paste mainly made of silicon oxide and including phosphorus. The quantity of phosphorus included in the impurity diffusion protecting layer 2 is set to a value the sheet resistivity of which is to be approximately 50 Ω/□ (square) by heat treatment at approximately 900 C.

[0063] The diffusion gas 3 including phosphorus is applied from the upside of the substrate, impurities are diffused at 900 C. for twenty minutes, a first N-type diffusion layer 4 having the sheet resistivity of approximately 50 Ω/□ is formed under the impurity diffusion protecting layer 2 and a second N-type diffusion layer 8 having the sheet resistivity of approximately 10 Ω/□ is formed in an opening 44 of the impurity diffusion protecting layer 2.

[0064] Next, as shown in FIG. 4B, a silver electrode 7 for an N type is formed over the upper surface and an aluminum electrode 5 for a P type is formed over the lower surface respectively by the similar making to that in the first embodiment. As described above, a photovoltaic device having emitter structure that sheet resistivity is small (the density of impurities is high) in only a lower part of the electrode can be simply manufactured by using the impurity diffusion protecting layer 2 including impurities.

[0065] In the above description, the impurity diffusion protecting layer 2 is left as it is, however, if necessary, the impurity diffusion protecting layer 2 is removed and afterward, a reflection reducing film may be also formed. The case that the electrode 7 is wider than the opening of the impurity diffusion protecting layer 2 is described above, however, the opening is made wider than the electrode to reduce contact resistance between the electrode 7 and the silicon substrate 1 and the whole electrode 7 may be also put on the second N-type diffusion layer 8.

[0066] Sectional process drawings shown in FIG. 5 show a case that two-stage BSF structure is manufactured.

[0067] First, as shown in FIG. 5A, an impurity diffusion protecting layer 2 including boron (B) that shows a conductive type of a P type in the silicon substrate is formed on the lower surface of the P-type silicon substrate 1 having an N-type diffusion layer 4 on the upper surface beforehand by printing and firing paste mainly made of silicon oxide and including boron.

[0068] The quantity of phosphorus included in the impurity diffusion protecting layer 2 is set to a value the sheet resistivity of which is to be approximately 50 Ω/□ by heat treatment at approximately 950 C. Diffusion gas 3 including boron is applied from the downside of the substrate, impurities are diffused at 950 C. for thirty minutes, a first P-type diffusion layer 6 having the sheet resistivity of approximately 50 Ω/□ is formed under the impurity diffusion protecting layer 2 and a second P-type diffusion layer 36 having the sheet resistivity of approximately 5 Ω/□ is formed in an opening 44 of the first P-type diffusion layer.

[0069] Next, as shown in FIG. 5B, a silver electrode 7 for an N type is formed over the upper surface and an aluminum electrode 5 for a P type is formed over the lower surface respectively by the similar making to the case of FIG. 4.

[0070] As described above, a photovoltaic device having BSF structure that sheet resistivity is small (the density of impurities is high) in only a lower part of the electrode can be simply manufactured by using the impurity diffusion protecting layer including impurities.

[0071] The case that phosphorus is used for P-type impurities and boron is used for N-type impurities is described above, however, it need scarcely be said that even if another material having the similar conductive type is used, the similar structure can be acquired, and in case such material is suitably selected and used, the similar effect can be also acquired by manufacturing the structure described above using such material. In the structure in which a P type and an N type are suitably inverted in the above description, the similar effect to effect in the structure described above can be also acquired. These are also similar in the following description.

[0072] Third Embodiment

[0073] Referring to sectional process drawings shown in FIG. 6, a third embodiment will be described below. In this embodiment, as shown in FIG. 6A, a passivation film 41 approximately 20 nm thick is formed on the upper surface and the lower surface of an N-type silicon substrate 33 by thermal oxidation at approximately 800 C.

[0074] An impurity diffusion protecting layer 2 having an opening 44 is formed on the passivation film 41 by the similar making to that in the first embodiment, as shown in FIG. 6B, a first P-type impurity layer 6 is formed on the lower surface using diffusion gas 3 including boron as P-type impurities and a second P-type impurity layer 36 low in the density of impurities is formed on the upper surface using gas 3 low in the density of impurities. In the formation of these impurity layers, a part uncovered with a diffusion protecting layer of the thin passivation film 41 shown in FIG. 6A becomes impurity glass in diffusion and is left on the surface of the substrate in which impurities are diffused. In this embodiment, the part is removed by a dilute hydrofluoric acid, however, the part may be also left.

[0075] Next, as shown in FIG. 6C, an electrode 7 and an N-type layer 4 under the electrode 7 are simultaneously formed by printing and firing the material of an electrode (silver paste) including antimony (Sb) in an opening 44 of the impurity diffusion protecting layer 2 according to the similar making to that in the first embodiment.

[0076] Finally, as shown in FIG. 6D, an electrode 5 is formed on the first P-type impurity layer 6 on the lower surface by the similar making to that in the first embodiment.

[0077] Owing to such structure, the recombination of minority carriers between the impurity diffusion protecting layer and the silicon substrate is reduced is reduced and current generated by light incident on the lower surface is increased, compared with the structure without the passivation film 41. Open-circuit voltage also rises.

[0078] The effect described above is effect acquired because the passivation film 41 exists between the impurity diffusion protecting layer 2 and the silicon substrate, and the structure of the other part and the making are not essential. A method of forming the passivation film 41 is not limited to thermal oxidation described above, and the passivation film may also be an oxide film and an SiNx film formed by plasma CVD and further, may be also a passivation film having passivation structure made of cesium (Cs) and using an electric charge and hetero structure using a-Si or others.

[0079] It need scarcely be said that it is also effective to use the passivation film in this embodiment in structure in the following fourth and fifth embodiments.

[0080] Fourth Embodiment

[0081] Referring to manufacturing process drawings shown in FIGS. 7 and 8, a fourth embodiment will be described below. A top view is shown on the upside in each drawing and a sectional view is shown on the downside in each drawing. In this embodiment, first as shown in FIG. 7A, an impurity diffusion protecting layer 2 having electric insulation performance is formed like a ladder on the upper surface of a P-type substrate 1 having a diffusion layer 4 on the lower surface by the similar making to that in the first embodiment, diffusion gas including phosphorus (P) is applied to the substrate using the impurity diffusion protecting layer as a mask and an N-type diffusion layer 4 is formed by the similar making to that in the second embodiment.

[0082] Next, as shown in FIG. 7B, the material of an electrode (aluminum paste in this embodiment) including impurities having a conductive type of an N type and having smaller width than the width of an opening 44 of the impurity diffusion protecting layer 2 is printed and fired, and a P-type aluminum electrode 5 and a P-type impurity layer 6 are simultaneously formed. As described above, as the impurity diffusion protecting layer 2 and the opening 44 are made wider than the electrode 5, the electrode 5 can be housed in a contact 19 even if the electrode slightly tilts or is slightly set off in printing. A subsequent process is not shown in FIG. 7, however, if necessary, as described in the first embodiment shown in FIG. 3, an electrode 7 such as a silver electrode for an N-type impurity layer 4 is formed and a photovoltaic device is manufactured.

[0083] However, in the above making, the area of the N-type impurity layer provided in the opening 44 of the impurity diffusion protecting layer 2 is large. As light incident on this part does not contribute to power generation, the photo-electric conversion efficiency of the photovoltaic device cannot be enhanced in this structure.

[0084] Then, as shown in FIG. 8A, an impurity diffusion protecting layer 2 having openings 44a and 44b forming two rows is formed. In this structure, as light incident on a floating N-type layer 45 being not in contact with the electrode 5 out of an N-type impurity layer in the opening contributes to power generation, the photo-electric conversion efficiency can be enhanced. The case that the openings are formed in two rows is described above, however, the area of the floating N-type layer is increased by increasing the number of rows more than two and further, the characteristics can be enhanced.

[0085] Fifth Embodiment

[0086] Referring to FIGS. 9A and 9B, a fifth embodiment will be described below. A top view is shown on the left side of each drawing and a sectional view is shown on the right side. In this embodiment, as shown in FIG. 9A, a P-type substrate 1 having a P-type impurity layer 6 on the lower surface and having an N-type impurity layer 4 on the upper surface is used and plural impurity diffusion protecting layers 2 are provided on the upper surface at an interval by the similar making to that in the first embodiment.

[0087] Afterward as shown in FIG. 9B, area in which an electrode 7 and the N-type impurity layer 4 are touched can be reduced by forming the electrode 7 on them. Though an electrode 5 is not shown, the electrode 5 is formed on the P-type impurity layer 6 if necessary and a photovoltaic device is manufactured.

[0088] As minority carriers in the part in which the electrode and the semiconductor layer are touched are recombined at high speed, open-circuit voltage is particularly deteriorated in case the area of the part is large. However, in the making in this embodiment, as the impurity diffusion protecting layer 2 exists on the N-type impurity layer 4 in the semiconductor layer, the area of the part in which the electrode and the N-type impurity layer 4 are touched can be reduced up to 20% or less, compared with a case that no impurity diffusion protecting layer exists and hereby, open-circuit voltage can be increased by approximately 10 mV.

[0089] Sixth Embodiment

[0090] Referring to FIG. 10, a sixth embodiment will be described below. As shown in FIG. 10A, in this embodiment, an N-type substrate 33 having a P-type impurity layer 6 on the lower surface and having an N-type impurity layer 4 on the upper surface is used and an impurity diffusion protecting layer 2 is formed on the upper surface of the substrate as an insulating layer having plural openings 44 by the similar making to that in the first embodiment.

[0091] Afterward, the area of a part in which an electrode 7 and the N-type impurity layer 4 are touched can be reduced by forming the N-type electrode 7 as shown in FIG. 10B. Though the following electrode is not shown, the electrode for the P-type impurity layer 6 is formed if necessary and a photovoltaic device is manufactured.

[0092] As minority carriers in the part in which the electrode 7 and the N-type impurity layer 4 in the semiconductor layer are touched are recombined at high speed, open-circuit voltage is particularly deteriorated in case the area of the part is large. However, in the making in this embodiment, as the impurity layer is touched to the electrode 7 in only a contact region 19, the contact region can be further reduced, compared with that in the structure in the fifth embodiment.

[0093] A part of the electrode 7 can be overlapped with the contact 19 without aligning the openings and the electrode by not only providing the openings 44 under the electrode 7 shown in FIG. 10B but arranging the electrodes at an interval equal to or narrower than the width of the electrode 7.

[0094] The methods of forming the impurity diffusion protecting layers 2 described in the above embodiments are not limited to screen printing and ink-jet printing may be also used. A silicon oxide film may be also deposited from the upside of a metal mask using the mask by plasma CVD and thermic CVD.

[0095] Also, an impurity diffusion protecting layer may be also formed by a silicon nitride film (an SiNx film). In case the impurity diffusion protecting layer is formed by the making according to the invention, a peculiar trend different from patterning according to conventional type photolithography appears. FIG. 11 schematically explain relation among the form and the position 23 of the impurity diffusion protecting layer 2 in pattern design, the actual contour and a mean position in the photovoltaic device according to the invention.

[0096] For example, in case an impurity diffusion protecting layer 2 having the form shown in FIG. 11A is printed, such irregularities that width 25 between an end face 21 at the leftmost end and an end face 22 at the rightmost end is 10 μm or more are made as shown in an enlarged view shown in FIG. 11B of a part A at the left end of a longitudinal pattern shown in FIG. 11A. Therefore, such irregularities that the width is 10 μm or more are also made in the peripheral contour along the end faces of a diffusion layer formed using the impurity diffusion protecting layer 2.

[0097] These irregularities are caused depending upon the precision of a printing screen mask and a metal mask, by the deformation of a printing screen caused by stress in printing and further, a drop of printing material. Generally, difference between irregularities in case photolithography is used is approximately 1 μm.

[0098] The mean position 24 of the contour at the left end is displaced on the left side by length 26 off the position 23 of the impurity diffusion protecting layer 2 in pattern design. This reason is that the relative positions of a printing screen or a metal mask and the semiconductor substrate 1 are displaced from a design value and in normal screen printing and normal printing using a metal mask, the displacement of approximately 20 μm or more is caused. Generally, displacement in case photolithography is used is approximately 1 μm.

[0099] In the case of screen printing, the occurrence of the blur of a pattern and a drop can be inhibited by setting the viscosity of paste material for manufacturing the impurity diffusion protecting layer 2 used for screen printing to fifty thousand to one million cp, desirably eighty thousand to four hundred thousand cp.

[0100] For a part B at the upper end of a lateral pattern shown in FIG. 11A, irregularities (width 31) having the similar pattern to the pattern shown in FIG. 11B and displacement 32 are also caused as shown in an enlarged view shown in FIG. 11C of the part B. Other reference numbers 27, 28, 29 and 30 respectively denote the uppermost part, a longitudinal mean position, the lowermost part and a longitudinal position in design. Therefore, pattern design in consideration of displacement is required.

[0101] Though the following multiple irregularities are not described in the description of the first to fifth embodiments, multiple irregularities 14 the maximum value 46 in height of which is approximately 10 μm and the minimum value in height of which is approximately 3 μm as shown in FIG. 12A may be provided on the surface of the photovoltaic device to prevent light from being reflected on the surface. In this case, each vertex of the irregularities 14 can be covered with the impurity diffusion protecting layer 2 by setting the viscosity for example of the material of the impurity diffusion protecting layer 2 according to the invention to a large value.

[0102] The height 46 of the irregularities can be made 2 μm or less by forming the irregularities 14 by reactive ion etching (RIE). In this case, the impurity diffusion protecting layer 2 having the more precise form can be manufactured by forming the impurity diffusion protecting layer 2 using material low in viscosity so that the thickness is 1 μm or less.

[0103] For the formation of the electrodes 5 and 7, photolithography can be also used in addition to a method of directly forming a pattern such as screen printing.

[0104] For the semiconductor substrate, a monocrystalline or polycrystalline substrate made of silicon, germanium or gallium arsenide and having the shape of a polygon such as a circle and a quadrangle can be used. The conductive type of the semiconductor substrate may be also any of an i type, a P type and an N type. Various impurity layers and the conductive types of the semiconductor substrate may be variously combined as long as they compose the photovoltaic device. For impurities, phosphorus, arsenic, antimony (respectively N-type impurities), boron, aluminum and gallium (respectively P-type impurities) may be used.

[0105] As described in detail above, the object described above can be achieved according to the invention. That is, the low-priced photovoltaic device the photo-electric conversion efficiency of which is high can be realized.

Photovoltaic device and making of the same

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