Photovoltaic Devices with Textured TCO Layers, and Methods of Making TCO Stacks

BACKGROUND

The present specification generally relates to photovoltaic devices. A photovoltaic device generates electrical power by converting light into electricity using semiconductor materials that exhibit the photovoltaic effect to generate current that is collected by conductive contacts.

One concern with the efficiency of photovoltaic devices is the energy loss due to light that is reflected away from the device instead of being absorbed and converted to electrical current. Light reflection may occur at the glass substrate, where incident light first strikes the photovoltaic device, or at layer interfaces within the transparent conductive oxide (TCO) stack itself. Anti-reflection coatings and features have thus been employed on the energy side (light incident side) of the photovoltaic device in an attempt to address this loss. However, a need still exists for alternative TCO layer stacks and better methods of making them that reduce the energy loss due to reflected light.

SUMMARY

Some embodiments provided herein relate to sputtering a transparent conductive oxide (TCO) material, such as a TCO material deposited on a glass substrate. These and additional features provided by the embodiments described herein will be more fully understood in view of the following detailed description, in conjunction with the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The embodiments set forth in the drawings are illustrative and exemplary in nature and not intended to limit the subject matter defined by the claims. Figures are not necessarily to scale such that the thickness of lines and layers may be exaggerated for clarity. The following detailed description of the illustrative embodiments can be understood when read in conjunction with the following drawings, where like structure is indicated with like reference numerals and in which:

FIG. 1 schematically depicts a photovoltaic device according to one or more embodiments shown and described herein;

FIG. 2 schematically depicts a substrate according to one or more embodiments shown and described herein;

FIG. 3 schematically depicts a photovoltaic device according to one or more embodiments shown and described herein;

FIG. 4 depicts a textured topography according to one or more embodiments shown and described herein;

FIG. 5 schematically depicts in cross section an exemplary sputtering chamber according to one or more embodiments shown and described herein;

FIG. 6 depicts a different textured topography according to one or more embodiments shown and described herein;

FIG. 7 is an enlarged view of the device of FIG. 7, showing an interfacial transition area according to one or more embodiments shown and described herein;

FIGS. 8A, 8B, 8C, and 8D are scanning electron micrographs (SEM) of surfaces of TCO layer stacks having varying textured topographies according to one or more embodiments shown and described herein;

FIGS. 9A, 9B, and 9C are cross-sectional scanning electron micrographs (SEM) of photovoltaic devices having varying textured topographies at an absorber interface according to one or more embodiments shown and described herein; and

FIG. 10 is a chart showing improvements in current density according to one or more embodiments shown and described herein.

DETAILED DESCRIPTION

Embodiments of methods of depositing a TCO material on a substrate, such as sputtering a TCO material on a glass substrate, used in a process for forming a photovoltaic device are described herein. Various embodiments of the photovoltaic device, methods of sputtering a TCO material, and methods for forming the photovoltaic device will be described in more detail herein.

Referring now to FIG. 1, an embodiment of a photovoltaic device 100 is schematically depicted. The photovoltaic device 100 can be configured to receive light and transform light into electrical signals, e.g., photons can be absorbed from the light and transformed into electrical signals via the photovoltaic effect. Accordingly, the photovoltaic device 100 can define an energy side 102 configured to be exposed to a light source such as, for example, the sun. The photovoltaic device 100 can also define an opposing side 104 offset from the energy side 102 such as, for example, by a plurality of material layers. It is noted that the term “light” can refer to various wavelengths of the electromagnetic spectrum such as, but not limited to, wavelengths in the ultraviolet (UV), infrared (IR), and visible portions of the electromagnetic spectrum. The photovoltaic device 100 can include a plurality of layers disposed between the energy side 102 and the opposing side 104. As used herein, the term “layer” refers to a thickness of material provided upon a surface. Each layer can cover all or any portion of the surface.

The photovoltaic device 100 can include a substrate 110 configured to facilitate the transmission of light into the photovoltaic device 100. The substrate 110 can be disposed at the energy side 102 of the photovoltaic device 100. Referring collectively to FIGS. 1 and 2, the substrate 110 can have a first surface 112 substantially facing the energy side 102 of the photovoltaic device 100 and a second surface 114 substantially facing the opposing side 104 of the photovoltaic device 100. One or more layers of material can be disposed between the first surface 112 and the second surface 114 of the substrate 110.

The substrate 110 can include a transparent layer 120 having a first surface 122 substantially facing the energy side 102 of the photovoltaic device 100 and a second surface 124 substantially facing the opposing side 104 of the photovoltaic device 100. In some embodiments, the second surface 124 of the transparent layer 120 can form the second surface 114 of the substrate 110. The transparent layer 120 can be formed from a substantially transparent material such as, for example, glass. Suitable glass can include soda-lime glass, or any glass with reduced iron content. The transparent layer 120 can have any suitable transmittance, including about 250 nm to about 1,300 nm in some embodiments, or about 250 nm to about 950 nm in other embodiments. The transparent layer 120 may also have any suitable transmission percentage, including, for example, more than about 50% in one embodiment, more than about 60% in another embodiment, more than about 70% in yet another embodiment, more than about 80% in a further embodiment, or more than about 85% in still a further embodiment. In one embodiment, transparent layer 120 can be formed from a glass with about 90% transmittance, or more. Optionally, the substrate 110 can include a coating 126 applied to the first surface 122 of the transparent layer 120. The coating 126 can be configured to interact with light or to improve durability of the substrate 110 such as, but not limited to, an antireflective coating, an anti-soiling coating, or a combination thereof.

Referring again to FIG. 1, the photovoltaic device 100 can include an optional barrier layer 130 configured to mitigate diffusion of contaminants (e.g., sodium) from the substrate 110, which could result in degradation or delamination. The barrier layer 130 can have a first surface 132 substantially facing the energy side 102 of the photovoltaic device 100 and a second surface 134 substantially facing the opposing side 104 of the photovoltaic device 100. In some embodiments, the barrier layer 130 can be provided adjacent to the substrate 110. For example, the first surface 132 of the barrier layer 130 can be provided upon the second surface 114 of the substrate 100. The phrase “adjacent to,” as used herein, means that two layers are disposed contiguously and without any intervening materials between at least a portion of the layers.

Generally, the barrier layer 130 can be substantially transparent, thermally stable, with a reduced number of pin holes and having high sodium-blocking capability, and good adhesive properties. Alternatively or additionally, the barrier layer 130 can be configured to apply color suppression to light. The barrier layer 130 can include one or more layers of suitable material, including, but not limited to, tin oxide, silicon dioxide, aluminum-doped silicon oxide, silicon oxide, silicon nitride, or aluminum oxide. The barrier layer 130 can have any suitable thickness bounded by the first surface 132 and the second surface 134, including, for example, more than about 500 Å in one embodiment, more than about 750 Å in another embodiment, or less than about 1200 Å in a further embodiment.

Referring still to FIG. 1, the photovoltaic device 100 can include a transparent conductive oxide (TCO) layer 140 configured to provide electrical contact to transport charge carriers generated by the photovoltaic device 100. The TCO layer 140 can have a first surface 142 substantially facing the energy side 102 of the photovoltaic device 100 and a second surface 144 substantially facing the opposing side 104 of the photovoltaic device 100. In some embodiments, the TCO layer 140 can be provided adjacent to the barrier layer 130. For example, the first surface 142 of the TCO layer 140 can be provided upon the second surface 134 of the barrier layer 130. Generally, the TCO layer 140 can be formed from one or more layers of n-type semiconductor material that is substantially transparent and has a wide band gap. Specifically, the wide band gap can have a larger energy value compared to the energy of the photons of the light, which can mitigate undesired absorption of light. The TCO layer 140 can include one or more layers of suitable material, including, but not limited to, tin dioxide, doped tin dioxide (e.g., F:SnO₂), indium tin oxide (ITO), or cadmium stannate (Cd₂SnO₄, or CTO). In some embodiments, the TCO layer stack 140 comprises multiple layers with varying refractive indices, as is described in more detail later.

The photovoltaic device 100 can include a buffer layer 150 configured to provide an insulating layer between the TCO layer 140 and any adjacent semiconductor layers. The buffer layer 150 can have a first surface 152 substantially facing the energy side 102 of the photovoltaic device 100 and a second surface 154 substantially facing the opposing side 104 of the photovoltaic device 100. In some embodiments, the buffer layer 150 can be provided adjacent to the TCO layer stack 140. For example, the first surface 152 of the buffer layer 150 can be provided upon the second surface 144 of the TCO layer 140. The buffer layer 150 may include material having higher resistivity than the TCO layer 140, including, but not limited to, tin dioxide, zinc magnesium oxide (e.g., Zn_1-xMg_xO), silicon dioxide (SnO₂), aluminum oxide (Al₂O₃), aluminum nitride (AlN), zinc tin oxide, zinc oxide, tin silicon oxide, or any combination thereof. In some embodiments, the material of the buffer layer 150 can be configured to substantially match the band gap of an adjacent semiconductor layer (e.g., an absorber). The buffer layer 150 may have any suitable thickness between the first surface 152 and the second surface 154, including, for example, more than about 100 Å in one embodiment, between about 100 Å and about 800 Å in another embodiment, or between about 150 Å and about 600 Å in a further embodiment. According to the embodiments, provided herein, a TCO layer stack 240 can include the barrier layer 130, the TCO layer 140, the buffer layer 150, or any combination thereof.

Referring again to FIG. 1, the photovoltaic device 100 can include an absorber layer 160 configured to cooperate with another layer to form a p-n junction within the photovoltaic device 100. Accordingly, absorbed photons of the light can free electron-hole pairs and generate carrier flow, which can yield electrical power. The absorber layer 160 can have a first surface 162 substantially facing the energy side 102 of the photovoltaic device 100 and a second surface 164 substantially facing the opposing side 104 of the photovoltaic device 100. A thickness of the absorber layer 160 can be defined between the first surface 162 and the second surface 164. The thickness of the absorber layer 160 can be between about 0.5 μm to about 10 μm such as, for example, between about 1 μm to about 7 μm in one embodiment, or between about 2 μm to about 5 μm in another embodiment.

According to the embodiments described herein, the absorber layer 160 can be formed from a p-type semiconductor material having an excess of positive charge carriers, i.e., holes. The absorber layer 160 can include any suitable p-type semiconductor material such as group II-VI semiconductors. Specific examples include, but are not limited to, semiconductor materials comprising cadmium, tellurium, selenium, or any combination thereof. Suitable examples include, but are not limited to, binary or ternary combinations of cadmium, selenium, and tellurium (e.g., CdSe_xTe_1-xwhere x may range from 0 to 1), or a compound comprising cadmium, selenium, tellurium, and one or more additional element.

In embodiments where the absorber layer 160 comprises tellurium and cadmium, the atomic percent of the tellurium can be greater than or equal to about 25 atomic percent and less than or equal to about 50 atomic percent such as, for example, greater than about 30 atomic percent and less than about 50 atomic percent in one embodiment, greater than about 40 atomic percent and less than about 50 atomic percent in a further embodiment, or greater than about 47 atomic percent and less than about 50 atomic percent in yet another embodiment. It is noted that the atomic percent described herein is representative of the entirety of the absorber layer 160, the atomic percentage of material at a particular location within the absorber layer 160 can vary with thickness compared to the overall composition of the absorber layer 160.

In embodiments where the absorber layer 160 comprises selenium and tellurium, the atomic percent of the selenium in the absorber layer 160 can be greater than about 0 atomic percent and less or equal to than about 25 atomic percent such as, for example, greater than about 1 atomic percent and less than about 20 atomic percent in one embodiment, greater than about 1 atomic percent and less than about 15 atomic percent in another embodiment, or greater than about 1 atomic percent and less than about 8 atomic percent in a further embodiment. It is noted that the concentration of tellurium, selenium, or both can vary through the thickness of the absorber layer 160. For example, when the absorber layer 160 comprises a compound including selenium at a mole fraction of x (x being between 0.05 and 0.95) and tellurium at a mole fraction of 1−x (Se_xTe_1-x), x can vary in the absorber layer 160 with distance from the first surface 162 of the absorber layer 160.

According to the embodiments provided herein, the absorber layer 160 can be doped with a dopant configured to manipulate the charge carrier concentration. In some embodiments, the absorber layer can be doped with a group I or V dopant such as, for example, copper, silver, arsenic, phosphorous, antimony, or a combination thereof. The total dosage of the dopant within the absorber layer 160 can be controlled. Alternatively or additionally, the amount of the dopant can vary with distance from the first surface 162 of the absorber layer 160.

Referring still to FIG. 1, the p-n junction can be formed by providing the absorber layer 160 sufficiently close to a portion of the photovoltaic device 100 having an excess of negative charge carriers, i.e., electrons or donors. In some embodiments, the absorber layer 160 can be provided adjacent to n-type semiconductor material, such as the TCO layer stack 140. Alternatively, one or more intervening layers can be provided between the absorber layer 160 and n-type semiconductor material. In some embodiments, the absorber layer 160 can be provided adjacent to the buffer layer 150. For example, the first surface 162 of the absorber layer 160 can be provided upon the second surface 154 of the buffer layer 150.

Referring now to FIG. 3, in some embodiments, a photovoltaic device 200 can include a window layer 170 comprising n-type semiconductor material. The absorber layer 160 can be formed adjacent to the window layer 170. The window layer 170 can have a first surface 172 substantially facing the energy side 102 of the photovoltaic device 100 and a second surface 174 substantially facing the opposing side 104 of the photovoltaic device 100. In some embodiments, the window layer 170 can be positioned between the absorber layer 160 and the TCO layer 20. In one embodiment, the window layer 170 can be positioned between the absorber layer 160 and the buffer layer 150. The window layer 170 can include any suitable material, including, for example, cadmium sulfide, zinc sulfide, cadmium zinc sulfide, zinc magnesium oxide, or any combination thereof.

Referring collectively to FIGS. 1 and 3, the photovoltaic device 100 can include a back contact layer 180 configured to provide electrical contact to the absorber layer 160. The back contact layer 180 can have a first surface 182 substantially facing the energy side 102 of the photovoltaic device 100 and a second surface 184 substantially facing the opposing side 104 of the photovoltaic device 100. A thickness of the back contact layer 180 can be defined between the first surface 182 and the second surface 184. The thickness of the back contact layer 180 can be between about 5 nm to about 200 nm such as, for example, between about 10 nm to about 50 nm in one embodiment.

In some embodiments, the back contact layer 180 can be provided adjacent to the absorber layer 160. For example, the first surface 182 of the back contact layer 180 can be provided upon the second surface 164 of the absorber layer 160. In some embodiments, the back contact layer 180 can be formed as a multi-layer configuration and comprise binary or ternary combinations of materials from groups I, II, VI, such as for example, one or more layers containing zinc, copper, cadmium, and tellurium in various compositions. Further exemplary materials include, but are not limited to, zinc telluride doped with copper telluride, or zinc telluride alloyed with copper telluride.

The photovoltaic device 100 can include a conducting layer 190 configured to provide electrical contact with the absorber layer 160. The conducting layer 190 can have a first surface 192 substantially facing the energy side 102 of the photovoltaic device 100 and a second surface 194 substantially facing the opposing side 104 of the photovoltaic device 100. In some embodiments, the conducting layer 190 can be provided adjacent to the back contact layer 180. For example, the first surface 192 of the conducting layer 190 can be provided upon the second surface 184 of the back contact layer 180. The conducting layer 190 can include any suitable conducting material such as, for example, one or more layers of nitrogen-containing metal, silver, nickel, copper, aluminum, titanium, palladium, chrome, molybdenum, gold, or the like. Suitable examples of a nitrogen-containing metal layer can include aluminum nitride, nickel nitride, titanium nitride, tungsten nitride, selenium nitride, tantalum nitride, or vanadium nitride. In certain embodiments the conducting layer can comprise three or more layers where the first layer is a nitride or oxynitride, e.g., MoN_x, TiN_x, CrN_x, WN_xor MoO_xN_yetc, the second layer is a conducting layer such as Al or an alloy of Al, and the third layer is a protective layer, e.g., Cr.

The photovoltaic device 100 can include a back support 196 configured to cooperate with the substrate 110 to form a housing for the photovoltaic device 100. The back support 196 can be disposed at the opposing side 102 of the photovoltaic device 100. For example, the back support 196 can be formed adjacent to conducting layer 190. The back support 196 can include any suitable material, including, for example, glass (e.g., soda-lime glass).

Referring still to FIGS. 1 and 3, manufacturing of a photovoltaic device 100, 200 generally includes sequentially disposing functional layers or layer precursors in a “stack” of layers through one or more processes, including, but not limited to, sputtering, spray, evaporation, molecular beam deposition, pyrolysis, closed space sublimation (CSS), pulse laser deposition (PLD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), electrochemical deposition (ECD), atomic layer deposition (ALD), or vapor transport deposition (VTD).

Manufacturing of a photovoltaic device 100, 200 can further include the selective removal of the certain layers of the stack of layers, i.e., scribing, to divide the photovoltaic device into 100, 200 a plurality of cells 210. For example, a first isolation scribe 212 (also referred to as P1 scribe) can be formed to ensure that the TCO layer stack 140 is electrically isolated between cells 210. Specifically, the first isolation scribe 212 can be formed though the TCO layer stack 140, the buffer layer 150, and the absorber layer 160 of photovoltaic device 100, or though the TCO layer stack 140, the buffer layer 150, the window layer 170, and the absorber layer 160 of photovoltaic device 200. Accordingly, the first isolation scribe 212 can be formed after the absorber layer 160 is deposited. The first isolation scribe 212 can then be filled with dielectric material before deposition of the back contact layer 180 and the conducting layer 190.

A series connecting scribe 214 (also referred to as P2 scribe) can be formed to electrically connect cells 210 in series. For example, the series connecting scribe 214 can be utilized to provide a conductive path from the conductive layer 190 of one cell 210 to the TCO layer stack 140 of another cell 210. The series connecting scribe 214 can be formed through the absorber layer 160, and the back contact layer 180 of photovoltaic device 100, or through the window layer 170, the absorber layer 160, and the back contact layer 180 of photovoltaic device 200. Optionally, the series connecting scribe 214 can be formed through some or all of the buffer layer 150. Accordingly, the series connecting scribe 214 can be formed after the back contact layer 180 is deposited. The series connecting scribe 214 can then be filled with a conducting material such as, but not limited to, the material of the conducting layer 190.

A second isolation scribe 216 (also referred to as P3 scribe) can be formed to isolate the back contact 190 into individual cells 210. The second isolation scribe 216 can be formed to isolate the conductive layer 190, the back contact layer 180, and at least a portion of the absorber layer 160. According to the embodiments provided herein, each of the first isolation scribe 212, the series connecting scribe 214, and the second isolation scribe 216 can be formed via laser cutting or laser scribing.

Referring now to FIG. 4, a modified photovoltaic device 300 is depicted. The photovoltaic device 300 includes a substrate 110, on which is sputtered at least a TCO layer stack 240. An absorber layer 160 is deposited by any suitable method on the TCO layer stack 240. The TCO layer stack 240 can have a first surface 242 substantially facing the energy side 102 of the photovoltaic device 300 and a second surface 244 substantially facing the opposing side 104 of the photovoltaic device 300. In this embodiment however, the second surface 244 of the TCO layer stack 240—which lies adjacent the first surface 162 of the absorber layer 160—exhibits a textured topography at this interface. The convention of designating this interface using the numerals of the two surfaces that form it, separated by a forward slash, is adopted herein (e.g. interface 244/162 for the interface mentioned immediately above). The textured topography can be thought of as a plurality of hills and valleys of varying height and diameter. As incident light 301 enters the photovoltaic device 300 from the energy side 102, the light 301 is still partially reflected. However, it is noted that the reflected portion 303 of the light 301 is reduced by the textured topography compared to the reflection of a smooth interface. Accordingly, the textured topography can increase light 305 that is transmitted into the absorber layer 160 as light 307 scatters at the textured interface 244/162. The increase in light 305 transmitted into the absorber layer 160 produces increased current in the photovoltaic device 300.

Although the textured topography is shown at the TCO layer stack/absorber interface (244/162) in the photovoltaic device 300 of FIG. 4, the textured topography can be positioned at any other interface within a photovoltaic device 300 up to and including the absorber layer 160. Consider, for example, the photovoltaic device 200 of FIG. 3. Any or all of the following interfaces of the TCO layer stack 240 could contain a textured topography in accordance with differing embodiments of the disclosure: substrate/barrier layer (114/132), barrier layer/TCO layer (134/142), or TCO layer/buffer layer (144/152). In embodiments, having a window layer 170, the buffer layer/window layer (154/172), or window layer/absorber (174/162) can also be textured. Furthermore, even the TCO layer stack 240 can comprise multiple layers, each having their own internal interfaces that can be textured. Under a given set of sputtering conditions, once a textured topography is begun, subsequent layers may adopt a similar texture. However, by selecting varying sputtering conditions, is may be possible to accentuate hills or smooth them, as desired.

As used herein “average roughness” is the measure of the magnitude of the texturing of a surface or interface. It should be understood that the process of sputtering can produce a distribution of hills and valleys, some higher, others lower; some wider, others narrower. Providing a textured topography as described herein may either accentuate or diminish such distribution. The “average roughness” estimates the mean height of the hills from the valley floor. Two methods are known for assessing average roughness. The first method is atomic force microscopy (AFM) which makes a 3-D image of the surface, and calculates an average roughness. The second method is ellipsometry which shines polarized light onto the surface and detects the reflected light and compares this to known models to estimate average roughness.

Referring now to FIG. 5, a general schematic is shown in cross-section of an exemplary sputtering chamber 60 according to one embodiment of the present invention. The exemplary sputtering chamber 60 is shown having a vertical orientation, although any other configuration can be utilized. The chamber 60 itself forms the anode 63; and the cathode 64 is formed in one wall of the chamber facing the substrate 110. The substrate 110 can held between first support 66 and second support 67, as shown, or alternatively, the substrate 110 can be supported on rollers or a conveyor in a horizontal orientation. Generally, the substrate 110 is positioned within the sputtering chamber 60 such that a sputtered layer 14 is formed on the surface facing the cathode 64. A power source 62 is configured to control and supply power to the chamber 60. Depending on the specific material to be sputtered or the specific substrate on which it is to be sputtered, the power may be supplied as either DV voltage or RF (alternating) voltage. As shown, via wires 68 and 69, respectively, the power source 62 applies a voltage to the cathode 64 to create a voltage potential between the cathode 64 and an anode 65 such that the substrate 110 is between the cathode 64 and anode 65. Although only a single power source 62 is shown, the voltage potential can be realized through the use of multiple power sources coupled together.

A sputtering environment control system 80 is depicted for introducing ionizable gases into the sputter chamber 60. Environment control system 80 includes a source of inert gas 81, and one or more sources of reactive gases 82, 83, and control valves for modulating the amount of gas released. The gas sources 81-83 are connected to the sputtering chamber 60 via one or more feed lines 84 and one or more inlets 85. In various embodiments, the source of inert gas 81 can be argon or nitrogen; and the source of reactive gas 82, 83, can include, for example, hydrogen, oxygen, H₂O, a mixture of Ar and O₂, a mixture of Ar and H₂, a mixture of N₂and O₂, and a mixture of N₂and H₂. When hydrogen is among the reactive gases, it is preferable to mix it in low percentages with the inert gas as shown at 82. Oxygen may have a dedicated inlet to the sputtering chamber 60. The environment control system 80 can be communicatively coupled to one or more processors 72, which is generally depicted in FIG. 4 as double-arrowed lines. As used herein, the term “communicatively coupled” means that the components are capable of exchanging data signals with one another such as, for example, electrical signals via conductive medium, electromagnetic signals via air, optical signals via optical waveguides, and the like.

A plasma field 70 is created once the sputtering atmosphere is ignited, and is sustained in response to the voltage potential between the cathode 64 and the chamber wall acting as an anode 63. The voltage potential causes the plasma ions within the plasma field 70 to accelerate toward the cathode 64, causing atoms from the cathode 64 to be ejected toward the surface on the substrate 110. As such, the cathode 64 is also referred to as a “target” and acts as the source material for the formation of the sputtered layer 14 on the surface facing the cathode 64. The nature of the cathode 64 is dependent on the layer or layers to be sputtered. It can be a metal or alloy target, such as elemental tin, elemental zinc, or mixtures thereof; or a ceramic target. Additionally, in some embodiments, a plurality of cathodes 64 can be utilized. A plurality of cathodes 64 can be particularly useful to form a layer including several types of materials (e.g., co-sputtering). Since the sputtering atmosphere contains typically contains oxygen gas, oxygen particles of the plasma field 70 can react with the ejected target atoms to form an oxide layer on the sputtered layer 14 on the substrate 110.

For a non-limiting example, the TCO layer stack 240, or any layers thereof, can be formed via sputtering at the specified sputtering temperature from a metal target to form a TCO layer stack 240 on the substrate 110 in an atmosphere containing an inert gas (e.g., argon) and oxygen (e.g., about 0% to about 20% by volume oxygen). Any of the compositions and materials previously discussed as constituents of the layers of the TCO layer stack 240 such as, for example, barrier layers 130 and buffer layers 150 can be deposited by such a sputtering process.

According to the embodiments described herein, a processor 72 means any device capable of executing machine readable instructions. Accordingly, each of the one or more processors 72 may be a controller, an integrated circuit, a microchip, a computer, or any other computing device. The one or more processors 72 can be configured to execute logic or software and perform functions as discussed in more detail below. For example, in some embodiments, the processor 72 can be programmed to control the sputtering environment by controlling valves and regulating flow rates for the inert carrier, and any reactive gases, such as hydrogen or oxygen. In some embodiments, the processor 72 can be programmed to heat or cool the substrate to a desired temperature, or to increase or decrease the voltage to alter the magnetic field strength. Additionally, the one or more processors 72 can be communicatively coupled to one or more memory components that can store the logic and/or input received by the one or more processors 72. The memory components described herein may be RAM, ROM, a flash memory, a hard drive, or any device capable of storing machine readable instructions.

Embodiments of the present disclosure comprise logic that includes machine readable instructions or an algorithm written in any programming language of any generation (e.g., 1GL, 2GL, 3GL, 4GL, or 5GL) such as, e.g., machine language that may be directly executed by the processor, or assembly language, object-oriented programming (OOP), scripting languages, microcode, etc., that may be compiled or assembled into machine readable instructions and stored on a machine readable medium. Alternatively, the logic or algorithm may be written in a hardware description language (HDL), such as logic implemented via either a field-programmable gate array (FPGA) configuration or an application-specific integrated circuit (ASIC), and their equivalents. Accordingly, the logic may be implemented in any conventional computer programming language, as pre-programmed hardware elements, or as a combination of hardware and software components.

For some TCO stack layer 140 materials, an annealing step is beneficial. Annealing by heat energy or by laser energy is common in the industry of photovoltaic devices and need not be described in detail herein.

It has been observed that photovoltaic devices 100, 200, 300 having TCO layer stack 240 with certain desired roughness attributes create more internal reflection than smooth films generally deposited by a sputtering processes. However, by carefully controlling the sputtering conditions and sputtering environment, it has been found that layers of the TCO layer stack 240 that have improved internal reflection can be produced by a sputtering process.

Referring now to FIGS. 6 and 7, another embodiment of a photovoltaic device 400 having a textured topography is shown. The photovoltaic device 400 can be compositionally similar to that the photovoltaic device 100 of FIG. 1, however scribing has been omitted for clarity. Upon substrate 110 are deposited the flowing layers of the TCO layer stack 240 in order: optional barrier layer 130, TCO layer 140, and the buffer layer 150. Then the following layers can be deposited: absorber layer 160, back contact 180, conductor material 190, and back support 196. The photovoltaic device 400 differs from the photovoltaic device 100 of FIG. 1, however, in having a textured topography beginning with the TCO layer/buffer layer interface 144/152, i.e., the interface between the second surface 144 of the TCO layer 140, (the surface away from the energy side of the device) and the first surface 152 of the buffer layer 150. The textured topography is carried over the buffer layer/absorber layer interface 154/162 as well; that interface formed at the second surface 154 of the buffer layer 150 and the first surface 162 of the absorber layer 160. It can be observed that the precise texturing at the buffer layer/absorber layer interface 154/162 can vary from the texture at the TCO layer/buffer layer interface 144/152.

FIG. 7 depicts an enlarged portion of the textured topography region of the photovoltaic device 400. Shown here (bounded by dotted lines for clarity) are two interfacial transition areas 448 and 458. Interfacial transition area 448 is defined by the lowest valley 449 and highest hill 450 of the second surface 144 the TCO layer 140. Similarly, interfacial transition area 458 is defined by the lowest valley 459 and highest hill 460 of the second surface 154 of the buffer layer 150. Consequently, as used herein, an “interfacial transition area” means an intermediate layer where adjacent deposited layers intermingle due to the textured topography hills and valleys of the underlying layer. Within interfacial transition area 448 the semiconductor material of the buffer layer 150 extends into and fills in the valleys of the TCO semiconductor material of the TCO layer 140; and within interfacial transition area 458 the semiconductor material of the absorber layer 160 extends into and fills in the valleys of the semiconductor material of the buffer layer 150. This intermingling of different semiconductor materials provides physical properties within these interfacial transition areas 448, 458 that are hybrids of the individual semiconductor materials within the interfacial transition areas.

One important such physical property is the refractive index, n. It is known from the Fresnel Equations, that reflection of unpolarized light at the interface between two media increases as the difference or “delta” between their respective refractive indices, n₁and n₂, increases. Minimizing the refractive index delta at each such interface can reduce the light reflected and increase the light transmitted. For example, in a photovoltaic device 100, 200, 300, 400 like that of FIGS. 1, 3, 6 and 7, a substrate 110 can have a refractive index of about 1.5, e.g., when formed from glass. An absorber layer 160 from a cadmium-based absorber has a refractive index of about 3.0. If a TCO layer 140 has a refractive index of about 1.8 and a buffer layer 150 has a refractive index of about 2.0, then it is possible to create one interfacial transition area between the TCO layer 140 and buffer layer 150 having an effective refractive index of about 1.9; and a second interfacial transition area between the absorber layer 160 and buffer layer 150 having an effective refractive index of about 2.5. Accordingly, each layer interface that includes a textured topography creates an intermediate interfacial transition region that acts as if the device had additional interface. At the same time, the hybrid nature of the interfacial transition areas make the delta in effective refractive index lesser at each step, producing a more gradual gradient in refractive indices. In embodiments with an optional barrier layer 130, the barrier layer 130 composition and/or surface texture may be selected so as to form an additional increment of the gradual gradient refractive index. These features combine to reduce reflection and contribute to more electrical current and power from the device.

By controlling the conditions of sputtering, it is possible to create the textured topography described and shown herein. Conditions known to control the textured topography and the effect each has on average roughness of the topography over ranges tested are shown in Table A, below.

TABLE A

Conditions and Effects on Topography Roughness

Condition
Ranges
Effect

Amount of oxygen
From 0 to about 40 sccm, e.g. 3
Greater oxygen flow

flowing into the
to about 20 sccm, or 5 to about
produced smoother sputtering

sputtering chamber
15 sccm
topography

Amount of hydrogen
From 0 to about 3% (added to
Greater hydrogen flow

flowing into the
argon carrier); e.g. 1% to 3% or
produced rougher sputtering

sputtering chamber
1% to 2%
topography; and hydrogen

added to oxygen contributed

to rougher surfaces.

Temperature of
From about 25 to about 400° C.;
As substrate temperature

substrate
e.g. from about 200 to about
increases, so does roughness

400° C.; or from about 300 to

about 380° C.

Initial roughness of a
From about 0 to about 10
Glass may be indented or

substrate
microns; e.g. from about 5 nm
etched to provide an initial

to about 2 micron; or from
roughness; this may be

about 20 to about 300 nm.
maintained or varied by

sputtering conditions.

Strength of magnetic
From about 20 to about 100
As magnetic field strength

field (flux density)
milli-Teslas (mT); e.g. from
increases, so does roughness

about 40 to about 90 mT; or

from about 60 to about 80 mT.

Referring again to FIG. 5, a sputtering chamber 60 is shown. A sputtering environment control system 80 is depicted for introducing various gases into the sputter chamber 60. The environment control system 80 can be communicatively coupled to one or more processors 72, which is generally depicted in FIG. 5 as double-arrowed lines. The control system 80 can be programmed with machine readable instructions to automatically adjust the sputtering condition parameters to achieve the desired effect. As a non-limiting example, starting on a smooth substrate, layers of materials may be sputtered with decreasing amounts of oxygen at each layer to enhance the roughness and build the “hills” higher to widen the interfacial transition areas. Alternatively, subsequent layers of materials may be sputtered with increasing amounts of oxygen and/or hydrogen at each layer to smooth the roughness of an initially textured substrate. For greatest roughness effect, the control system can be configured to sputter layers with little or no oxygen or hydrogen supplement and at higher temperatures and/or higher magnetic field strength.

EXAMPLES
Example 1

TCO layer stacks 240 were prepared by sputtering on a glass substrate in an argon environment supplemented with oxygen at varying flow rates as shown in Table B. Oxygen flow is defined by Standard cubic centimeters per minute (sccm). SEM images of the roughness of the resulting TCO layer stacks 240 are shown in FIGS. 8A to 8D. The effect of decreasing roughness with increases oxygen flow can be seen.

TABLE B

TCO layer stacks with varying degrees of roughness

Device
A
B
C
D

Oxygen Flow
0 sccm
7.5 sccm
10 sccm
12.5 sccm

Results FIG.
8A
8B
8C
8D

Example 2

Three photovoltaic devices 901, 910, 930 were prepared by sputtering successive layers as described herein. Roughness was varied by varying the condition of oxygen and hydrogen content of the sputtering environment. Average roughness was determined by ellipsometry. The ellipsometry results are in Table C and cross-sectional SEMs of the devices at the buffer layer/absorber layer interface 154/162 are depicted in FIGS. 9A to 9C. In FIG. 9A, device 901 can be observed based on the scale bar 902, which depicts a 400 nm scale, that some of the larger hills 904, which form grain-like geometry at the interface, at the second surface 244 of the TCO layer stack 240 are more than 100 nm in size. In FIG. 9B, device 910 can be observed based on the scale bar 912, which depicts a 200 nm scale, to have hills 914 having a size at an intermediate level at the second surface 244 of the TCO layer stack 240, with the hills 914 having sizes falling between the size of the hills 904 in device 901 and the hills 934 of the device 930. In FIG. 9C, device 930 can be observed based on the scale bar 932, which depicts a 200 nm scale, with hills 934 at the second surface 244 of the TCO layer stack 240 having the smallest size.

TABLE C

Ellipsometry of PV devices having varying degrees of roughness

Device
1
2
3

Oxygen Flow
6
sccm
15
sccm
15
sccm

Hydrogen concentration
0%
2.4%
0%

(wt % mixed with Ar)

Roughness by Ellipsometry
28.8
nm
11.4
nm
5.5
nm

Results FIG.
9A
9B
9C

Additionally, these three devices 901, 910, 930 were measured for current density (mA/cm²) by a quantum efficiency measurement system. Compared to device 930 having the second surface 244 of the TCO layer stack 240, which is formed at buffer layer/absorber layer interface 154/162 (See, e.g., FIG. 7), at 5.5 nm has a current density of about 23.24 mA/cm², device 901 with the roughest second surface 244 of the TCO layer stack 240, i.e., absorber interface, (28.8 nm) had a current flow increase of about 1.7% to about 23.65 mA/cm², and device 902 with intermediate roughness at the second surface 244 of the TCO layer stack 240 had a current flow increase of about 0.5% to about 23.35 mA/cm². These data points are plotted in FIG. 10.

According to the embodiments provided herein, a method for manufacturing a photovoltaic device can include sputtering onto a substrate at least one transparent metal oxide layer in an inert sputtering environment. The inert sputtering environment with can be controlled with oxygen at a flow rate of from about 0.1 sccm to about 30 sccm. A sputtered transparent conductive oxide layer stack can be produced having at least one interface with an average roughness greater than about 5 nm. Alternatively or additionally, the transparent conductive oxide layer stack can be annealed.

According to the embodiments provided herein a thin film transparent conductive oxide layer stack can include sputtering onto a substrate at least one transparent metal oxide layer in an inert sputtering environment. The inert sputtering environment can be controlled with oxygen at a flow rate of from about 0.1 sccm to about 30 sccm. A sputtered transparent conductive oxide layer stack can be produced having at least one interface with an average roughness greater than about 5 nm. Alternatively or additionally, the transparent conductive oxide layer stack can be annealed. Alternatively or additionally, the average roughness is from about 5 nm to about 200 nm. Alternatively or additionally, the average roughness is from about 5 nm to about 120 nm. Alternatively or additionally, the average roughness is from about 5 nm to about 60 nm. Alternatively or additionally, the average roughness is from about 5 nm to about 30 nm.

According to another embodiment, a thin film transparent oxide layer stack can include sputtering onto a substrate at least one transparent metal oxide layer in an inert sputtering environment. The inert sputtering environment can be controlled with oxygen at a flow rate of from about 0.1 sccm to about 30 sccm. A sputtered transparent oxide layer stack can be produced having at least one interface with an average roughness greater than about 5 nm. Alternatively or additionally, the transparent conductive oxide layer stack can be annealed.

In a further embodiment, a method for manufacturing an improved thin film transparent oxide layer for use with an associated absorber layer can include sputtering onto a substrate one or more transparent metal oxide layers under conditions selected to produce a sputtered transparent oxide layer having at least one interface having an average roughness when annealed of 5 to 60 nm, said sputtering conditions being selected from (i) supplementing an inert sputtering or annealing environment with oxygen or hydrogen, (ii) increasing the substrate temperature to a range from about 25 to about 400° C., and (iii) increasing a magnetic field strength associated with the sputtering process to a range from about 20 mT to about 100 mT. Upon exposure to incident light, the roughness of the at least one interface of the transparent oxide layer reduces reflection and increases light scattering transmission into the associated absorber layer.

In yet another embodiment, a photovoltaic device can include a substrate a transparent layer stack, and an absorber layer. The transparent conductive layer stack can include at least two transparent metal oxide layers having different refractive indices to form a transparent oxide layer stack in which at least one interface between two metal oxide layers within the transparent conductive oxide layer stack or at least one interface between the transparent conductive oxide layer stack and an adjacent layer has an average roughness of 5 to 60 nm. The absorber layer can be disposed on the transparent layer stack. The roughness of the at least one interface of the transparent oxide layer stack produces an interfacial transition area having an effective refractive index that is intermediate the refractive indices of the two adjacent layers to form a more gradual gradient of refractive indices.

While particular embodiments have been illustrated and described herein, it should be understood that various other changes and modifications may be made without departing from the spirit and scope of the claimed subject matter. Moreover, although various aspects of the claimed subject matter have been described herein, such aspects need not be utilized in combination. It is therefore intended that the appended claims cover all such changes and modifications that are within the scope of the claimed subject matter.

Photovoltaic Devices with Textured TCO Layers, and Methods of Making TCO Stacks

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