Patent Application
20150214398
The present invention relates to a photovoltaic element and a manufacturing method thereof, and particularly relates to a heterojunction photovoltaic element configured by combining an amorphous semiconductor layer and a crystalline semiconductor substrate and a manufacturing method thereof.
Crystalline solar cells using a crystalline semiconductor substrate have a high photoelectric conversion efficiency. In particular, crystalline silicon solar cells using a crystalline silicon substrate have already been widely put into practical use. Specially, as a heterojunction solar cell using an amorphous or microcrystalline semiconductor thin film for a conductive thin film, a solar cell that has an intrinsic semiconductor thin film between the conductive thin film and the crystalline substrate has been developed. In this solar cell, the intrinsic semiconductor film between the crystalline surface and the conductive thin film has a function of passivating defects on the surface and preventing loss due to diffusion of impurities from the conductive thin film and recombination of carriers; therefore, this solar cell can obtain a high open circuit voltage and thus has a high photoelectric conversion efficiency.
In such a solar cell, in order to improve the characteristics, it is necessary to increase the short circuit current and the fill factor while maintaining a high open circuit voltage. In order to increase the short circuit current, it is important to increase the optically and electrically effective incident surface as much as possible so that more light is absorbed. Moreover, it is important for the fill factor to increase the parallel resistance sufficiently while reducing the series resistance as much as possible over the whole region of the element. To that end, it is important that a transparent conductive film is arranged such that the series resistance is electrically sufficiently low.
In order to realize this ideal state, it is necessary to cover the whole surface of the substrate with a passivation film to passivate defects, then cover the whole surface of the light receiving surface (incident surface) of the substrate with, as an emitter layer, a semiconductor layer having a conductivity type different from that of the substrate, and then cover the whole surface of the emitter layer formed on the incident surface of the substrate with a transparent conductive film. At the same time, it is necessary to cover the back surface with a semiconductor layer having the same conductivity type as that of the substrate and cover the semiconductor layer with an electrode.
However, in reality, with CVD methods that have been used for manufacturing semiconductor layers, a film is, in some cases, deposited such that it wraps around the side surfaces or the opposite surface of the substrate, which are surfaces other than the deposition target surface. This may result in the failure of the formation of a junction as designed near the end portion of the substrate and therefore a reduction in characteristics due to the failure in collecting carriers may be caused. Moreover, even when a conventional sputtering method is used as a deposition method of a transparent conductive film, a film is deposited on the main surface and is also deposited such that it wraps around the side surfaces. Consequently, positive and negative electrodes are short-circuited at the side surfaces, the end portion of the deposition target surface, or the end portion of the opposite surface; therefore, the characteristics easily degrade.
A technology is disclosed in Patent Literature 1 in which an intrinsic amorphous semiconductor, a second-conductivity-type amorphous semiconductor layer, and a conductive thin film are deposited such that they wrap around from the first main surface to the side surfaces of the crystalline semiconductor substrate, an intrinsic amorphous semiconductor, a first-conductivity-type amorphous semiconductor, and a conductive thin film are deposited such that they wrap around the second main surface and the side surfaces, and thereafter, positive and negative electrodes are separated from each other by forming grooves on any of the main surfaces with a laser or the like, thereby maintaining a maximum effective region of the passivation film while preventing leakage.
However, when grooves are formed on the surface on which a junction is formed with a different conductivity type, although leakage can be prevented, carriers cannot be collected in the region outside the formed grooves and thus the effective area is reduced. Moreover, when grooves are formed on the surface on which a junction is formed with the same conductivity type, positive and negative electrodes are short-circuited through the substrate and thus leakage current cannot be ignored. Consequently, degradation of the characteristics is significant. In either case, an additional process for forming the grooves is necessary and the process becomes complicated because of the formation of the grooves on the passivation film and the conductive film.
A configuration is disclosed in Patent Literature 2 in which an intrinsic semiconductor layer and a conductivity-type semiconductor layer are deposited on the back surface side of a crystalline semiconductor substrate, in the order that they appear in this sentence, by using a mask such that they have a smaller area than that of the substrate, thereby preventing leakage at the end portion of the substrate. Additionally, a technology is disclosed in which an intrinsic semiconductor layer is first deposited on the whole surface of the substrate and then a conductivity-type semiconductor layer is deposited, thereby passivating the whole surface.
However, with the method of depositing an intrinsic semiconductor layer with a smaller area than that of the substrate, there is no intrinsic semiconductor layer on part of the back surface and thus the surface thereof cannot be passivated; therefore, generated carriers are recombined and thus the characteristics are significantly degraded. Moreover, with the method of first depositing an intrinsic semiconductor layer on the whole surface of the substrate, although a passivation film is formed on the whole surface of the substrate, there is no method of preventing leakage at the end portion due to the transparent conductive film formed on the passivation film, which leads to a reduction in the open circuit voltage and the short circuit current.
A technology is disclosed in Patent Literature 3 in which after a first-conductivity-type amorphous silicon layer and an electrode layer are deposited on the first main surface of a single-crystal silicon substrate, a contact prevention layer is formed to prevent leakage, and then a second-conductivity-type amorphous silicon layer and an electrode layer are formed on the second main surface.
However, it is necessary to perform an additional process for forming the contact prevention layer that prevents leakage and the process of forming a thick dielectric layer only on the side surfaces has poor production characteristics and is not easy to perform. Moreover, it is necessary to form an electrode layer on the first main surface before an amorphous semiconductor layer is formed on the second main surface and, at this point, the electrode layer often comes into contact with the surface of the substrate on which the passivation film is not present because the electrode layer wraps around the end portion of the second main surface, which leads to a reduction in the effective area and degradation of the characteristics, such as a reduction in the open circuit voltage.
Patent Literature 1: Japanese Patent No. 3349308
Patent Literature 2: Japanese Patent No. 3825585
Patent Literature 3: Japanese Patent Application Laid-open No. 2011-60971
However, with the above conventional technologies, it is necessary to perform an additional complicated process to prevent leakage current or to limit the effective area such that it is smaller than the substrate to prevent leakage current; therefore, there is a problem in that efficiency is reduced.
The present invention has been achieved in view of the above and an object of the present invention is to obtain a photovoltaic element that does not need an additional new process, that has a high efficiency because the entire main surface on the light receiving surface side of the substrate and the entire side surfaces of the substrate are an effective area, and that is capable of preventing leakage current, and a manufacturing method thereof.
In order to solve the above problems and achieve the object, a photovoltaic element according to the present invention including: a first-conductivity-type semiconductor substrate that includes a first main surface, a side surface, and a second main surface; a second-conductivity-type semiconductor layer that is formed such that the second-conductivity-type semiconductor layer entirely covers the first main surface of the semiconductor substrate and covers a peripheral portion of the second main surface by wrapping around the side surface from the first main surface; a first intrinsic semiconductor layer that is interposed between the second-conductivity-type semiconductor layer and the semiconductor substrate; a first transparent conductive film that is formed such that the first transparent conductive film is in contact with the second-conductivity-type semiconductor layer and extends to the side surface from the first main surface; a first-conductivity-type semiconductor layer that is formed over the second main surface of the semiconductor substrate; a second intrinsic semiconductor layer that is interposed between the first-conductivity-type semiconductor layer and the semiconductor substrate; and a second transparent conductive film that is provided over a second main surface of the semiconductor substrate such that the second transparent conductive film is in contact with the first-conductivity-type semiconductor layer, wherein the second transparent conductive film is formed such that an end portion is located on an inner side of an outer edge of a second main surface of the semiconductor substrate, the second transparent conductive film is formed such that the second transparent conductive film does not intersect with the first transparent conductive film along a normal line that extends from the end portion of the second transparent conductive film toward a surface of the semiconductor substrate, and on the second main surface and between an end portion of the first transparent conductive film and the end portion of the second transparent conductive film, either a structure, in which the first intrinsic semiconductor layer, the second-conductivity-type semiconductor layer, the second intrinsic semiconductor layer, and the first-conductivity-type semiconductor layer are laminated in order, or a structure, in which the first intrinsic semiconductor layer, the second-conductivity-type semiconductor layer, and the first-conductivity-type semiconductor layer are laminated in order, is provided.
According to the present invention, a substantially intrinsic semiconductor layer (intrinsic semiconductor layer) and a semiconductor thin film having a conductivity type different from that of the semiconductor substrate are provided on the first main surface, the side surfaces, and the peripheral portion of the second main surface of the semiconductor substrate, a first transparent conductive film is provided over the first main surface and the side surfaces, an intrinsic semiconductor layer and a semiconductor layer having the same conductivity type as that of the semiconductor substrate are provided on the second main surface, and a second transparent conductive film having a smaller area than that of the semiconductor substrate is provided on the semiconductor substrate. On the second main surface, between the end portion of the first transparent conductive film and the end portion of the second transparent conductive film, the intrinsic semiconductor, the semiconductor thin film having a conductivity type different from that of the semiconductor substrate, the intrinsic semiconductor layer, and the semiconductor layer having the same conductivity type as that of the semiconductor substrate are provided in the order that they appear in this sentence, thereby suppressing leakage current between the semiconductor substrate and the first transparent conductive film at the end portion of the semiconductor substrate. Furthermore, in the space between the first and second transparent conductive films and on the end portion, the films are laminated in the same order so as to form a pin junction or a pn junction; therefore, the forward current flows effectively through the junction between the films and the substrate and the reverse current flowing in the surface and the interface of the semiconductor thin film and the end surface of the semiconductor thin film is blocked, whereby the flow of the charge is maintained in a normal state. Consequently, the function of an electrical cell is exhibited by exhibiting the current collecting effect and leakage current is suppressed. With such a configuration, the optically and electrically effective area can be maximized only by controlling the end portion of each layer and leakage current can be prevented not only between the first and second transparent conductive films but also between the semiconductor substrate and the first transparent conductive film without requiring the addition of a new film or an additional complex process.
Exemplary embodiments of a photovoltaic element and a manufacturing method thereof according to the present invention will be explained below in detail with reference to the drawings. This invention is not limited to the embodiments and can be modified as appropriate without departing from the scope of the invention. In the drawings illustrated below, for easier understanding, scales of respective layers or respective members may be shown differently from what they are in reality. This also holds true for the relationships between the drawings.
In the photovoltaic element in the first embodiment, a second-conductivity-type semiconductor layer is formed such that it covers the entire first main surface of the semiconductor substrate and covers a predetermined width of the peripheral portion of the second main surface of the semiconductor substrate by wrapping around the side surfaces of the semiconductor substrate, with a first intrinsic semiconductor layer therebetween. A first-conductivity-type semiconductor layer is formed over the second main surface of the semiconductor substrate with a second intrinsic semiconductor layer therebetween. The photovoltaic element in the first embodiment further includes a first transparent conductive film, which is formed such that it is in contact with the second-conductivity-type semiconductor layer and extends to the side surfaces from the first main surface, and a second transparent conductive film, which is provided such that it is in contact with the first-conductivity-type semiconductor layer. Furthermore, the second transparent conductive film is formed such that its end portion is located on the inner side of the outer edge of the second main surface of the semiconductor substrate and it does not intersect with the first transparent conductive film along the normal line that extends from the end portion of the second transparent conductive film toward the surface of the semiconductor substrate. Moreover, on the second main surface, the photovoltaic element in the first embodiment includes a structure in which the first intrinsic semiconductor layer, the second-conductivity-type semiconductor layer, the second intrinsic semiconductor layer, and the first-conductivity-type semiconductor layer are laminated, in the order that they appear in this sentence, between the end portion of the first transparent conductive film and the end portion of the second transparent conductive film. In other words, even in the end portion of the second main surface of the semiconductor substrate, the films are laminated in the same order so as to form a pin junction; therefore, the forward current flows effectively through the junction between the films and the substrate and the reverse current flowing in the surface and the interface of the semiconductor thin film and the end surface of the semiconductor thin film can be blocked, whereby the flow of the charge is maintained in a normal state. Consequently, leakage current is suppressed and the function of an electrical cell is exhibited by exhibiting the current collecting effect.
The second transparent conductive film is formed such that its outer edge is located on the inner side of the outer edge of the second main surface of the semiconductor substrate by a predetermined distance and is formed such that it does not intersect with the first transparent conductive film along the normal line that extends from the outer edge of the second transparent conductive film toward the surface of the semiconductor substrate. In a similar manner, the structure in which the first intrinsic semiconductor layer, the second-conductivity-type semiconductor layer, the second intrinsic semiconductor layer, the first-conductivity-type semiconductor layer are laminated, in the order that they appear in this sentence, is also formed such that it extends to the inner side of the outer edge of the second main surface by a predetermined distance.
In this example, an n-type single-crystal silicon substrate (hereinafter, referred to as an n-type silicon substrate in some cases) 1, which includes a first main surface 1A, side surfaces 1C, and a second main surface 1B and has a thickness between 100 μm and 500 μm, is used as the first-conductivity-type semiconductor substrate. A first amorphous silicon i layer 2 is used as the first intrinsic semiconductor layer and a second amorphous silicon i layer 3 is used as the second intrinsic semiconductor layer. An amorphous silicon p layer 4 is used as the second-conductivity-type semiconductor layer and an amorphous silicon n layer 5 is used as the first-conductivity-type semiconductor layer. A first ITO (Indium Tin Oxide) layer 6 is used as the first transparent conductive film and a second ITO (Indium Tin Oxide) layer 7 is used as the second transparent conductive film. A metal electrode 8 is used for current collection.
Specifically, in the photovoltaic element in the first embodiment, as illustrated in
The first ITO layer 6 extends up to substantially the outer edge of the n-type silicon substrate 1 and does not intersect with the first ITO layer 6 along the normal line S0, which extends from the first ITO layer 6 toward the surface of the n-type silicon substrate 1. The end portion Se of the first ITO layer 6 matches the outer edge of the n-type silicon substrate 1 and the outer edge of the second ITO layer 7 is formed such that it is located on the inner side of the outer edge of the n-type silicon substrate 1 by a predetermined distance X. The second ITO layer 7 is formed such that it does not intersect with the first ITO layer 6 along the normal line S0, which extends from the outer edge of the second ITO layer 7 toward the surface of the n-type silicon substrate 1.
The amorphous silicon n layer 5, which has the same conductivity type as that of the n-type silicon substrate 1, is formed over the amorphous silicon p layer 4, which has a conductivity type different from that of the n-type silicon substrate 1.
Next, the manufacturing method of the photovoltaic element in the first embodiment will be explained in accordance with the flowchart of
After the n-type silicon substrate 1 is cleaned and the damaged layer of the n-type silicon substrate 1 is etched, a gettering process is performed to remove impurities in the n-type silicon substrate 1 (S1002). In the gettering process, impurities are segregated in a phosphorus glass layer that is formed by thermally diffusing phosphorus at a processing temperature of approximately 1000° C. and the phosphorus glass layer is then etched by using hydrogen fluoride or the like.
After the gettering process, a texture is formed on the substrate surface by performing wet etching using an alkaline solution and an additive in order to reduce the light reflection loss on the substrate surface (S1003). Potassium hydroxide, sodium hydroxide, or the like is used as the alkaline solution and isopropyl alcohol or the like is used as the additive. From
After the texture is formed, the n-type single-crystal silicon substrate 1 is cleaned so as to remove particles on the surface thereof, which is to be a heterojunction interface, and to eliminate organic contamination and metal contamination (S1004). For cleaning, for example, cleaning known as RCA cleaning, SPM cleaning (sulfuric acid-hydrogen peroxide mixture cleaning), HPM cleaning (hydrochloric acid-hydrogen peroxide mixture cleaning), DHF cleaning (dilute hydrofluoric acid cleaning), and alcohol cleaning are used.
The RCA cleaning is a method as follows: First, a wafer is immersed into a dilute hydrofluoric acid solution (HF) to elute a thin silicon oxide film on the surface. At this point, at the same time as the elution of the silicon oxide film, a lot of foreign matter adhered to the silicon oxide film is also removed. Furthermore, organic materials and particles are removed by using ammonia (NH4OH)+hydrogen peroxide (H2O2). Next, metals are removed by using hydrochloric acid (HCl)+hydrogen peroxide (H2O2). Finally, finishing is performed by using ultra-pure water.
After the substrate is cleaned by using any of the above cleaning methods, semiconductor layers of respective conductivity types are formed in order on the n-type silicon substrate 1 so as to form a heterojunction and pn and nn+ junctions. The n-type silicon substrate 1 obtained after being subjected to the texture forming process and the cleaning process has a thickness between 100 μm and 500 μm.
First, as illustrated in
At this point, in order to deposit predetermined amorphous silicon layers not only on the first main surface 1A and the side surfaces 1C but also on the peripheral portion of the second main surface 1B, a plasma CVD device having a structure as illustrated in
A plasma CVD device 100 used in this example includes a processing chamber 101 as illustrated in the schematic diagrams in
In the plasma CVD device 100, which is a semiconductor depositing device, after a vacuum is drawn in the processing chamber 101 by a vacuum pump through the discharge port 105, the n-type silicon substrate 1, which is a processing target substrate, is arranged on the support 102, which serves also as an anode electrode, by using a carrying mechanism (not illustrated). At this point, the first main surface 1A out of the two main surfaces (the first main surface 1A, which is a front surface, and the second main surface 1B, which is a back surface) of the n-type silicon substrate 1 supported by the support 102 faces the cathode electrode 103 side. Then, a process gas is supplied from the gas supply source (not illustrated) to the space between the support 102, which is used also as an anode electrode, and the cathode electrode 103 through the openings (not illustrated), which are formed in the cathode electrode 103 such that they resemble a shower head, via a mass flow controller (not illustrated) as a process-gas control system and the gas supply portion 104. A high-frequency power (high-frequency bias) supplied from the high-frequency power supply 106 is applied to the cathode electrode 103 and plasma of the process gas is generated in the space between the cathode electrode 103 and the support 102, which is used also as an anode electrode. The chemically active species generated in the plasma serve as a deposition precursor and react on the first main surface 1A of the n-type silicon substrate 1, thereby forming a desired film. At this point, on the n-type silicon substrate 1 that is placed on the support 102 that has a flat convex portion having a smaller area than that of the second main surface 1B, the deposition precursor flows from the first main surface 1A to the peripheral portion of the second main surface 1B around the side surfaces 1C to deposit the first amorphous silicon i layer 2 and the amorphous silicon p layer 4 in the order that they appear in this sentence.
Next, as illustrated in
Next, as illustrated in
Thereafter, a transparent conductive film (the second ITO layer 7) is formed over the second main surface 1B by using a mask such that it has a smaller area than that of the substrate (S1010: second transparent conductive film formation). Finally, the metal electrode 8 is formed over the first main surface 1A and the second main surface 1B (S1011: electrode formation).
As described above, according to the photovoltaic element in the present embodiment, the effective area can be maximized while preventing leakage current; whereby the characteristics can be improved. The leakage current flowing between the ITOs through each amorphous layer can be suppressed by controlling the distance between the first ITO layer 6 and the second ITO layer 7. Furthermore, the structure in which the first amorphous silicon i layer 2, the amorphous silicon p layer 4, the second amorphous silicon i layer 3, and the amorphous silicon n layer 5 are laminated, in the order that they appear in this sentence, is provided between the first ITO layer 6 and the second ITO layer 7; therefore, the leakage current flowing between the first ITO layer 6 and the n-type silicon substrate 1 through each amorphous layer can be suppressed. In addition to this, on the end portion of the second main surface 1B of the n-type silicon substrate 1, the order of the films is maintained to form a pin junction; therefore, the flow of the charge is maintained in a normal state, thereby exhibiting the function of an electrical cell. Consequently, even on the end portion, although the second ITO layer 7 is withdrawn by the distance X from the end portion of the n-type silicon substrate 1, charge flows between the second ITO layer 7 and the first ITO layer 6; therefore, the current collecting effect is exhibited and this region serves as an electrical cell area. Moreover, the optically and electrically effective area can be maximized only by controlling the end portion of each layer and leakage current can be prevented not only between the first and second ITO layers 6 and 7 but also between the n-type silicon substrate 1 and the first ITO layer 6 without requiring the addition of a new film or an additional new complex process. In contrast, when a contact prevention layer is provided as in Patent Literature 3, the contact prevention layer is required to keep the thickness in order to exhibit its function, which causes a reduction in the effective electrical cell area. Moreover, a reduction in the open circuit voltage due to wrap-around is inevitable.
In
As is understood from the comparison between the curve “a” and the curve “b” in
From the above results, in the present embodiment, on the peripheral portion of the second main surface 1B, the distance in the plane direction between the end portion of the first transparent conductive film and the end portion of the second transparent conductive film is set to be equal to or more than 0.1 mm and equal to or less than 3 mm. Furthermore, on the second main surface 1B, the length in the plane direction of the structure in which the first amorphous silicon i layer 2, the amorphous silicon p layer 4, the second amorphous silicon i layer 3, and the amorphous silicon n layer 5 are laminated, in the order that they appear in this sentence, is set to be equal to or more than 0.1 mm and equal to or less than 3 mm between the first and second ITO layers 6 and 7. Consequently, leakage current is not generated and thus high efficiency can be achieved.
On the peripheral portion of the second main surface 1B, the distance in the plane direction between the end portion of the first transparent conductive film and the end portion of the second transparent conductive film is preferably set to be equal to or more than 0.25 mm and equal to or less than 2.5 mm, and more preferably set to be equal to or more than 0.5 mm and equal to or less than 2.0 mm. Moreover, on the second main surface 1B, the length in the plane direction of the structure in which the first amorphous silicon i layer 2, the amorphous silicon p layer 4, the second amorphous silicon i layer 3, and the amorphous silicon n layer 5 are laminated, in the order that they appear in this sentence, is preferably set to be equal to or more than 0.25 mm and equal to or more than 2.5 mm, and more preferably set to be equal to or more than 0.5 mm and equal to or less than 2.0 mm between the first and second ITOs. With such a structure, further highly efficient characteristics can be obtained.
Moreover, the film thickness of each of the first amorphous silicon i layer 2 and the amorphous silicon p layer 4 that are formed to wrap around onto the peripheral portion of the second main surface 1B becomes in some cases smaller than that when they are formed on the first main surface 1A depending on the deposition conditions; however, when the film thickness of each of the layers formed to wrap around onto the peripheral portion of the second main surface 1B is equal to or more than 50% of the film thickness of each of the layers formed on the first main surface 1A, and the laminated structure of the second amorphous silicon i layer 3 and the amorphous silicon n layer 5 that are arranged over the first amorphous silicon i layer 2 and the amorphous silicon p layer 4 is within a range equal to or more than 0.1 mm and equal to or less than 3 mm from the peripheral portion of the n-type silicon substrate 1, both the leakage current reduction effect and the current collecting effect can be achieved and thus excellent characteristics can be obtained. The film thickness of each of the first amorphous silicon i layer 2 and the amorphous silicon p layer 4 that are formed to wrap around onto the peripheral portion of the second main surface 1B is preferably equal to or more than 80% of the film thickness of each of the layers formed on the first main surface 1A, and the length of the laminated structure is preferably equal to or more than 0.25 mm and equal to or less than 2.5 mm, and more preferably equal to or more than 0.5 mm and equal to or less than 2.0 mm. With such a configuration, leakage current is sufficiently suppressed so that the characteristics are not affected and thus higher output characteristics can be obtained. The film thickness of each of the first amorphous silicon i layer 2 and the amorphous silicon p layer 4 that are formed to wrap around onto the peripheral portion of the second main surface 1B is set to be equal to or more than 50% of the film thickness of each of the layers formed on the first main surface 1A. This is because when the film thickness of each of the layers formed to wrap around onto the peripheral portion of the second main surface 1B is approximately 50% of the film thickness of each of the layers on the first main surface 1A, each layer can substantially exhibit its function. When the film thickness of each of the layers formed to wrap around onto the peripheral portion of the second main surface 1B is equal to or more than approximately 80% of the film thickness of each of the layers on the first main surface 1A, each layer can exhibit its function substantially perfectly.
In the present embodiment, the first amorphous silicon i layer 2, the amorphous silicon p layer 4 having a conductivity type different from that of the n-type silicon substrate 1, the second amorphous silicon i layer 3, and the amorphous silicon n layer 5 having the same conductivity type as that of the n-type silicon substrate 1 are formed; however, the first and second amorphous silicon i layers 2 and 3 may be formed first. In such a case, between the first and second ITO layers 6 and 7, a structure is formed in which the first amorphous silicon i layer 2, the amorphous silicon p layer 4, and the amorphous silicon n layer 5 are laminated in the order that they appear in this sentence. Even with such a configuration, the leakage current flowing between the first ITO layer 6 and the n-type silicon substrate 1 through each amorphous layer can be suppressed.
However, when the amorphous silicon n layer 5 is formed before the amorphous silicon p layer 4 and the amorphous silicon n layer 5 is inserted between the amorphous silicon p layer 4 and the n-type silicon substrate, the configuration becomes such that the p-type amorphous silicon, the n-type amorphous silicon, and the n-type crystalline silicon are formed from above in the order that they appear in this sentence (the intrinsic amorphous silicon layer is ignored) and excellent characteristics cannot be obtained. The reason why excellent characteristics cannot be obtained is that, because a junction having poor characteristics is formed at the pn junction, carriers cannot be efficiently collected.
From the above point, higher characteristics can be obtained by forming the p-type amorphous silicon layer before the n-type semiconductor layer to have a configuration in which the n-type amorphous silicon, the p-type amorphous silicon, and the n-type crystalline silicon are laminated as in the process of the present embodiment. This is because it is desirable to form a pn junction between a substrate and an amorphous silicon layer with respect to the characteristics.
Moreover, in the end portion of the amorphous silicon p layer 4 formed on the second main surface 1B, the thickness is non-uniform; therefore, the diode characteristics easily deteriorate and leakage easily occurs. Therefore, by having a laminated structure of the second amorphous silicon i layer 3, which is in contact with the second main surface 1B of the n-type silicon substrate 1, and the amorphous silicon n layer 5 between the second ITO layer 7 and the laminated structure of the first amorphous silicon i layer 2, the amorphous silicon p layer 4, the second amorphous silicon i layer 3, and the amorphous silicon n layer 5 on the peripheral portion of the second main surface 1B within the design range described above, it is possible to avoid electrical contact with a degraded diode. Consequently, higher characteristics can be obtained.
When the value of the resistivity of the n-type single-crystal silicon substrate 1 is approximately equal to or less than 4 Ωcm, a similar result is obtained. If the resistivity of the n-type single-crystal silicon substrate 1 exceeds 4 Ωcm, the output is reduced because of an increase in the series resistance.
As illustrated in the flowchart in
In the present embodiment, the transparent conductive films (the first and second ITO layers 6 and 7) can be formed after the amorphous silicon n layer 5 is formed. Therefore, metal contamination of the n-type silicon substrate 1 can be reduced compared to the case where the second amorphous silicon i layer 3 is formed after the first ITO layer 6, which is a transparent conductive film on the first main surface 1A side, is formed. Consequently, the characteristics can be improved.
As illustrated in the flowchart in
In the present embodiment, in a similar manner to the second embodiment, the transparent conductive films (the first and second ITO layers 6 and 7) can be formed after the amorphous silicon n layer 5 is formed. Therefore, metal contamination of the n-type silicon substrate 1 can be reduced compared to the case where the second amorphous silicon i layer 3 is formed after the first ITO layer 6, which is a transparent conductive film on the first main surface 1A side, is formed. Consequently, the characteristics can be improved. Moreover, in this case, the second amorphous silicon i layer 3 and the amorphous silicon n layer 5 are formed not only over the second main surface 1B but also over the side surfaces 10 and the peripheral portion of the first main surface 1A. In other words, the entire surface of the n-type silicon substrate 1 is covered with the semiconductor layers before the transparent conductive films (the first and second ITO layers 6 and 7) are formed; therefore, degradation of the characteristics due to metal contamination of the n-type silicon substrate 1 does not occur and it is not necessary to perform mask alignment to form the amorphous silicon n layer 5. Consequently, the characteristics are excellent and productivity is excellent.
The amorphous silicon n layer 5 and the first ITO layer 6 are in contact with each other in the side-surface direction; however, as illustrated in
As illustrated in the flowchart in
In the present embodiment, because the intrinsic amorphous silicon layers are formed over the entire surface of the n-type silicon substrate 1 before the transparent conductive films are formed, there is no problem of metal contamination. Moreover, when the amorphous silicon n layer 5 is formed, a mask is not needed; therefore, contamination due to, for example, attachment and detachment of a mask does not occur. Consequently, the characteristics are excellent and productivity is excellent.
In the present embodiment, in a similar manner to the third embodiment, the amorphous silicon n layer 5 and the first ITO layer 6 are in contact with each other in the side-surface direction; however, as illustrated in
Alternatively, as illustrated in the flowchart in
In the present embodiment, because the intrinsic amorphous silicon is formed over the entire surface of the n-type silicon substrate 1 before the transparent conductive films are formed, there is no problem of metal contamination. Moreover, on the peripheral portion of the second main surface 1B, a region is formed in which the first amorphous silicon i layer 2 and the second amorphous silicon i layer 3 overlap with each other; therefore, a substantially thick intrinsic amorphous silicon layer can be formed. At this point, if the length of the region of the substantially thick intrinsic amorphous silicon layer in a direction toward the center of the semiconductor substrate is equal to or more than 0.05 mm, it is possible to suppress leakage current flowing between the first ITO layer 6 and the n-type silicon substrate 1 through each amorphous layer. If the length of the region of the substantially thick intrinsic amorphous silicon layer in a direction toward the center of the semiconductor substrate is less than 0.05 mm, it is difficult to suppress leakage current by the intrinsic amorphous silicon layer structure formed to have a substantially large thickness. On the other hand, because the length of the region of the laminated structure of the amorphous silicon p layer 4 and the amorphous silicon n layer 5 in a direction toward the center of the semiconductor substrate needs to be at least 0.1 mm, if the length exceeds 2.9 mm, the electric field applied to the metal electrode 8 cannot be sufficiently applied to the junction formed between the amorphous silicon p layer 4 and the amorphous silicon n layer 5 and thus it becomes difficult to maintain the current collecting effect. Therefore, when the length of the region of the intrinsic amorphous silicon layer in a direction toward the center of the semiconductor substrate is in a range equal to or more than 0.05 mm and equal to or less than 2.9 mm, leakage current can be suppressed and the current collecting effect can be maintained; therefore, the characteristics are excellent.
The length of the region of the substantially thick intrinsic amorphous silicon layer in a direction toward the center of the semiconductor substrate is preferably in a range equal to or more than 0.1 mm and equal to or less than 2.4 mm, and more preferably in a range equal to or more than 0.1 mm and equal to or less than 1.9 mm. Within such ranges, leakage current can be further suppressed and the current collecting efficiency is increased; therefore, high characteristics can be obtained.
In the present embodiment, in a similar manner to the third embodiment, the amorphous silicon n layer 5 and the first ITO layer 6 are in contact with each other in the side-surface direction; however, as illustrated in
In the plasma CVD device used in the first to fifth embodiments, a support is used that has a convex portion having a smaller area than that of the semiconductor substrate. The first main surface or the second main surface of the semiconductor substrate is brought into contact with the convex portion and films are formed such that they cover the entire first or second main surface and extend to a predetermined width of the peripheral portion of the second or first main surface by wrapping around the side surfaces. When each film is formed, it is possible to adjust the wrap-around distance with high accuracy by adjusting the size of the convex portion. It is desirable that the wrap-around distance is uniform. However, the structure may be deviated. For example, the semiconductor layers located between the end portions of the first and second transparent conductive films may be configured such that only a part thereof has a pipn structure and other parts have a pin structure.
Moreover, the transparent conductive films are not limited to ITOs and can be appropriately changed to tin oxide, zinc oxide, or the like.
As the semiconductor substrate, other than a crystalline silicon substrate, such as a single-crystal silicon substrate and a polycrystalline silicon substrate, for example, a crystalline silicon-based substrate, examples of which include a silicon compound substrate, such as a silicon carbide substrate, can also be used. As the intrinsic amorphous silicon thin film or the amorphous silicon thin film having each conductivity type, a crystalline thin film, such as a microcrystalline silicon-based thin film and a polycrystalline silicon-based thin film, can also be used.
As described above, the photovoltaic element and the manufacturing method thereof according to the present invention can shorten the manufacturing time because a complex additional process is not necessary and can maximize the effective area of the substrate while preventing leakage current, and are thus useful for improving the conversion efficiency. In particular, the photovoltaic element and the manufacturing method thereof according to the present invention are suitable for photovoltaic power generation.
1 n-type silicon substrate, 2 first amorphous silicon i layer, 3 second amorphous silicon i layer, 4 amorphous silicon p layer, 5 amorphous silicon n layer, 6 first ITO layer, 7 second ITO layer, 8 metal electrode, 100 plasma CVD device, 101 processing chamber, 102, 102S support (anode electrode), 103 cathode electrode, 104 gas supply portion, 105 discharge portion, 106 high-frequency (RF) power supply, Se end portion, S0 normal line S0 extending from the end portion of the second ITO layer 7 toward the surface of the n-type silicon substrate 1.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2012-189220 | Aug 2012 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2013/072899 | 8/27/2013 | WO | 00 |
