Patent Application
20070097018
This application claims priority to prior applications JP 2005-245583 and JP 2006215361, the disclosures of which are incorporated herein by reference.
This invention relates to a flat panel display unit and to picture displaying by the use thereof, in particular, to picture displaying by means of a plurality of flat panel display units.
For displaying different pictures with a plurality of liquid crystal display units, it is necessary to provide the same number of signal sources as the liquid crystal display units. For instance, the same number of graphic boards, each of which has a picture signal output, as the liquid crystal display units is used as the signal sources. Alternatively, a graphic board having the same number of picture signal outputs as the liquid crystal display units is used as the signal sources.
Moreover, there is a liquid crystal display unit that a liquid crystal display panel thereof can display two different pictures at a time by dividing a screen. The liquid crystal display unit has also two image signal sources. Such a display unit is disclosed in Japanese Patent Unexamined Publication No. 9-62230.
On the other hand, it is known that a liquid crystal display unit has two pairs of drivers to drive a liquid crystal panel and to display a picture. The liquid crystal display unit simultaneously scans two areas of the liquid crystal panel. Therefore, the liquid crystal display unit needs two signal sources. Such a display unit is disclosed in Japanese Patent Unexamined Publication No. 5-80714.
At any rate, the liquid crystal display unit needs the same number of signal sources as pictures which would be displayed. That is, it is currently impossible that one of two liquid crystal display units displays an upper/left half of a picture according to a picture signal while the other displays a lower/right half of the picture according to the same picture signal. Furthermore, it is currently impossible that one of two liquid crystal display units displays a picture according to a picture signal while the other displays another picture according to the same picture signal. This is true of the liquid crystal display unit which has liquid crystal display panel divided into two areas.
It is therefore an object of this invention to provide a method that a plurality of picture displaying units, each of which displays a part of a picture, displays the whole of the picture according to a single picture signal without the same number of signal sources, such as graphic boards, as the picture displaying units.
Other objects of this invention will become clear as the description proceeds.
According to a first aspect of this invention, a picture displaying method is for displaying a picture by means of a plurality of picture displaying units each of which has a displaying panel driven with primary and secondary driving signals produced according to an input picture signal. The picture displaying method comprises the steps of supplying the input picture signal to each of the picture displaying units; starting, in a first displaying unit which is one of the picture displaying units, producing first primary and first secondary driving signals according to the input picture signal; starting, in a second displaying unit which is another one of the picture displaying units, producing one of second primary and second secondary driving signals according to the input picture signal; driving a first displaying panel of the first displaying unit with the first primary and the first secondary driving signals to display a first part of the picture represented by the input picture signal; sending a start pulse signal produced by the first displaying unit to the second displaying unit after displaying the first part of the picture; starting, in the second displaying unit, producing the other of the second primary and the second secondary driving signals in response to the start pulse signal; and driving a second displaying panel of the second displaying unit with the second primary and the second secondary driving signals to display a second part, which is different from the first part, of the picture represented by the input picture signal.
According to a second aspect of this invention, a picture displaying system comprises a plurality of picture displaying units each of which has a displaying panel driven with primary and secondary driving signals produced according to an input picture signal. The input picture signal is supplied to each of the picture displaying units. A first picture displaying unit which is one of the picture displaying units starts producing first primary and first secondary driving signals according to the input picture signal, drives a first displaying panel thereof with the first primary and the first secondary driving signals to display a first part of a picture represented by the input picture signal, and then sends a start pulse signal to a second picture displaying unit which is another one of the picture displaying units. The second picture displaying unit starts producing one of second primary and second secondary driving signals according to the input picture signal, and starts producing the other of the second primary and the second secondary driving signals according to the picture signal in response to the start pulse signal, and drives a second displaying panel thereof with the second primary and the second secondary driving signals to display a second part, which is different from the first part, of the picture represented by the input picture signal.
According to a third aspect of this invention, a picture displaying unit comprises a start pulse signal producing circuit for producing start pulse signals to start producing first primary and first secondary driving signals according to an input picture signal. Primary and secondary driver circuits are for producing the first primary and the first secondary driving signals in response to the start pulse signals. A displaying panel is for being driven with the first primary and the first secondary driving signals. The primary driver circuit sends an additional start pulse signal to another picture displaying unit which receives the input picture signal to start producing one of second primary and second secondary driving signals after producing the first primary driving signal. The displaying panel displays a part of a picture represented by the input picture signal.
According to a fourth aspect of this invention, a picture displaying unit comprises a start pulse signal producing circuit for producing an internal start pulse signal to start producing primary driving signals according to an input picture signal. A primary driver circuit is for producing the primary driving signal in response to the internal start pulse signal. A secondary driver circuit is for receiving an external start pulse signal from the outside to produce the secondary driving signal. A displaying panel is driven with the primary and the secondary driving signals for displaying a part of a picture represented by the input picture signal.
According to a fifth aspect of this invention, a picture displaying unit comprises a start pulse signal producing circuit for producing an internal start pulse signal to start producing a primary driving signal according to an input picture signal. A primary driver circuit is for producing the primary driving signal in response to the internal start pulse signal. A secondary driver circuit is for receiving an external start pulse signal from a preceding picture displaying unit to produce a secondary driving signal. The secondary driver circuit produces another external start pulse signal to be supplied to a following picture displaying unit. A displaying panel is driven with the primary and the secondary driving signals to display a part of a picture represented by the input picture signal.
According to a sixth aspect of this invention, a picture displaying method is for displaying a picture represented by a picture signal by means of a plurality of picture displaying units. The picture displaying method comprises the steps of: supplying the input picture signal to each of the picture displaying units; displaying a first part of the picture according to the picture signal by means of a first picture displaying unit which is one of the picture displaying units; sending a start signal from the first picture displaying unit to a second picture displaying unit which is another one of the picture displaying units after displaying of the first part of the picture; and displaying a second part different from the first part of the picture according to the picture signal in response to the start signal by means of the second picture displaying unit.
According to a seventh aspect of this invention, a picture displaying system is for displaying a picture represented by a picture signal. The system comprises a first picture displaying unit for receiving the picture signal to display a first part of the picture and to produce a start signal after displaying the first part of the picture. A second picture displaying unit is for receiving both of the picture signal and the start signal to display a second part different form the first part of the picture.
Referring to
The picture displaying system 100 includes first and second liquid crystal display units 1 and 2 and a signal source 3.
The first and the second liquid crystal display units 1 and 2 display different pictures according to a common picture signal S1 supplied from the signal source 3.
The signal source 3 produces the picture signal S1. The signal source 3, for example, is a video card for a computer. The picture signal S1, for example, includes color signals RGB, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync and a dot clock signal CLK. The picture signal S1 includes a picture frame which represents a picture having 2n (n: a natural number) of scanning lines each of which corresponds to m (m: a natural number) of pixels. Alternatively, the picture frame represents two successive pictures each of which has n of scanning lines. A conventional liquid crystal display unit needs a liquid crystal display panel with at least 2n of gate lines to display the picture having 2n of the scanning lines.
The first liquid crystal display unit 1 includes a first control circuit 11, a first source driver 12, a first gate driver 13 and a first panel 14. The first panel 14 is a TFT (or active matrix type) liquid crystal panel having m (m: a natural number) of source lines and n of gate lines (G1, G2, . . . , Gn). The first source driver 12 has a first writing shift register 12r having the same number (=m) of stages (e.g. flip-flops) as the source lines of the first panel 14. The first gate driver 13 has a first scanning shift register 13r having the same number (=n) of stages (e.g. flip-flops) as the gate lines of the first panel 14.
Similarly, the second liquid crystal display unit 2 includes a second control circuit 16, a second source driver 17, a second gate driver 15 and a second panel 18. The second panel 18 similar to the first panel 14. That is, the second panel 18 is a TFT (or active matrix type) liquid crystal panel having m (m: a natural number) of source lines and n (n: a natural number) of gate lines (Gn+1, Gn+2, . . . , Gn+n). The second source driver 17 has a second writing shift register 17r having the same number (=m) of stages as the source lines of the second panel 18. The second gate driver 15 has a second scanning shift register 15r having the same number (=n) of stages as the gate lines of the second panel 18.
The first liquid crystal display unit 1 operates as follows.
On receiving the picture signal S1 from the signal source 3, the first control circuit 11 passes the color signals RGB included in the picture signal S1 to the first source driver 12 as a first color signal RGB1. Furthermore, the first control circuit 11 produces a first writing start pulse signal S2, a first writing shift clock signal S3, a first scanning start pulse signal S4 and a first scanning shift clock signal S5. These signals s2-S5 are produced by using the horizontal synchronization signal Hsync, the vertical synchronization signal Vsync and/or the dot clock signal CLK. The first writing start pulse signal S2 and the first writing shift clock signal 83 are supplied to the first source driver 12 while the first scanning start pulse signal S4 and the first scanning shift clock signal 85 are supplied to the first gate driver 13.
In the first source driver 12, the first writing start pulse signal S2 from the first control circuit 11 is supplied to the first writing shift register 12r. The first writing shift register 12r shifts and outputs the first writing start pulse signal S2 in response to the first writing shift clock signal S3. One of the source lines of the first panel 14 is specified according to the stage of the first writing shift register 12r that outputs the first writing start pulse signal S2. The first source driver 12 performs sampling of the color signal RGB1 in response to the output of the first writing shift register 12r. Subsequently the first source driver 12 performs D-A conversion of the sampled color signal to produce a first source driving signal S6. The first source driving signal S6 is supplied from the first source driver 12 to the specified source line of the first panel 14. Thus, the source lines of the first panel 14 are driven by the first source driving signal S6 in order. Thus, the source lines of the first panel are driven by the first source driving signal one by one.
On the other hand, in the first gate driver 13, the first scanning start pulse signal S4 from the first control circuit 11 is supplied to the first scanning shift register 13r. The first scanning shift register 13r shifts and outputs the first scanning start pulse signal S4 in response to the first scanning shift clock signal S5. One of the gate lines G1-Gn of the first panel 14 is specified according to the stage of the first scanning shift register 13r that outputs the first scanning start pulse signal S4. The first gate driver 13 converts the output of the shift register 13r into an ON voltage of a TFT level and supplies it to the specified gate line of the first panel 14 as a first gate driving signal S7. As a result, the gate lines G1-Gn are supplied with the ON voltage one by one according to the first scanning shift clock signal S4.
The first gate driver 13 further supplies a second scanning start pulse signal 88 to the second gate driver 15, after the ON voltage is supplied to the nth gate line of the first panel 14.
The first panel 14 receives the first source driving signal S6 from the first source driver 12 and the first gate driving signal S7 from the first gate driver 13. The first panel 14 selects the gate lines one by one according to the first gate driving signal S7. While each gate line is selected, the first panel 14 writes the first source driving signal S6 to the source lines thereof in turn.
The second control circuit 16 receives the picture signal S1 from the signal source 3 and passes the color signals RGB included in the picture signal S1 to the second source driver 17 as a second color signal RGB2. Furthermore, the second control circuit 16 produces a second writing start pulse signal 89, a second writing shift clock signal S10 and a second scanning shift clock signal S11 according to the picture signal S1. The second writing start pulse signal S9 and the second writing shift clock signal S10 are supplied to the second source driver 17 while the second scanning shift clock signal S1 is supplied to the second gate driver 15. The second control circuit 16 does not supply a start pulse signal to the second gate driver 15 differently from the first control circuit 11. The second color signal RGB2, the second writing start pulse signal S9, the second writing shift clock signal S10 and the second scanning shift clock signal S11 are identical to the first color signal RGB1, the first writing start pulse signal S2, the first writing shift clock signal S3 and the first scanning shift clock signal S5, respectively.
In the second source driver 17, the second writing start pulse signal S9 from the second control circuit 16 is supplied to the second writing shift register 17r. The second writing shift register 17r shifts and outputs the second writing start pulse signal S9 in response to the second writing shift clock signal S10. One of the source lines of the second panel 18 is specified according to the stage of the second writing shift register 17r that outputs the second writing start pulse signal S9. The second source driver 17 performs sampling of the second color signal RGB2 in response to the output of the second writing shift register 17r. Subsequently the second source driver 17 performs D-A conversion of the sampled color signal to produce a second source driving signal S12. The second source driving signal S12 is supplied from the second source driver 17 to the specified source line of the second panel 18. The second source driving signal 812 is identical to the first source driving signal S6.
On the other hand, in the second gate driver 15, the second scanning start pulse signal S8 from the first gate driver 13 is supplied to the second scanning shift register 15r. The second scanning shift register 15r shifts and outputs the second scanning start pulse signal S8 in response to the second scanning shift clock signal S11. One of the gate lines Gn+1-Gn+n of the second panel 18 is specified according to the stage of the second scanning shift register 15r that outputs the second scanning start pulse signal S9. The second gate driver 15 converts the output of the second scanning shift register 15r into ON voltage of the TFT level and supplies it to the specified gate line of the second panel 18 as a second gate driving signal S13. As a result, the gate lines Gn+1-Gn+n are supplied with the ON voltage one by one according to the second scanning shift clock signal S11 after the second scanning start pulse signal S8 is supplied from the first gate driver 13 to the second gate driver 15.
The second panel 18 receives the second source driving signal 812 from the second source driver 17 and the second gate driving signal S13 from the second gate driver 15. The second panel 18 selects the gate lines one by one according to the second gate driving signal S13. While each gate line is selected, the second panel 18 writes the second source driving signal S12 to the source lines thereof in turn.
As mentioned above, the picture signal S1 has the picture frame having 2n of the scanning lines. A first half, from the first scanning line to the nth scanning line, of the picture frame is displayed by the first panel 14 while a latter half, from the n+1th scanning line to the 2 nth scanning line, of the picture frame is displayed by the second panel 18.
The scanning start pulse signal S4 registered in the first scanning shift register 13r is sifted in response to the first scanning shift clock pulse signal S5, and thereby the first gate driving signal S7 is supplied to the gate lines G1, G2, . . . , Gn of the first panel 14 in turn. At the same time, the first source driving signal S6 is supplied to the first panel 14 in response to the first writing shift clock signal S3. Thus, the first to the nth scanning lines are displayed on the first panel 14.
After production of the first gate driving signal S7 for the nth gate line, the first gate driver 13 produces the second scanning start pulse signal 88 to supply it to the second gate driver 15.
The second scanning start pulse signal S8 is registered in the second scanning shift register 15r and shifted in response to the second scanning shift clock signal S11. As a result, the second gate driving signal 813 is supplied to the gate lines Gn+1, Gn+2, . . . , Gn+n of the second panel 18 in turn. At the same time, the second source driving signal S12 is supplied to the second panel 14 in response to the second writing shift clock signal S10. Thus, the n+1th to the 2 nth scanning lines are displayed on the second panel 18.
As mentioned above, the former n of the scanning lines included in the picture frame of the picture signal S1 are displayed on the first panel 14 while the latter n of the scanning lines are displayed on the second panel 18. Thus, the displaying system can display different pictures (or areas of a picture) without providing the same number of the signal sources such as graphic boards as the picture displaying units.
Referring to
The picture displaying system 200 has liquid crystal displaying units 4 and 5 which are different from the units 1 and 2 of
The first source driver 21 includes a first writing shift register 21 r which has the same number (=m) of stages as the source lines of the first panel 14. The first writing start pulse signal S2 output from the first control circuit 11 is supplied to the first writing shift register 21r. The first writing shift register 21r shifts and outputs the first writing start pulse signal S2 in response to the first writing shift clock signal 83. One of the source lines of the first panel 14 is specified according to the stage of the first writing shift register 21r that outputs the first writing start pulse signal 82. The first source driver 21 performs sampling of the first color signal RGB1 in response to the output of first writing shift register 21r. Subsequently, the first source driver 21 performs D-A conversion of the sampled color signal to produce the first source driving signal S6. The first source driving signal S6 is supplied from the first source driver 21 to the specified source line of the first panel 14.
The first source driver 21 further supplies a second writing start pulse signal S20 to the second source driver 25 after it receives the shift clock signal S3 for the number of the source lines of the first panel 14. That is, the first source driver 21 supplies the second writing start pulse signal S20 to the second source driver 25 when the first source driving signal S6 is supplied to the mth source line of the first panel 14.
The first gate driver 22 is different from the first gate driver 13 of
The second gate driver 23 includes a second scanning shift register 23r having the same number (=n) of stages as the gate lines Gn+1-Gn+n of the second panel 18. The second scanning shift register 23r receives a second scanning start pulse signal S21 and the second scanning shift clock signal S11 from the second control circuit 24. The second scanning shift register 23r shifts the second scanning start pulse signal S21 in response to the second scanning shift clock signal S11. The second gate driver 23 converts the output of the second scanning shift register 23r into the ON voltage of the TFT level. The ON voltage is supplied to the specified gate line as the second gate driving signal S13. The second gate driving signal S13 is identical to the first gate driving signal S7.
The second control circuit 24 receives the picture signal S1 and passes the color signals RGB included in the picture signal S1 to the second source driver 25 as a second color signal RGB2. The second control circuit 24 further produces a second writing shift clock signal S10, the second scanning signal clock signal S11 and the second scanning start pulse signal S21. The second writing shift clock signal S10 is supplied to the second source driver 25, The second scanning start pulse signal S21 and the second scanning shift clock signal S11 are supplied to the second gate driver 23 as mentioned above. It will be noticed that the second control circuit 24 does not produces the second writing start pulse signal S9 differently from that of
The second source driver 25 includes a second writing shift register 25r which has the same number (=m) of stages as the source lines of the second panel 18 like the first writing shift register 21r. The second writing start pulse signal S20 output from the first source driver 21 is supplied to the second writing shift register 25r. The second writing shift register 25r shifts and outputs the second writing start pulse signal S20 in response to the second writing shift clock signal S10 supplied from the second control circuit 24. One of the source lines of the second panel 18 is specified according to the stage of the second writing shift register 25r that outputs the second writing start pulse signal S20. The second source driver 25 performs sampling of the second color signal RGB2 in response to the output of second writing shift register 25r. Subsequently, the second source driver 25 performs D-A conversion of the sampled color signal to produce the second source driving signal S12. The second source driving signal S12 is supplied from the second source driver 25 to the specified source line of the second panel 18.
Thus, the displaying system can display different pictures (or areas of a picture) like that of the first embodiment without providing the same number of the signal sources such as graphic boards as the picture displaying units.
While this invention has thus far been described in conjunction with the preferred embodiments thereof, it will readily be possible for those skilled in the art to put this invention into practice in various other manners.
For example, three or more liquid crystal units may be used in a picture displaying system though each of the systems 100 and 200 has two units 1 and 2 or 4 and 5. Specifically, one or more liquid crystal display unit(s) 6 shown in
The size of each panel of the picture displaying system 300 or 400 depend on the number of the liquid crystal units and the number of pixels of the picture frame. If the number of the liquid crystal units is equal to I (I: an integer equal to or larger than three) and the number of the pixels of the picture frame is equal to m×n (m, n: natural numbers), each panel of the system 300 has n of gate lines and m/l of source lines. On the same assumption, each panel of the system 400 has n/l of gate lines and m of source lines.
In
The second gate driver 30 of
In
The second source driver 40 of
Furthermore, this invention is not limited to the system having the liquid crystal display panels. Other flat panel display may be used as far as raw and column lines are used in each panel.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2005-245583 | Aug 2005 | JP | national |
| 2006-215361 | Aug 2006 | JP | national |
