The present disclosure relates to radio frequency bias potential control systems for processing chambers.
The background description provided here is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Plasma etching is frequently used in semiconductor fabrication. In plasma etching, ions are accelerated by an electric field to etch exposed surfaces on a substrate. The electric field is generated based on RF power signals generated by a radio frequency (RF) generator of a RF power system. The RF power signals generated by the RF generator must be precisely controlled to effectively execute plasma etching.
A RF power system may include a RF generator, a matching network, and a load (e.g., a plasma chamber). The RF generator generates RF power signals, which are received at the matching network. The matching network matches an input impedance of the matching network to a characteristic impedance of a transmission line between the RF generator and the matching network. This impedance matching aids in maximizing an amount of power forwarded to the matching network (“forward power”) and minimizing an amount of power reflected back from the matching network to the RF generator (“reverse power”). Forward power may be maximized and reverse power may be minimized when the input impedance of the matching network matches the characteristic impedance of the transmission line.
In the RF power source or supply field, there are typically two approaches to applying the RF signal to the load. A first, more traditional approach is to apply a continuous wave signal to the load. In a continuous wave mode, the continuous wave signal is typically a sinusoidal wave that is output continuously by the power source to the load. In the continuous wave approach, the RF signal assumes a sinusoidal output, and the amplitude and/or frequency of the sinusoidal wave can be varied in order to vary the output power applied to the load.
A second approach to applying the RF signal to the load involves pulsing the RF signal, rather than applying a continuous wave signal to the load. In a pulse mode of operation, a RF sinusoidal signal is modulated by a modulation signal in order to define an envelope for the modulated sinusoidal signal. In a conventional pulse modulation scheme, the RF sinusoidal signal typically is output at a constant frequency and amplitude. Power delivered to the load is varied by varying the modulation signal, rather than varying the sinusoidal, RF signal.
In a typical RF power supply configuration, output power applied to the load is determined by using sensors that measure the forward and reflected power or the voltage and current of the RF signal applied to the load. Either set of these signals is analyzed in a typical control loop. The analysis typically determines a power value which is used to adjust the output of the RF power supply in order to vary the power applied to the load. In a RF power delivery system, where the load is a plasma chamber, the varying impedance of the load causes a corresponding varying power applied to the load, as applied power is in part a function of the impedance of the load.
In plasma systems, power is typically delivered in one of two configurations. In a first configuration, the power is capacitively coupled to the plasma chamber. Such systems are referred to as capacitively coupled plasma (CCP) systems. In a second configuration, the power is inductively coupled to the plasma chamber. Such systems are typically referred to as inductively coupled plasma (ICP) systems. Plasma delivery systems typically include a bias power and a source power applied to one or a plurality of electrodes. The source power is typically used to generate the plasma and the bias power is typically used to tune the plasma to an energy level relative to a bias RF power level. The bias and the source may share the same electrode or may use separate electrodes, in accordance with various design considerations.
When a RF power delivery system drives a load in the form of a plasma chamber, the electric field generated by the power delivered to the plasma chamber results in ion energy within the chamber. The ion energy is distributed non-uniformly due to particle drift/diffusion effects and the externally applied fields. One characteristic measure of ion energy is the ion energy distribution function (IEDF). The ion energy distribution function (IEDF) at the substrate surface can be controlled with a RF waveform. One way of controlling the IEDF for a system in which multiple RF power signals are applied to the load occurs by varying multiple RF signals that are related by frequency and phase. The frequencies between the multiple RF power signals are locked, and the relative phase between the multiple RF signals is also locked. Examples of such systems can be found with reference to U.S. Pat. No. 7,602,127, U.S. Pat. No. 8,110,991, and U.S. Pat. No. 8,395,322, assigned to the assignee of the present invention and incorporated by reference in this application.
RF plasma processing systems include components for plasma generation and control. One such component is referred to as a plasma chamber or reactor. A typical plasma chamber or reactor utilized in RF plasma processing systems, such as by way of example, for thin-film manufacturing, utilizes a dual frequency system. One frequency (the source) of the dual frequency system controls the generation of the plasma, and the other frequency (the bias) of the dual frequency system controls ion energy. Examples of dual frequency systems include systems that are described in U.S. Pat. No. 7,602,127; U.S. Pat. No. 8,110,991; and U.S. Pat. No. 8,395,322 referenced above. The dual frequency systems described in the above-referenced patents include a closed-loop control system to adapt RF power supply operation for the purpose of controlling ion density and its corresponding IEDF.
Multiple approaches exist for controlling a plasma bias potential and thus the corresponding IEDF. The approaches include: conventional low-frequency sine wave biasing; multiple sine wave biasing without harmonic locking; harmonically locked multiple sine wave biasing; and shaped biasing to create a monotonic or custom IEDF. Each of these approaches has associated disadvantages and/or limitations. For example, the low-frequency sine wave biasing approach exhibits a bimodal IEDF (i.e. primarily two non-zero ion energy levels or absolute voltage potentials over a cycle of a RF bias voltage signal). A monotonic IEDF (i.e. primarily a single non-zero ion energy levels or absolute voltage potential over a cycle of a RF bias voltage signal) is better than a bimodal IEDF for controlling etch profiles and/or etch selectivity.
As another example, the harmonically controlled multiple sine wave biasing approach may be implemented in high-power implementations, but includes the use of large expensive generators, which are difficult to isolate from each other when operating at low bias RF frequencies. The harmonically controlled multiple sine wave biasing approach experiences instantaneous high voltage peaks or nulls that affect instantaneous ion energy levels due to variation in instantaneous plasma sheath voltage.
The shaped biasing approaches can be power limited and also includes large expensive power generators. One shaped biasing approach includes a broadband amplifier. It is difficult to properly match a non-linear plasma impedance to a source impedance of the broadband amplifier. In addition, a broadband amplifier is typically power inefficient and expensive.
Another shaped biasing approach includes the use of a switch mode power supply and current source for generating a bias potential. This approach includes pulse width modulation and sine wave modulation and is power and voltage limited due to use of transistors in a half-bridge configuration and corresponding breakdown voltages of the transistors. Only one of the transistors is ON at any moment in time. It is also difficult to scale this approach for high power applications, such as high aspect ratio (HAR) plasma etch processes.
While the above systems enable a certain degree of control of a plasma process, the continually increasing need for smaller components and increased yields demand continual improvement over the above-described approaches.
A radio frequency power system is provided that includes bias modules, a switch, a matching network, and a control module. The bias modules are configured to generate respectively direct current (DC) bias voltages. The switch is configured to (i) receive current from the bias modules, and (ii) control flow of the current from the bias modules to generate a radio frequency bias voltage signal. The matching network is configured to (i) receive the radio frequency bias voltage signal, and (ii) based on the radio frequency bias voltage signal, supply at least a portion of a radio frequency output voltage signal to an electrode of a substrate support in a processing chamber. The control module is connected to the switch and configured to control a state of the switch based on the radio frequency output voltage signal to shape a waveform of the radio frequency bias voltage signal.
In other features, a method of operating a radio frequency power system is provided. The method includes: generating DC bias voltages via bias modules; receiving current from the bias modules at a switch; controlling flow of the current from the bias modules via the switch to generate a radio frequency bias voltage signal; receiving the radio frequency bias voltage signal at a first matching network; based on the radio frequency bias voltage signal, supplying at least a portion of a radio frequency output voltage signal to an electrode of a substrate support in a processing chamber; and controlling a state of the switch based on the radio frequency output voltage signal to shape a waveform of the radio frequency bias voltage signal.
In other features, a radio frequency power system for supplying radio frequency power to an electrode in a substrate support of a processing chamber is provided. The radio frequency power system includes a processor and a memory. The memory stores instructions executable by the processor and configured to: signal bias modules to generate direct current bias voltages; control a state of a switch to generate a radio frequency bias voltage signal based on the direct current bias voltages; receive a feedback signal including a portion of a radio frequency output signal generated via matching networks based on the radio frequency bias voltage, where the feedback signal is indicative of a radio frequency voltage at the electrode; and control the state of the switch based on the feedback signal to provide a predetermined ion energy distribution function.
Further areas of applicability of the present disclosure will become apparent from the detailed description, the claims and the drawings. The detailed description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the disclosure.
The present disclosure will become more fully understood from the detailed description and the accompanying drawings, wherein:
In the drawings, reference numbers may be reused to identify similar and/or identical elements.
A RF voltage generation system for setting a voltage potential of an electrode in, for example, a substrate support (e.g., an electrostatic chuck) of a processing chamber can include a source generator and a bias generator. An example of a RF power system 10 including a source generator 12 and a bias generator 14 are shown in
The examples set forth herein include RF voltage generation systems that provide high-power and shaped plasma sheath voltage waveforms, which control IEDFs. The RF voltage generation systems generate a flat periodic and highly negative plasma sheath voltage while providing a monotonic IEDF. In order to provide a flat periodic and highly negative bias RF voltage at a plasma sheath, output voltages of the source and bias generators are pre-distorted to account for plasma coupling and parasitic components of the RF delivery system. Examples of pre-distorted bias voltage signal VRFBias 30, composite source and bias voltage signal Vcomposite 32, and a sheath voltage signal VRFSheath 34 are shown in
The transformer T includes the primary winding and a secondary winding. An output of the primary winding is connected to a terminal of a switch (e.g., a metal-oxide-semiconductor field-effect transistor (MOSFET)). The switch SW is controlled by the control module 102. The control module 102 may operate the switch SW in a linear mode or a switch mode. During the linear mode, the switch SW is operated as a variable resistance and used to implement a linear regulator. The control module 102 and the switch SW operate as a high-speed RF voltage regulator. The voltages supplied from the control module 102 to a gate of the switch SW during the linear mode are within a non-saturated region of the switch SW. During the switch mode, the control module 102 supplies a voltage to the gate of the switch SW to operate the switch SW in a saturated region. During the switch mode, the switch SW is transitioned between ON and OFF states.
While the switch SW is in a partially ON state or full ON state, current passes from the bias modules 106, through the diodes1-N, through DC blocking capacitor CB1, through the primary winding of the transformer T, and then through the switch SW to a reference (or ground) terminal 111. The DC blocking capacitor CB1 prevents saturation of the transformer T. The current passing through the primary winding induces passage of current through the secondary winding of the transformer T. The secondary winding is connected to the reference terminal 111 at a first end and to the matching network 110 at a second end. A RF bias voltage signal having voltage(s) VRFBIAS is generated between the input of the matching network 110 and the reference terminal 111. The transformer T is a step-up transformer and thus increases a voltage magnitude of a combined envelope voltage(s) VENVELOPE to a magnitude of the RF bias voltage(s) VRFBIAS.
The matching networks 108, 110 are provided as examples, matching networks of different types and/or configurations may be incorporated in the RF power system 100 of
The outputs of the matching networks 108, 110 are connected to each other and to an electrode 114 of a substrate support 116 and provide a RF output voltage signal having voltage(s) VRFOUT. The substrate support 116 supports a substrate 118 in the processing chamber 112. The outputs of the matching networks 108, 110 are also connected to a detector 120. The detector 120 effectively filters out the RF voltage signal having the voltage(s) VRFSOURCE and provides a detected voltage signal having voltage(s) VRFBiasSense associated with the voltage(s) VRFBIAS. The detector 120 and corresponding connections provides a feedback loop for feedback control. The RF output voltage signal and the detected voltage signal may be referred to as feedback signals provided in the feedback loop. In one embodiment, the detector 120 includes a low pass filter or a band pass filter and permits passage and detection of frequencies within a predetermined range of one or more frequencies of the RF bias voltage signal having voltage(s) VRFBIAS. In one embodiment, the detector 120 is implemented as a low pass filter or band pass filter. In one embodiment, a frequency of the RF bias voltage signal having voltage(s) VRFBIAS is 400 kHz and the filter permits passage of a band of frequencies centered at 400 kHz. In another embodiment, the frequency of the RF bias voltage signal is 100 kHz-2 MHz.
The control module 102, in addition to receiving the voltage(s) VRFBiasSense, may also receive a pulse synchronization signal SYNC. The control module 102 controls the bias modules 106 based on the voltage(s) VRFBiasSense and the pulse synchronization signal SYNC. For example, timing and duration of ON periods of one or more of the bias modules may be based on the voltage(s) VRFBiasSense and the pulse synchronization signal SYNC. The control module 102 may control the frequency and/or duty cycle of the switch SW and thus the frequency and/or duty cycle of the RF bias voltage signal having voltage(s) VRFBias based on the voltage(s) VRFBiasSense and the pulse synchronization signal SYNC. Control of the DC bias voltages and parameters of the switch SW allows for precise shaping of the RF bias voltage signal and thus precise shaping of the RF voltage output signal and result voltage signal received at the electrode 114.
The RF power system 100 may further include memory 130. The memory 130 may be used to store set, predetermined and/or detected voltages and/or other operating parameters. The voltages may include VENVELOPE, VRFBIAS, VRFOUT, VRFBiasSense, etc. for each cycle. A cycle may refer to a cycle of VRFBias and/or VRFOUT. The parameters may include the voltage(s) VRFSource and parameters associated with the switch SW. The switch parameters may include frequency, duty cycle, ON times, OFF times, etc.
Examples of the voltage signals having voltages VENVELOPE, VRFBIAS are shown in
In one embodiment, the output of each of the bias modules 106 provides a step voltage of the combined envelope voltage signal 150. In the example of
The source generator 204 generates a source RF voltage signal having voltage(s) VRFSOURCE and a predetermined frequency. The source RF voltage signal is provided to the matching network 208. The bias modules 206 operate as DC power sources and generate respective bias DC voltage signals at predetermined DC voltages. Thus, the bias modules 206 may be referred to as bias generators. Outputs of the bias modules 206 are passed respectively through the diodes D1-DN. The outputs of the bias modules 206 are connected to an input terminal of the switch SW. In one embodiment, the bias modules 206 operate as batteries connected in parallel through the diodes D1-DN, such that the highest DC voltage output from the bias modules 206 is provided to the input of the switch SW. In other words, the output of the one of the bias modules 206 with the highest DC voltage is provided to the input of the switch SW.
The switch may be a MOSFET or other suitable switch. The switch SW is controlled by the control module 202. The control module 202 may operate the switch SW in a linear mode or a switch mode. During the linear mode, the switch SW is operated as a variable resistance and used to implement a linear regulator. The voltages supplied from the control module 202 to a gate of the switch SW during the linear mode are within a non-saturated region of the switch SW. During the switch mode, the control module 202 supplies a voltage to the gate of the switch SW to operate the switch SW in a saturated region. During the switch mode, the switch SW is transitioned between ON and OFF states.
While the switch SW is in a partially ON state or a full ON state, current passes from through the switch SW to the matching network 210. A RF output voltage VRFBIAS is generated and provided to the input of the matching network 210. Voltage magnitude(s) of the combined envelope voltage(s) VENVELOPE may be equal to magnitude(s) of the voltage(s) VRFBIAS minus a voltage drop across the switch SW, which is negligible when the switch SW is in a full ON state.
The matching networks 208, 210 are provided as examples, matching networks of different types and/or configurations may be incorporated in the RF power system 200 of
The outputs of the matching networks 208, 210 are connected to each other and to an electrode 214 of a substrate support 216 and provide a RF output voltage signal having voltage(s) VRFOUT. The substrate support 216 supports a substrate 218 in the processing chamber 212. The outputs of the matching networks 208, 210 are also connected to a detector 220. The detector 120 effectively filters out the RF voltage signal having the voltage(s) VRFSOURCE and provides a detected voltage signal having voltage(s) VRFBiasSense associated with the voltage(s) VRFBIAS. The detector 220 and corresponding connections provides a feedback loop for feedback control. In one embodiment, the detector 220 operates similar as the filter 120 of
The control module 202, in addition to receiving the voltage(s) VRFBiasSense, may also receive a pulse synchronization signal SYNC. The control module 202 controls the bias modules 206 based on the voltage(s) VRFBiasSense and the pulse synchronization signal SYNC. For example, timing and duration of ON periods of one or more of the bias modules may be based on the voltage(s) VRFBiasSense and the pulse synchronization signal SYNC. The control module 202 may control the frequency and/or duty cycle of the switch SW and thus the frequency and/or duty cycle of the RF bias voltage signal having voltage(s) VRFBias based on the voltage(s) VRFBiasSense and the pulse synchronization signal SYNC.
For further defined structure of the control modules of
The method may begin at 300. At 302, the control module 250 and/or the pattern module 252 may select a RF voltage pattern for VRFBias, VRFOUT, and/or a plasma sheath voltage. The control module 250 may select the RF voltage pattern to provide a predetermined IEDF (e.g., monotonic IEDF). Thus, the control module 250 may be referred to as an IEDF controller. This RF voltage pattern may be selected for a recipe and/or etching pattern followed during, for example, etching, cleaning, and/or other substrate processing operation.
At 304, the control module 250 and/or the sheath voltage module 254, based on the selected RF voltage pattern and for a current cycle, may determine or select one or more plasma sheath voltages and/or voltages indicative of the sheath voltages, such as one or more RF output voltages for VRFOUT. At 306, the control module 250 and/or the bias voltage module 256 may determine one or more voltages for VRFBias based on the determined or selected one or more plasma sheath voltages and/or voltages indicative of the sheath voltages.
At 308, the control module 250 may determine, based on the voltage(s) VRFBias and/or other parameters. Some parameters may be determined by the DC voltage module 258, such as DC bias voltages of bias modules (e.g., the bias modules 106, 206). Other parameters may be determined by the switch module 260, such as switch parameters. Yet other parameters may be determined by the prediction module 262, such as predicted voltage(s) for VRFBiasSense. The predicted voltages may be based on previous voltage(s) for VRFBiasSense and corresponding determined and/or selected voltages and parameters. This information may be stored in a memory (e.g., one of the memories 130, 230). In one embodiment, this information is stored in tabular form relating the predicted voltage(s) to the other parameters.
At 310, the control module 250 and/or the DC voltage module 258 controls the bias modules to generate the DC bias voltages to define the outer RF bias voltage envelope to be followed. In one embodiment, one of the bias modules is left in an ON state. For this embodiment, the control module 250 and/or the DC voltage module 258 may activate one or more of the other bias modules, depending on the corresponding step being provided in the current cycle. The number of bias modules activated during a cycle may depend on the complexity of the RF voltage waveform being generated. The bias modules being activated during the current cycle may be activated in a sequential manner. When one or more bias modules are being activated, one or more other bias modules may be deactivated. Operation 310 may be performed while operation 312 is performed.
At 312, the control module 250 and/or the switch module 260 controls a state of the switch SW to provide the RF bias voltage signal having the voltage(s) VRFBias. This may include controlling a voltage provided to the gate of the switch, an ON time of the switch, an OFF time of the switch, and/or duration(s) in one or more states. The RF bias voltage signal is provided to an electrode of a substrate support via a matching network.
At 314, a filter (e.g., one of the filters 120, 220) receives an RF voltage output signal having voltage(s) VRFOUT and/or other detected voltage signal having voltages indicative of the plasma sheath voltage. In one embodiment, the voltage at the electrode is detected and provided to the filter. At 316, the filter filters the received voltage signal to provide a detected voltage signal having voltage(s) VRFBiasSense. The voltage(s) VRFBiasSense are received at the control module.
At 318, the control module 250 and/or the current state module 264 may store in the memory the voltage(s) VRFBiasSense and corresponding RF output voltage(s) VRFOUT, the DC bias voltages, and the switch parameters. At 320, the control module 250 and/or the comparison module 266 compares the detected voltage(s) VRFBiasSense to the predicted voltage(s) VRFBiasSense to determine difference values for the current cycle. At 322, the control module 250 and/or the comparison module 266 may store the difference values in the memory.
At 324, the control module 250 and/or the convergence module 268 adjusts one or more of the DC bias voltages and/or parameters of the switch for a next cycle based on (i) the difference values for the current cycle, (ii) difference values for a previous one or more cycles, and (iii) adjustments made based on results of the previous one or more cycles. Adjusting the DC bias voltages may include adjusting other parameters, such as ON times, OFF times, and/or durations in ON and OFF states of the bias modules. At 326, the control module 250 and/or the convergence module 268 may store the adjusted DC bias voltages and/or other parameters adjusted during operation 324. The adjustments made based on voltages, parameters and/or adjustments of previous cycles provides a feedforward method of converging on a waveform of the selected RF voltage pattern. The error from previous cycles is used to increase the rate of convergence. The control module 250 and/or the convergence module 268 in receiving the output of the filter and making the stated adjustments performs as a high-speed regulator.
At 328, the control module 250 may determine if another RF voltage cycle is to be generated for the currently selected RF voltage pattern. If another RF voltage cycle is to be generated, operation 310 is performed, otherwise operation 330 may be performed. At 330, the control module 250 may determine if another RF voltage pattern is to be selected. If another RF voltage pattern is to be selected, operation 302 may be performed, otherwise the method may end at 332.
The above-described operations are meant to be illustrative examples; the operations may be performed sequentially, synchronously, simultaneously, continuously, during overlapping time periods or in a different order depending upon the application. Also, any of the operations may not be performed or skipped depending on the implementation and/or sequence of events.
The RF power systems disclosed herein include fewer hardware components than traditional RF power systems such as the RF power systems previously described for the sine wave biasing, multiple sine wave biasing, and broadband amplifier/shaped biasing approaches. This decreases associated operating costs and increases reliability. The disclosed RF power systems also provide increased operating efficiency over the multiple sine wave and broadband amplifier/shaped biasing approaches. There is less wasted energy to heat due to use of multiple DC bias modules, which can be 90% efficient. The disclosed RF power systems are applicable to high voltage (e.g., greater than or equal to −10,000 V) applications and provide monotonic IEDFs for high aspect ratio (HAR) etching. HAR etching is used to manufacture 3D NAND flash memory devices, high density dynamic random access memory (DRAM) devices, and other memory devices, such as phase change random access memory (PCRAM). In one embodiment, the RF power systems may be implemented to precisely control low ion energy processes, such as atomic layer etch and atomic layer deposition processes. These processes are utilized in semiconductor logic processing and multi-patterning lithography processing.
The foregoing description is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses. The broad teachings of the disclosure can be implemented in a variety of forms. Therefore, while this disclosure includes particular examples, the true scope of the disclosure should not be so limited since other modifications will become apparent upon a study of the drawings, the specification, and the following claims. It should be understood that one or more steps within a method may be executed in different order (or concurrently) without altering the principles of the present disclosure. Further, although each of the embodiments is described above as having certain features, any one or more of those features described with respect to any embodiment of the disclosure can be implemented in and/or combined with features of any of the other embodiments, even if that combination is not explicitly described. In other words, the described embodiments are not mutually exclusive, and permutations of one or more embodiments with one another remain within the scope of this disclosure.
Although the terms first, second, third, etc. may be used herein to describe various elements, components, loops, circuits, and/or modules, these elements, components, loops, circuits, and/or modules should not be limited by these terms. These terms may be only used to distinguish one element, component, loop, circuit or module from another element, component, loop, circuit or module. Terms such as “first,” “second,” and other numerical terms when used herein do not imply a sequence or order unless clearly indicated by the context. Thus, a first element, component, loop, circuit or module discussed below could be termed a second element, component, loop, circuit or module without departing from the teachings of the example implementations disclosed herein.
Spatial and functional relationships between elements (for example, between modules, circuit elements, semiconductor layers, etc.) are described using various terms, including “connected,” “engaged,” “coupled,” “adjacent,” “next to,” “on top of,” “above,” “below,” and “disposed.” Unless explicitly described as being “direct,” when a relationship between first and second elements is described in the above disclosure, that relationship can be a direct relationship where no other intervening elements are present between the first and second elements, but can also be an indirect relationship where one or more intervening elements are present (either spatially or functionally) between the first and second elements. As used herein, the phrase at least one of A, B, and C should be construed to mean a logical (A OR B OR C), using a non-exclusive logical OR, and should not be construed to mean “at least one of A, at least one of B, and at least one of C.”
In the figures, the direction of an arrow, as indicated by the arrowhead, generally demonstrates the flow of information (such as data or instructions) that is of interest to the illustration. For example, when element A and element B exchange a variety of information but information transmitted from element A to element B is relevant to the illustration, the arrow may point from element A to element B. This unidirectional arrow does not imply that no other information is transmitted from element B to element A. Further, for information sent from element A to element B, element B may send requests for, or receipt acknowledgements of, the information to element A.
In this application, including the definitions below, the term “module” or the term “controller” may be replaced with the term “circuit.” The term “module” may refer to, be part of, or include: an Application Specific Integrated Circuit (ASIC); a digital, analog, or mixed analog/digital discrete circuit; a digital, analog, or mixed analog/digital integrated circuit; a combinational logic circuit; a field programmable gate array (FPGA); a processor circuit (shared, dedicated, or group) that executes code; a memory circuit (shared, dedicated, or group) that stores code executed by the processor circuit; other suitable hardware components that provide the described functionality; or a combination of some or all of the above, such as in a system-on-chip.
The module may include one or more interface circuits. In some examples, the interface circuits may include wired or wireless interfaces that are connected to a local area network (LAN), the Internet, a wide area network (WAN), or combinations thereof. The functionality of any given module of the present disclosure may be distributed among multiple modules that are connected via interface circuits. For example, multiple modules may allow load balancing. In a further example, a server (also known as remote, or cloud) module may accomplish some functionality on behalf of a client module.
The term code, as used above, may include software, firmware, and/or microcode, and may refer to programs, routines, functions, classes, data structures, and/or objects. The term shared processor circuit encompasses a single processor circuit that executes some or all code from multiple modules. The term group processor circuit encompasses a processor circuit that, in combination with additional processor circuits, executes some or all code from one or more modules. References to multiple processor circuits encompass multiple processor circuits on discrete dies, multiple processor circuits on a single die, multiple cores of a single processor circuit, multiple threads of a single processor circuit, or a combination of the above. The term shared memory circuit encompasses a single memory circuit that stores some or all code from multiple modules. The term group memory circuit encompasses a memory circuit that, in combination with additional memories, stores some or all code from one or more modules.
The term memory circuit is a subset of the term computer-readable medium. The term computer-readable medium, as used herein, does not encompass transitory electrical or electromagnetic signals propagating through a medium (such as on a carrier wave); the term computer-readable medium may therefore be considered tangible and non-transitory. Non-limiting examples of a non-transitory, tangible computer-readable medium are nonvolatile memory circuits (such as a flash memory circuit, an erasable programmable read-only memory circuit, or a mask read-only memory circuit), volatile memory circuits (such as a static random access memory circuit or a dynamic random access memory circuit), magnetic storage media (such as an analog or digital magnetic tape or a hard disk drive), and optical storage media (such as a CD, a DVD, or a Blu-ray Disc).
The apparatuses and methods described in this application may be partially or fully implemented by a special purpose computer created by configuring a general purpose computer to execute one or more particular functions embodied in computer programs. The functional blocks, flowchart components, and other elements described above serve as software specifications, which can be translated into the computer programs by the routine work of a skilled technician or programmer.
The computer programs include processor-executable instructions that are stored on at least one non-transitory, tangible computer-readable medium. The computer programs may also include or rely on stored data. The computer programs may encompass a basic input/output system (BIOS) that interacts with hardware of the special purpose computer, device drivers that interact with particular devices of the special purpose computer, one or more operating systems, user applications, background services, background applications, etc.
The computer programs may include: (i) descriptive text to be parsed, such as HTML (hypertext markup language), XML (extensible markup language), or JSON (JavaScript Object Notation) (ii) assembly code, (iii) object code generated from source code by a compiler, (iv) source code for execution by an interpreter, (v) source code for compilation and execution by a just-in-time compiler, etc. As examples only, source code may be written using syntax from languages including C, C++, C#, Objective-C, Swift, Haskell, Go, SQL, R, Lisp, Java®, Fortran, Perl, Pascal, Curl, OCaml, Javascript®, HTML5 (Hypertext Markup Language 5th revision), Ada, ASP (Active Server Pages), PHP (PHP: Hypertext Preprocessor), Scala, Eiffel, Smalltalk, Erlang, Ruby, Flash®, Visual Basic®, Lua, MATLAB, SIMULINK, and Python®.
None of the elements recited in the claims are intended to be a means-plus-function element within the meaning of 35 U.S.C. § 112(f) unless an element is expressly recited using the phrase “means for,” or in the case of a method claim using the phrases “operation for” or “step for.”
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