Claims
- 1. A piezoelectric device, comprising:
- (a) a piezoelectric element having a generally planar surface; and
- (b) a substrate having a generally planar surface and a different rate of thermal expansion than said piezoelectric element,
- one of said piezoelectric element and substrate planar surfaces containing a hollow portion that extends to be open to the exterior of the device; and
- wherein said hollow portion is disposed in at least part of all areas which are bonded together.
- 2. The piezoelectric device of claim 1, wherein said hollow portion is a first groove.
- 3. The piezoelectric device of claim 2, wherein said first groove is intersected by a second groove.
- 4. The piezoelectric device of claim 1, wherein said substrate comprises one of semiconductor, glass, and piezoelectric material.
- 5. The piezoelectric device of claim 1, wherein said substrate comprises one of silicon, gallium arsenide, and indium phosphate.
- 6. The piezoelectric device of claim 1, wherein said substrate is a silicon substrate on which an integrated circuit is formed.
- 7. The piezoelectric device of claim 1, wherein said substrate is a glass substrate on which an integrated circuit is formed, said integrated circuit including a thin-film transistor.
- 8. The piezoelectric device of claim 1, wherein said piezoelectric element comprises one of quartz, lithium niobate, lithium tantalate, and PLZT.
- 9. A piezoelectric device as defined in claim 1, wherein one of said piezoelectric element and said substrate contains a plurality of such hollow portions.
- 10. A piezoelectric device formed by a process comprising the steps of:
- (1) mirror finishing principal surfaces of a first substrate and a second substrate, said second substrate comprising a piezoelectric element having a different rate of thermal expansion than said first substrate;
- (2) forming a plurality of grooves on at least one of said principal surfaces of said first and second substrates and at least one of said plurality of grooves extends to be open to the exterior of the device;
- (3) joining said principal surfaces of said first substrate and said second substrate;
- (4) applying heat to the joined substrates and bonding the joined substrates;
- (5) forming an opening in said first substrate such that an area of said second substrate is exposed through said opening;
- (6) forming a plurality of piezoelectric elements by forming electrodes on the exposed area of the second substrate through said opening and on a rear side of said second substrate at an area corresponding to the exposed area; and
- (7) dividing the bonded substrates into portions each having one of said plurality of piezoelectric elements.
Parent Case Info
This is a division of application Ser. No. 08/677,548 filed Jul. 18, 1996.
US Referenced Citations (8)
Foreign Referenced Citations (3)
Number |
Date |
Country |
0 594 117 A1 |
Apr 1994 |
EPX |
0 616 426 A1 |
Sep 1994 |
EPX |
0 651 449 A2 |
May 1995 |
EPX |
Non-Patent Literature Citations (2)
Entry |
Abstract of JP 60-121715; Bonding Method for Semiconductor Wafer; Jun. 29, 1995; Toshiba K.K. *abstract*. |
Abstract of JP 62-292412; Method for Junction of Semiconductor Substrate; Dec. 23, 1987; Toshiba Corp. *abstract*. |
Divisions (1)
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Number |
Date |
Country |
Parent |
677548 |
Jul 1996 |
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