The present invention relates generally to block-based integrated circuit design methodologies and more particularly to a novel method for pin assignment in the blocks used in such methodologies.
In a conventional block-based design methodology, the design of an integrated circuit is defined by hierarchical netlist. The netlist contains information of the nets and instances of all components seen at each hierarchal level. At any one level, the components may consist of standard cells, hard and soft macros, functional blocks, and other known types of design blocks. The netlist is hierarchical in that a block component at any level of the netlist may in turn be comprised of one or more blocks, standard cells and nets at the next lower level.
Typically, at the top level of the netlist, several blocks may be placed to define the overall layout and function of the integrated circuit. Completing the top level of the netlist, standard cells may also be placed between the blocks and the wiring of the net routed to interconnect the blocks and standard cells to implement the function.
This process continues through each subsequent lower level of the hierarchy until the lowest level is reached at which each block seen at the lowest level is comprised of standard cells. Thus, at any currently seen level in the hierarchy, the blocks visible at the current level are placed with the standard cells also seen at such level and the wiring of the current level being routed.
Also at each level of the hierarchy, block pins are assigned to a respective physical location, typically along its edge or periphery, within each of the blocks seen at such level. These pins connect the wiring internal of each block to the wiring external of the block at the current level of the hierarchy. In the prior art, the assigning of these pins to a physical location in each block is performed by either a top-down approach or a bottom-up approach.
Generally, when the pins are assigned in the top-down approach, the nets and the blocks at the current level are seen, but not the components within the blocks. Conversely, when pins are assigned in the bottom-up approach, the components within the block are seen, but not the nets or other blocks that connect to the block. As compared to each other, the use of one of these approaches to assign block pins may confer specific benefits and advantages over the use of the other approach when criteria such as block placement, the placement of components within blocks and routing between and within blocks are considered. However, each of these approaches has its respective disadvantages and limitations in the overall integrated circuit design.
In the top-down approach, the block pins are assigned to their respective locations within a block after the integrated circuit design has been partitioned into the block hierarchy. More particularly, after the blocks have been placed at the current level of the hierarchy, the pins for each block are assigned to a physical location substantially adjacent its periphery or sides. The location to which any one pin is assigned in any one block is determined, for example, in accordance with the placement of such block with respect to the other blocks at the current level and the connectivity constraints between such pin and one or more other pins of the other blocks to which it will connect. Accordingly, a primary goal of the top-down approach is to assign each pin to an optimal physical location within its block in accordance with top-level routability and timing constraints of the integrated circuit design.
The blocks used in a typical netlist include hard macros, i.e., blocks that have been physically implemented in a library, and soft macros, i.e., blocks that have not yet been implemented, may be intermixed with each other. In the top-down approach, the hard and soft macros, as well as the other components, are placed after partitioning, and timing and physical modeling is performed. After block placement, the top-down pin assignment commences.
In each of the hard macros, the physical locations to which their respective pins are assigned have already been well defined in the library. The physical location each of the hard macro block pins will have vis-a-vis pins of other components will then be determined solely by the placement of the hard macro itself, and its pins will be not subject to further assignment to other locations. Accordingly, only the soft macro block pins may be assigned after block placement.
After block placement, it may be seen that a preferred placement for several block pins within a soft macro block may be along one of its edges when top-level routing and timing constraints with respect to other blocks is considered. However, this edge may not be able to accommodate all of these pins, either because of lack of available locations or because routing congestion would otherwise result. Therefore, some of these pins are then disadvantageously assigned to less preferential locations along other edges of the block. Although routing congestion may be eased, timing between blocks may be degraded.
Since at the time of pin assignment components within the block are not seen, the assigned locations may further disadvantageously degrade routing or timing to the components within the block to which these pins connect. For example, wire lengths to such block internal components may become excessive or internal routing may become congested.
In the bottom-up approach, each of the block level pins is pre-assigned to its respective physical location based primarily on data flow and timing within the block. For example, these pins may be assigned to locations within the block in accordance with the placement of the standard cells and lower level blocks inside the block. Preferably, each block pin is assigned to an edge of the block closest to the component within the same block to which the pin is connected to minimize wire length. Thus, the bottom-up approach is advantageous with respect to wire length inside the block when compared to the top-down approach as described above.
However, since the physical location for each of the block pins is fixed within each block, the location that each of these pins after block placement is solely a function of the placement of its respective block. Although within each block, wire lengths, data flow and timing may be acceptable, top level routability and timing constraints may be disadvantageously degraded.
In either of the pin assignment approaches described above, the block pins have been permanently assigned to locations adjacent the periphery of the block such that each of these pins can be accessed externally of the block with wires in the same hierarchical level of the netlist. Irrespective of the approach used, restricting pin locations to the periphery of a block disadvantageously excludes all other possible locations within the block that the pins may be placed to optimize placement with respect to both the components they connect to within a block and the pins of other blocks and cells in the current level of the netlist.
However, if block pins could be placed at any location internally in the block, and not along its periphery, these pins typically may only be accessed through a via dropped from a next higher level in the netlist. Although vias are well known in fabrication processes, some design processes do not allow a via to be dropped from a higher level to a location within a block since violation of a prohibition against stacking vias may result.
In
Typically, the block 1 would be internally routed such that the cell pin 4 would connect to one of the block pins 5. However, the placement of a block pin to connect to the cell pin 4 may optimally be at some internal location within the block 1 and not along its edge 6 or any other edge thereof. For example, this optimal internal location may be shown at a block pin 5A provided to connect to the cell pin 4. Routing of the block 1 between the cell pin 4 and the block pin 5A may exemplarily result in a first via 81 dropped from the M3 layer 33 at the location of the block pin 5A to the M2 layer 32 and a second via 82 dropped from the M2 layer 32 to the cell pin 4. The first via 81 and the second via 82 are vertically offset from each other such that a wire 9 in the M2 layer 32 is provided to make a connection between them.
The block pin 5A, since it is at a location internally within the block 1 and not along its edge 6, is no longer accessible to a router operating in the hierarchical level of the block 1 and, therefore, cannot be reached the current level of the net that includes the wires 7. To connect to the block pin 5A, a third via 83 would need to be dropped from the next higher level of the netlist. A wire (not shown) in the next higher level would need to be routed to the via 83 to connect to the block pin 5A.
However, a router at the next higher level would only see the block 1 and the block pins 5, including block pin 5A, and not the internal routing within the block 1. Should this router drop the via 83, a violation against the prohibition against stacking vias would occur, as best seen in
It is a primary object of the present invention to provide a pin assignment method that overcomes one or more disadvantages and limitations of the prior art hereinabove enumerated.
It is an important object of the present invention to provide a pin assignment method that enables block pins to be assigned to locations internally within a block after placement of the block to place such pins with respect to connectivity to pins of other blocks at the current level substantially concurrently with respect to connectivity to components within the block.
It is a further object of the present invention to provide in a pin assignment a method that allows placement of block pins internally within a block and further allowing dropping of vias to these internally located pins.
According to the present invention, each one of a plurality of pins are first assigned to a respective one of a plurality of first locations along a periphery of a block and components are then placed within in the block in relative proximity to the pins with which the components connect. Each of the pins may then be moved to a respective second internal location proximal the components to which such pins connect. The components may then have their placement refined in accordance to their relative position to the pins connecting to such components at the second location.
A feature in one particular embodiment of the present invention is that the final location of the pins is determined first preferentially with respect to interconnectivity between blocks and then replaced preferentially in accordance with respect to connectivity within the block. This feature advantageously optimizes connectivity constraints between blocks as with the top-down approach concurrently with optimizing connectivity constraints within each block as with the bottom-up approach. By combining the advantages of both approaches in a new and unique process, their respective disadvantages are mitigated.
For example, when the pins are first assigned to the block periphery, the top-level connectivity constraints may be taken into consideration for the placement of the pins similarly to the top-down approach. The components to which these pins connect are placed within the block, taking into consideration connectivity constraints between the components and the pins to which the components will connect. After the components are placed, any of the pins may be moved away from the block periphery to an internal location proximal the component to which it connects. The shape of the pins may also, in one particular embodiment, be abstracted to a distributed shape to enhance top-level routability. Internal block connectivity concerns, similar to the bottom-up approach, may be used when moving the pins. Finally, with the pins having been moved, the positioning of the components in the block may be refined, again in accordance with connectivity constraints between components and the pins connecting thereto. Thus, combining the advantages of a top-down and bottom-up approach to pin assignment results in a preferential placement of pins for connectivity to other blocks and cells in the current level of the netlist concurrently with preferential placement of pins for connectivity to components in the block.
Another feature in another embodiment of the present invention is that block pins may be placed as virtual pins to reserve spaces for vias. Such virtual pins may be formed in a temporarily created block top layer. The block is routed with connections being made to the virtual pins. The temporary top layer and virtual pins are removed during block abstraction such that pins remaining in the true top layer of the block can be accessed by vias from then next higher level in the netlist. This feature advantageously obviates violation of the prohibition against via stacking by ensuring that a via dropped from a hierarchical level above the block will not stack above a via routed within the block.
These and other objects, advantages and features of the present invention will ecome readily apparent to those skilled in the art from a study of the following escription of the Exemplary Preferred Embodiments when read in conjunction with the attached Drawing and appended Claims.
Referring now to
In the above described method of flowchart 10, the components 20 in the block 14 may be any of the components as defined above as exemplarily including standard cells, hard and soft macros and sub-blocks in the netlist. It is also to be understood that the first locations to which the block pins 16 are assigned in accordance with the assigning step 12 need not be limited to the positions, as seen in
Typically, the present invention is performed after the floor planning steps of a block-based design process. For example, in known block-based design processes data concerning the integrated circuit, such as netlist, timing constraints, libraries and physical data, is loaded such that the data can be used by the software implementing such process.
The software process then partitions the circuit being designed. After partitioning, initial timing and physical modeling followed by block placement are performed.
When the blocks are placed, the number of pins in each of the blocks is known, but not their location. Initially all such pins within a block may be placed at its center or at any other convenient location. It is at this point in the design process that the assigning step 12 of the present invention may be commenced to assign the pins to locations within each of the blocks.
With further reference to
To place the pins 16, in accordance with the placing step 30, known heuristic or global routing algorithms may be used. Typically, a heuristic based on the shortest distance of pin-to-pin connection may be readily performed and may yield reasonably acceptable results. However, if there are blockages or routing congestion, the heuristic used by itself may yield a sub-optimal result. A global router that detects blockages and congestion may avoid such blockages and congestion while routing pin-to-pin connections, resulting in improved placing of the pins 16 to their respective first locations.
Specific examples of the placing step 30 may be seen with further reference to
In one example, the placing step 30 may further include the step 38 of selecting a most critical path 39 to assign at least one pin 16a in the first block 34 and at least one corresponding pin 16b in the second block 36. The most critical path 39 may typically be chosen by first ranking the criticality of all paths based on timing constraints. For example, the path having the worst timing between the block 34 and the block 36 may be chosen as the most critical path 39. Since the path 39 has the worst ranking of criticality it should preferably be selected to be the shortest path between the block 34 and the block 36, as best seen in
In the exemplary design 32, the placing step 30 may first be performed on the pin 16a in the first block 34 to take it from the center of the block 34 (or any other initial position the pin occupies prior to performing the assigning step 12 as described above) to its respective first location, which is selected to be closest to the second block 36. Similarly, the placing step 30 may then be subsequently performed on the corresponding pin 16b in the second block 36 to place it from the center of the block 36 to its respective first location, which is selected to be closest to the first block 34 to result in the most critical path 39 to be the shortest path.
Placement for the remaining pins 16 in each of the first block 34 and the second block 36 may then proceed based, similarly as described immediately above, for each subsequent path in decreasing order of their criticality ranking. For example, the second most critical path would be identified and its respective pins assigned, and so forth until the least critical path is reached and its pins assigned.
As described immediately above, the placing step 30 is performed first with respect to pin 16a and subsequently with respect to pin 16b. In general, the broadest aspects of the method of the present invention as described in reference to
Another example of the placing step 30 of
With reference to
For example, as best seen in
In this specific example, the block pin 16c had first been placed in its first location n
The above described step 48 of distributing each respective one of the block pins 16 into its bounding box 46 beneficially enhances routability between a block pin 16 and its associated component pins 47 and eases routing congestion with the block 14. For example, each of the bounding boxes 46 generally defines an area containing the component pins 47 to which the respective block pin 16 will connect. When each of the block pins 16 are distributed into their respective bounding box 46, the component pins therein become grouped with the block pin 16 with which they connect. It is thus seen that any block pin 16 within its bounding box 46 has been placed within relative proximity to the components 20 to which it connects. The refining step 24 enhances this grouping by adjusting the position of the components 20 such that their component pins 47 are preferentially positioned with respect to the block pin 16 in the bounding box.
In any event, the distributing of the pins 16 must be done within the constraints of top-level routability. The moving step 22, and in particular the distributing step 48, together with the refining step 24, may be reiterated as often as necessary to provide an optimal placement for the pins 16.
The moving step 22 may further include the step 50 of abstracting a shape of each of the pins 16 from a small shape to a distributed shape, as best seen at 16 in
Generally, in block-based design processes, each block will have multiple layers of metal and the pin layer is chosen based on the number of layers used in a block. Typically, the top layer is used for the block pins, as described above with reference to
The width of the block pins 16 is coextensive with the minimum layer width, which is determined by the specific fabrication process to be used. If any of the pins 16 belong to a net that requires a larger width, such as for high current wires, such pins 16 assume the larger net width. Similarly, a minimum layer spacing rule for wires with the net is used to determine the spacing between neighboring pins 16, however, the net spacing rule may take precedence. In accordance with the net spacing rule, extra spacing may be reserved between wires of a net to minimize capacitive coupling between wires. The pins 16 in these nets subject to the rule assume the same wire spacing.
Furthermore, power or ground nets may be used to shield a signal net from potential noise induced by neighboring signal nets. The pins 16 in the one of the signal nets is accordingly separated by the power or ground net from the pins in the neighboring signal net.
As described above, the pins 16 after the performing the moving step 22 may be at locations anywhere within the block 14, subject to the criteria as described above. As described above with reference to
Prior to setting forth a description of this method, reference is made to
With further reference to
After the virtual pin 16v is defined, the method of
After the block 52 is routed, an abstracting step 80 is performed wherein the block 52 is abstracted to form geometrical pins and blockages for top level routing. In the abstraction, the virtual pin 16v, the blockage 63, and any other pins and blockages in the M4 layer 60 are removed. Similarly, the first via 68 as well as any other vias between the M4 layer 60 and the M3 layer 58 are also removed.
The above described pin assignment method of the present invention, as set forth in
Furthermore, the present invention may also be used in the block-based architecture as disclosed in U.S. Pat. No. 6,536,028 for Standard Block Architecture for Integrated Circuit Design and U.S. Pat. No. 6,467,074 for Integrated Circuit Architecture with Standard Blocks. In such event, the block 14 may the standard block as described in the herein referenced patents and the components 20 described above may be standard cells.
There has been described above a novel method for assigning pins in to individual blocks used in block-based integrated circuit design methodologies. Those skilled in the art may now make numerous uses of, and departures from, the above described exemplary embodiments without departing from the inventive principles disclosed herein.
Accordingly, the present invention is to be defined solely by the scope of the appended Claims.