Patent Application
20180331472
This disclosure pertains to computing system, and in particular (but not exclusively) connections to facilitate electronic communication.
Advances in semi-conductor processing and logic design have permitted an increase in the amount of logic that may be present on integrated circuit devices. As a corollary, computer system configurations have evolved from a single or multiple integrated circuits in a system to multiple cores, multiple hardware threads, and multiple logical processors present on individual integrated circuits, as well as other interfaces integrated within such processors. A processor or integrated circuit typically comprises a single physical processor die, where the processor die may include any number of cores, hardware threads, logical processors, interfaces, memory, controller hubs, etc.
As a result of the greater ability to fit more processing power in smaller packages, smaller computing devices have increased in popularity. Smartphones, tablets, ultrathin notebooks, and other user equipment have grown exponentially. However, these smaller devices are reliant on servers both for data storage and complex processing that exceeds the form factor. Consequently, the demand in the high-performance computing market (i.e. server space) has also increased. For instance, in modern servers, there is typically not only a single processor with multiple cores, but also multiple physical processors (also referred to as multiple sockets) to increase the computing power. But as the processing power grows along with the number of devices in a computing system, the communication between sockets and other devices becomes more critical.
In fact, interconnects have grown from more traditional multi-drop buses that primarily handled electrical communications to full blown interconnect architectures that facilitate fast communication. Further, as the demand for future high performance processors increases, demand grows for interconnect architectures capable of supporting the corresponding high data rates made available by next generation processors.
In the following description, numerous specific details are set forth, such as examples of specific types of processors and system configurations, specific hardware structures, specific architectural and micro architectural details, specific register configurations, specific instruction types, specific system components, specific measurements/heights, specific processor pipeline stages and operation etc. in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that these specific details need not be employed to practice the present invention. In other instances, well known components or methods, such as specific and alternative processor architectures, specific logic circuits/code for described algorithms, specific firmware code, specific interconnect operation, specific logic configurations, specific manufacturing techniques and materials, specific compiler implementations, specific expression of algorithms in code, specific power down and gating techniques/logic and other specific operational details of computer system haven't been described in detail in order to avoid unnecessarily obscuring the present invention.
Although the following embodiments may be described with reference to energy conservation and energy efficiency in specific integrated circuits, such as in computing platforms or microprocessors, other embodiments are applicable to other types of integrated circuits and logic devices. Similar techniques and teachings of embodiments described herein may be applied to other types of circuits or semiconductor devices that may also benefit from better energy efficiency and energy conservation. For example, the disclosed embodiments are not limited to desktop computer systems or Ultrabooks™. And may be also used in other devices, such as handheld devices, tablets, other thin notebooks, systems on a chip (SOC) devices, and embedded applications. Some examples of handheld devices include cellular phones, Internet protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications typically include a microcontroller, a digital signal processor (DSP), a system on a chip, network computers (NetPC), set-top boxes, network hubs, wide area network (WAN) switches, or any other system that can perform the functions and operations taught below. Moreover, the apparatus', methods, and systems described herein are not limited to physical computing devices, but may also relate to software optimizations for energy conservation and efficiency.
As computing systems are advancing, the components therein are becoming more complex. As a result, the interconnect architecture to couple and communicate between the components is also increasing in complexity to ensure bandwidth requirements are met for optimal component operation. Furthermore, different market segments demand different aspects of interconnect architectures to suit the market's needs. For example, servers require higher performance, while the mobile ecosystem is sometimes able to sacrifice overall performance for power savings. Yet, it's a singular purpose of most fabrics to provide highest possible performance with maximum power saving. Below, a number of interconnects are discussed, which would potentially benefit from aspects of the invention described herein.
One interconnect fabric architecture includes the Peripheral Component Interconnect (PCI) Express (PCIe) architecture. A primary goal of PCIe is to enable components and devices from different vendors to inter-operate in an open architecture, spanning multiple market segments; Clients (Desktops and Mobile), Servers (Standard and Enterprise), and Embedded and Communication devices. PCI Express is a high performance, general purpose I/O interconnect defined for a wide variety of future computing and communication platforms. Some PCI attributes, such as its usage model, load-store architecture, and software interfaces, have been maintained through its revisions, whereas previous parallel bus implementations have been replaced by a highly scalable, fully serial interface. The more recent versions of PCI Express take advantage of advances in point-to-point interconnects, Switch-based technology, and packetized protocol to deliver new levels of performance and features. Power Management, Quality Of Service (QoS), Hot-Plug/Hot-Swap support, Data Integrity, and Error Handling are among some of the advanced features supported by PCI Express.
Referring to
System memory 110 includes any memory device, such as random access memory (RAM), non-volatile (NV) memory, or other memory accessible by devices in system 100. System memory 110 is coupled to controller hub 115 through memory interface 116. Examples of a memory interface include a double-data rate (DDR) memory interface, a dual-channel DDR memory interface, and a dynamic RAM (DRAM) memory interface.
In one embodiment, controller hub 115 is a root hub, root complex, or root controller in a Peripheral Component Interconnect Express (PCIe or PCIE) interconnection hierarchy. Examples of controller hub 115 include a chipset, a memory controller hub (MCH), a northbridge, an interconnect controller hub (ICH) a southbridge, and a root controller/hub. Often the term chipset refers to two physically separate controller hubs, i.e. a memory controller hub (MCH) coupled to an interconnect controller hub (ICH). Note that current systems often include the MCH integrated with processor 105, while controller 115 is to communicate with I/O devices, in a similar manner as described below. In some embodiments, peer-to-peer routing is optionally supported through root complex 115.
Here, controller hub 115 is coupled to switch/bridge 120 through serial link 119. Input/output modules 117 and 121, which may also be referred to as interfaces/ports 117 and 121, include/implement a layered protocol stack to provide communication between controller hub 115 and switch 120. In one embodiment, multiple devices are capable of being coupled to switch 120.
Switch/bridge 120 routes packets/messages from device 125 upstream, i.e. up a hierarchy towards a root complex, to controller hub 115 and downstream, i.e. down a hierarchy away from a root controller, from processor 105 or system memory 110 to device 125. Switch 120, in one embodiment, is referred to as a logical assembly of multiple virtual PCI-to-PCI bridge devices. Device 125 includes any internal or external device or component to be coupled to an electronic system, such as an I/O device, a Network Interface Controller (NIC), an add-in card, an audio processor, a network processor, a hard-drive, a storage device, a CD/DVD ROM, a monitor, a printer, a mouse, a keyboard, a router, a portable storage device, a Firewire device, a Universal Serial Bus (USB) device, a scanner, and other input/output devices. Often in the PCIe vernacular, such as device, is referred to as an endpoint. Although not specifically shown, device 125 may include a PCIe to PCI/PCI-X bridge to support legacy or other version PCI devices. Endpoint devices in PCIe are often classified as legacy, PCIe, or root complex integrated endpoints.
Graphics accelerator 130 is also coupled to controller hub 115 through serial link 132. In one embodiment, graphics accelerator 130 is coupled to an MCH, which is coupled to an ICH. Switch 120, and accordingly I/O device 125, is then coupled to the ICH. I/O modules 131 and 118 are also to implement a layered protocol stack to communicate between graphics accelerator 130 and controller hub 115. Similar to the MCH discussion above, a graphics controller or the graphics accelerator 130 itself may be integrated in processor 105.
Turning to
PCI Express uses packets to communicate information between components. Packets are formed in the Transaction Layer 155 and Data Link Layer 210 to carry the information from the transmitting component to the receiving component. As the transmitted packets flow through the other layers, they are extended with additional information necessary to handle packets at those layers. At the receiving side the reverse process occurs and packets get transformed from their Physical Layer 220 representation to the Data Link Layer 210 representation and finally (for Transaction Layer Packets) to the form that can be processed by the Transaction Layer 155 of the receiving device.
In one embodiment, transaction layer 155 is to provide an interface between a device's processing core and the interconnect architecture, such as data link layer 210 and physical layer 220. In this regard, a primary responsibility of the transaction layer 155 is the assembly and disassembly of packets (i.e., transaction layer packets, or TLPs). The translation layer 155 typically manages credit-base flow control for TLPs. PCIe implements split transactions, i.e. transactions with request and response separated by time, allowing a link to carry other traffic while the target device gathers data for the response.
In addition PCIe utilizes credit-based flow control. In this scheme, a device advertises an initial amount of credit for each of the receive buffers in Transaction Layer 155. An external device at the opposite end of the link, such as controller hub 115 in
In one embodiment, four transaction address spaces include a configuration address space, a memory address space, an input/output address space, and a message address space. Memory space transactions include one or more of read requests and write requests to transfer data to/from a memory-mapped location. In one embodiment, memory space transactions are capable of using two different address formats, e.g., a short address format, such as a 32-bit address, or a long address format, such as 64-bit address. Configuration space transactions are used to access configuration space of the PCIe devices. Transactions to the configuration space include read requests and write requests. Message transactions are defined to support in-band communication between PCIe agents.
Therefore, in one embodiment, transaction layer 155 assembles packet header/payload 156. Format for current packet headers/payloads may be found in the PCIe specification at the PCIe specification website.
Quickly referring to
Transaction descriptor 300 includes global identifier field 302, attributes field 304 and channel identifier field 306. In the illustrated example, global identifier field 302 is depicted comprising local transaction identifier field 308 and source identifier field 310. In one embodiment, global transaction identifier 302 is unique for all outstanding requests.
According to one implementation, local transaction identifier field 308 is a field generated by a requesting agent, and it is unique for all outstanding requests that require a completion for that requesting agent. Furthermore, in this example, source identifier 310 uniquely identifies the requestor agent within a PCIe hierarchy. Accordingly, together with source ID 310, local transaction identifier 308 field provides global identification of a transaction within a hierarchy domain.
Attributes field 304 specifies characteristics and relationships of the transaction. In this regard, attributes field 304 is potentially used to provide additional information that allows modification of the default handling of transactions. In one embodiment, attributes field 304 includes priority field 312, reserved field 314, ordering field 316, and no-snoop field 318. Here, priority sub-field 312 may be modified by an initiator to assign a priority to the transaction. Reserved attribute field 314 is left reserved for future, or vendor-defined usage. Possible usage models using priority or security attributes may be implemented using the reserved attribute field.
In this example, ordering attribute field 316 is used to supply optional information conveying the type of ordering that may modify default ordering rules. According to one example implementation, an ordering attribute of “0” denotes default ordering rules are to apply, wherein an ordering attribute of “1” denotes relaxed ordering, wherein writes can pass writes in the same direction, and read completions can pass writes in the same direction. Snoop attribute field 318 is utilized to determine if transactions are snooped. As shown, channel ID Field 306 identifies a channel that a transaction is associated with.
Link layer 210, also referred to as data link layer 210, acts as an intermediate stage between transaction layer 155 and the physical layer 220. In one embodiment, a responsibility of the data link layer 210 is providing a reliable mechanism for exchanging Transaction Layer Packets (TLPs) between two components a link. One side of the Data Link Layer 210 accepts TLPs assembled by the Transaction Layer 155, applies packet sequence identifier 211, i.e. an identification number or packet number, calculates and applies an error detection code, i.e. CRC 212, and submits the modified TLPs to the Physical Layer 220 for transmission across a physical to an external device.
In one embodiment, physical layer 220 includes logical sub block 221 and electrical sub-block 222 to physically transmit a packet to an external device. Here, logical sub-block 221 is responsible for the “digital” functions of Physical Layer 221. In this regard, the logical sub-block includes a transmit section to prepare outgoing information for transmission by physical sub-block 222, and a receiver section to identify and prepare received information before passing it to the Link Layer 210.
Physical block 222 includes a transmitter and a receiver. The transmitter is supplied by logical sub-block 221 with symbols, which the transmitter serializes and transmits onto to an external device. The receiver is supplied with serialized symbols from an external device and transforms the received signals into a bit-stream. The bit-stream is de-serialized and supplied to logical sub-block 221. In one embodiment, an 8b/10b transmission code is employed, where ten-bit symbols are transmitted/received. Here, special symbols are used to frame a packet with frames 223. In addition, in one example, the receiver also provides a symbol clock recovered from the incoming serial stream.
As stated above, although transaction layer 155, link layer 210, and physical layer 220 are discussed in reference to a specific embodiment of a PCIe protocol stack, a layered protocol stack is not so limited. In fact, any layered protocol may be included/implemented. As an example, an port/interface that is represented as a layered protocol includes: (1) a first layer to assemble packets, i.e. a transaction layer; a second layer to sequence packets, i.e. a link layer; and a third layer to transmit the packets, i.e. a physical layer. As a specific example, a common standard interface (CSI) layered protocol is utilized.
Referring next to
A transmission path refers to any path for transmitting data, such as a transmission line, a copper line, an optical line, a wireless communication channel, an infrared communication link, or other communication path. A connection between two devices, such as device 405 and device 410, is referred to as a link, such as link 415. A link may support one lane—each lane representing a set of differential signal pairs (one pair for transmission, one pair for reception). To scale bandwidth, a link may aggregate multiple lanes denoted by xN, where N is any supported Link width, such as 1, 2, 4, 8, 12, 16, 32, 64, or wider.
A differential pair refers to two transmission paths, such as lines 416 and 417, to transmit differential signals. As an example, when line 416 toggles from a low voltage level to a high voltage level, i.e. a rising edge, line 417 drives from a high logic level to a low logic level, i.e. a falling edge. Differential signals potentially demonstrate better electrical characteristics, such as better signal integrity, i.e. cross-coupling, voltage overshoot/undershoot, ringing, etc. This allows for better timing window, which enables faster transmission frequencies.
Some systems can include connectors to allow additional computing components to be added to the system, such as graphics cards, processor cards, memory cards, I/O cards, etc. A circuit board, such as a motherboard or baseboard can include one or more connectors to accept an expansion or add-in card. One of a variety of compatible cards can be mounted to a baseboard using the connector so as to communicatively couple the card to the board by one of a set of conductors. A pin field can be provided on the connector through which the electrical connections can be facilitated. An add-card can be configured for a specific purpose, so as to extend functionality of the computer to which it is connected (e.g., through the computer's baseboard). In one example implementation, the add-in card comprises a device compatible with a PCI-based interconnect protocol, such as PCIe. In examples such as PCIe or other technologies, communications can involve differential signaling using differential conductor pairs provided in the pin field of the connector.
In one example of a connector, all contacts are electrically isolated from one another by airspace and a plastic connector shell. In this example, conductors 510 and 512 represent a first differential pair, capable of carrying equal and opposite currents to balance the signal integrity effects. Conductors 520 and 522 represent a second differential pair. Ground conductor pairs 530 and 532, 540 and 542, and 550 and 552 are joined only at the printed circuit board (PCB) level (baseboard and AIC). In some implementations, a ground conductor (e.g., 542) adjacent to a signal conductor (e.g., 510) of a differential pair may balance some of the return current (in addition to 512). (It should be noted that in other implementations the signals are not differential. This, however, does not necessarily limit the applicability of the concepts described herein, as the above concepts can be applied to other systems, including signals that are non-differential signals.)
As noted above, the principles described above can be applied to connections, devices, and systems compliant with a PCIe-based specification. For instance, in the case of PCIe Gen4, data rates may meet or exceed 16 GT/s. To support PCIe Gen4 traffic the frequency bandwidth may generally be considered to span the 0-8 GHz range. This exceeds the bandwidth of previous PCIe versions' connector interface, (e.g., where the PCIe Gen3 Card Electromechanical Spec (CEM Spec) and common PCIe Gen1-2-3 PCB design techniques are applied). In the pursuit of Gen4 readiness, numerous channel impairments that limit the performance of the connector have been identified (e.g., through electromagnetic component simulation as well as simulation at the channel level, and subsequently confirmed in hardware, using vector network analysis) that did not meaningfully affect PCIe Gen1-2-3 channels. Accordingly, there is a desire to develop enhanced PCIe connectors (and other high speed interconnect connectors) capable of handling the high data rates of next generation interconnects and corresponding processors, among other example issues.
As shown in
In some implementations, the systems described above can be implemented to include features to reduce crosstalk within a connector pin field and address at least some of the example issues introduced above. Among the example benefits of such features, insertion loss and mode conversion of the connector can be improved. Accordingly, crosstalk effects can be reduced to enhance signal quality of neighboring data lanes. Such solutions can be applied to connector pin fields including those defined in PCIe and PCIe-based specifications, as well as other interconnect specifications.
For instance, in the example of PCIe-compliant connectors, some pin positions in the PCIe pin field suffer much higher broadband crosstalk than others. This crosstalk does not originate in the connector body itself. Instead, it stems from the irregular PCIe connector pin field signal assignment, where the via to via crosstalk among particular pin pairs in the connector's baseboard pin field is markedly higher than at other locations. This issue has been shown to greatly degrade channel performance in the affected lanes. Since the overall bus performance of the connector link is limited by the performance of its worst lanes, remediation of this crosstalk is particularly beneficial for PCIe Gen4 and other high-speed interconnects utilizing sideband signaling.
In some implementations, a desired pin field (e.g., a PCIe pin field) for a set of high speed differential pairs ideally constitutes a Ground-Ground-Signal-Signal-Ground-Ground pattern. In such cases, each differential pair can thus be viewed as having four ground return paths; each comprising the baseboard vias, the connector contact, and the mating add-in card. In such instances, the each differential pair is effectively “surrounded” by ground conductors, which assists in insulating the differential pair from crosstalk effects from other lanes and corresponding pins. In some cases, these four ground conductors can be sufficient to reduce broadband crosstalk and prevent mode conversion.
In real world pin fields, the Ground-Ground-Signal-Signal-Ground-Ground pattern can be broken through the provision of the occasional sideband pins for corresponding sideband channels. For instance, at other positions, the differential pair may have only two or three adjacent ground return paths. This is due to sideband signals that may be assigned to Clock Request#, Power Break#, or multiple Present2# and Reserved pins. Each of these sideband signals effectively displaces a ground conductor and interrupts the Ground-Ground-Signal-Signal-Ground-Ground pattern. This issue is present, for instance, in every connector that uses the PCIe CEM spec mandated pin field pattern, and in every PCIe connector length, including the x1, x4, x8, and x16 styles, among other examples.
In the example of
Turning to
In one example, the baseboard (x,y) via locations for the pins in the PCIe thru-hole and press-fit connectors can be dictated by the PCIe Card Electromechanical specification (CEM spec). Similarly, the electrical function assigned to each pin can also be dictated by the CEM spec. Compliance with this or another specification can force adoption of a particular pin field layout leaving no option for reassigning the pins to arrange the grounds differently, or to move the pin locations. In general, while the 4-ground Ground-Ground-Signal-Signal-Ground-Ground pattern provides adequate ground return paths for each differential pair, however, the addition of sentry vias proximate to non-ground pins (as shown in the example of
As introduced above, a number (typically 2, 3, or 4) small ground vias (sentry vias) can be added adjacent to each sideband pin in the PCIe connector pin field. These small ground vias can provide a ground return path roughly equivalent to that of a large, CEM spec compliant, 27 mil ground via at the same pin position, and will not interfere with the assigned function of the sideband connector pin. In
9.
Sentry vias can also help reduce a separate crosstalk mechanism, which stems from a resonant crosstalk peak in the sideband conductors, which falls at about 5 GHz. The sideband resonant crosstalk can be suppressed using AC sideband termination to damp the resonance, such as described in Provisional Patent Application Ser. No. 62/184,830, filed Jun. 25, 2015, and entitled “Sideband Conductor Resonance Mitigation” incorporated by reference in its entirety. However, sentry vias can partially abate the effects of sideband resonance. When combined, AC sideband termination and sentry vias can deliver better performance than either solution in isolation.
The pin field, as in other examples, can additionally accommodate several sideband signals among the high speed section of the x4 connector, such as those shown in Table 1.
The concept introduced in the example of
In some implementations, the coupling that causes the majority of the crosstalk is largely confined to the baseboard. In such cases, the magnitude of the crosstalk is linked to the thickness of the baseboard. Accordingly, the number of ground vias employed can be based on the thickness of the circuit baseboard. For instance, thinner baseboards may require only two sentry vias to reduce crosstalk to −35 dB at 8 GHz, for example, while a 120 mil board would use four sentry vias to suppress crosstalk to the same level.
A similar approach can be used to shield the 100 MHz baseband reference clock (RefClk) signals from the adjacent Rx0 pin pair. While the frequency content of the RefClk is generally lower than full-speed Gen4 traffic, the crosstalk between the RefClk pair (A13, A14) and Rx0 (A15, A16) may be markedly higher than any other adjacent pairs in the connector. While the addition of sentry vias for the RefClk pins can substantially reduce this crosstalk, it may not even reach the level of the baseline case for some lanes (e.g., Lane Rx0↔Lane Rx1). For instance, while the fundamental 100 MHz frequency of the RefClock falls at a frequency where its crosstalk might be discounted, the risetime should also be considered. If the risetime of the RefClk transition is sufficiently fast, it is possible that it could introduce glitches in the Rx0 Lane. Therefore, it may be prudent to add sentry vias to RefClk, to obtain 4-6 dB of incremental crosstalk reduction. Further, the RefClk pair may benefit from greater immunity to Rx0 traffic. For instance,
The principles above can be applied across a connector pin field so as to add one or more ground vias proximate or adjacent to each sideband pin in the pin field, such as shown in the example of
As shown in the examples of
In some implementations, even when providing each sideband pin with corresponding ground vias, some energy can “leak” around edges of the pin field and introduce crosstalk. For instance, as shown in
Note that the apparatus', methods', and systems described above may be implemented in any electronic device or system as aforementioned. As specific illustrations, the figures below provide exemplary systems for utilizing the invention as described herein. As the systems below are described in more detail, a number of different interconnects are disclosed, described, and revisited from the discussion above. And as is readily apparent, the advances described above may be applied to any of those interconnects, fabrics, or architectures.
Referring to
In one embodiment, a processing element refers to hardware or logic to support a software thread. Examples of hardware processing elements include: a thread unit, a thread slot, a thread, a process unit, a context, a context unit, a logical processor, a hardware thread, a core, and/or any other element, which is capable of holding a state for a processor, such as an execution state or architectural state. In other words, a processing element, in one embodiment, refers to any hardware capable of being independently associated with code, such as a software thread, operating system, application, or other code. A physical processor (or processor socket) typically refers to an integrated circuit, which potentially includes any number of other processing elements, such as cores or hardware threads.
A core often refers to logic located on an integrated circuit capable of maintaining an independent architectural state, wherein each independently maintained architectural state is associated with at least some dedicated execution resources. In contrast to cores, a hardware thread typically refers to any logic located on an integrated circuit capable of maintaining an independent architectural state, wherein the independently maintained architectural states share access to execution resources. As can be seen, when certain resources are shared and others are dedicated to an architectural state, the line between the nomenclature of a hardware thread and core overlaps. Yet often, a core and a hardware thread are viewed by an operating system as individual logical processors, where the operating system is able to individually schedule operations on each logical processor.
Physical processor 1600 as illustrated in
As depicted, core 1601 includes two hardware threads 1601a and 1601b, which may also be referred to as hardware thread slots 1601a and 1601b. Therefore, software entities, such as an operating system, in one embodiment potentially view processor 1600 as four separate processors, i.e., four logical processors or processing elements capable of executing four software threads concurrently. As alluded to above, a first thread is associated with architecture state registers 1601a, a second thread is associated with architecture state registers 1601b, a third thread may be associated with architecture state registers 1602a, and a fourth thread may be associated with architecture state registers 1602b. Here, each of the architecture state registers (1601a, 1601b, 1602a, and 1602b) may be referred to as processing elements, thread slots, or thread units, as described above. As illustrated, architecture state registers 1601a are replicated in architecture state registers 1601b, so individual architecture states/contexts are capable of being stored for logical processor 1601a and logical processor 1601b. In core 1601, other smaller resources, such as instruction pointers and renaming logic in allocator and renamer block 1630 may also be replicated for threads 1601a and 1601b. Some resources, such as re-order buffers in reorder/retirement unit 1635 ILTB 1620, load/store buffers, and queues may be shared through partitioning. Other resources, such as general purpose internal registers, page-table base register(s), low-level data-cache and data-TLB 1615, execution unit(s) 1640, and portions of out-of-order unit 1635 are potentially fully shared.
Processor 1600 often includes other resources, which may be fully shared, shared through partitioning, or dedicated by/to processing elements. In
Core 1601 further includes decode module 1625 coupled to fetch unit 1620 to decode fetched elements. Fetch logic, in one embodiment, includes individual sequencers associated with thread slots 1601a, 1601b, respectively. Usually core 1601 is associated with a first ISA, which defines/specifies instructions executable on processor 1600. Often machine code instructions that are part of the first ISA include a portion of the instruction (referred to as an opcode), which references/specifies an instruction or operation to be performed. Decode logic 1625 includes circuitry that recognizes these instructions from their opcodes and passes the decoded instructions on in the pipeline for processing as defined by the first ISA. For example, as discussed in more detail below decoders 1625, in one embodiment, include logic designed or adapted to recognize specific instructions, such as transactional instruction. As a result of the recognition by decoders 1625, the architecture or core 1601 takes specific, predefined actions to perform tasks associated with the appropriate instruction. It is important to note that any of the tasks, blocks, operations, and methods described herein may be performed in response to a single or multiple instructions; some of which may be new or old instructions. Note decoders 1626, in one embodiment, recognize the same ISA (or a subset thereof). Alternatively, in a heterogeneous core environment, decoders 1626 recognize a second ISA (either a subset of the first ISA or a distinct ISA).
In one example, allocator and renamer block 1630 includes an allocator to reserve resources, such as register files to store instruction processing results. However, threads 1601a and 1601b are potentially capable of out-of-order execution, where allocator and renamer block 1630 also reserves other resources, such as reorder buffers to track instruction results. Unit 1630 may also include a register renamer to rename program/instruction reference registers to other registers internal to processor 1600. Reorder/retirement unit 1635 includes components, such as the reorder buffers mentioned above, load buffers, and store buffers, to support out-of-order execution and later in-order retirement of instructions executed out-of-order.
Scheduler and execution unit(s) block 1640, in one embodiment, includes a scheduler unit to schedule instructions/operation on execution units. For example, a floating point instruction is scheduled on a port of an execution unit that has an available floating point execution unit. Register files associated with the execution units are also included to store information instruction processing results. Exemplary execution units include a floating point execution unit, an integer execution unit, a jump execution unit, a load execution unit, a store execution unit, and other known execution units.
Lower level data cache and data translation buffer (D-TLB) 1650 are coupled to execution unit(s) 1640. The data cache is to store recently used/operated on elements, such as data operands, which are potentially held in memory coherency states. The D-TLB is to store recent virtual/linear to physical address translations. As a specific example, a processor may include a page table structure to break physical memory into a plurality of virtual pages.
Here, cores 1601 and 1602 share access to higher-level or further-out cache, such as a second level cache associated with on-chip interface 1610. Note that higher-level or further-out refers to cache levels increasing or getting further way from the execution unit(s). In one embodiment, higher-level cache is a last-level data cache—last cache in the memory hierarchy on processor 1600—such as a second or third level data cache. However, higher level cache is not so limited, as it may be associated with or include an instruction cache. A trace cache—a type of instruction cache—instead may be coupled after decoder 1625 to store recently decoded traces. Here, an instruction potentially refers to a macro-instruction (i.e. a general instruction recognized by the decoders), which may decode into a number of micro-instructions (micro-operations).
In the depicted configuration, processor 1600 also includes on-chip interface module 1610. Historically, a memory controller, which is described in more detail below, has been included in a computing system external to processor 1600. In this scenario, on-chip interface 1610 is to communicate with devices external to processor 1600, such as system memory 1675, a chipset (often including a memory controller hub to connect to memory 1675 and an I/O controller hub to connect peripheral devices), a memory controller hub, a northbridge, or other integrated circuit. And in this scenario, bus 1605 may include any known interconnect, such as multi-drop bus, a point-to-point interconnect, a serial interconnect, a parallel bus, a coherent (e.g. cache coherent) bus, a layered protocol architecture, a differential bus, and a GTL bus.
Memory 1675 may be dedicated to processor 1600 or shared with other devices in a system. Common examples of types of memory 1675 include DRAM, SRAM, non-volatile memory (NV memory), and other known storage devices. Note that device 1680 may include a graphic accelerator, processor or card coupled to a memory controller hub, data storage coupled to an I/O controller hub, a wireless transceiver, a flash device, an audio controller, a network controller, or other known device.
Recently however, as more logic and devices are being integrated on a single die, such as SOC, each of these devices may be incorporated on processor 1600. For example in one embodiment, a memory controller hub is on the same package and/or die with processor 1600. Here, a portion of the core (an on-core portion) 1610 includes one or more controller(s) for interfacing with other devices such as memory 1675 or a graphics device 1680. The configuration including an interconnect and controllers for interfacing with such devices is often referred to as an on-core (or un-core configuration). As an example, on-chip interface 1610 includes a ring interconnect for on-chip communication and a high-speed serial point-to-point link 1605 for off-chip communication. Yet, in the SOC environment, even more devices, such as the network interface, co-processors, memory 1675, graphics processor 1680, and any other known computer devices/interface may be integrated on a single die or integrated circuit to provide small form factor with high functionality and low power consumption.
In one embodiment, processor 1600 is capable of executing a compiler, optimization, and/or translator code 1677 to compile, translate, and/or optimize application code 1676 to support the apparatus and methods described herein or to interface therewith. A compiler often includes a program or set of programs to translate source text/code into target text/code. Usually, compilation of program/application code with a compiler is done in multiple phases and passes to transform hi-level programming language code into low-level machine or assembly language code. Yet, single pass compilers may still be utilized for simple compilation. A compiler may utilize any known compilation techniques and perform any known compiler operations, such as lexical analysis, preprocessing, parsing, semantic analysis, code generation, code transformation, and code optimization.
Larger compilers often include multiple phases, but most often these phases are included within two general phases: (1) a front-end, i.e. generally where syntactic processing, semantic processing, and some transformation/optimization may take place, and (2) a back-end, i.e. generally where analysis, transformations, optimizations, and code generation takes place. Some compilers refer to a middle, which illustrates the blurring of delineation between a front-end and back end of a compiler. As a result, reference to insertion, association, generation, or other operation of a compiler may take place in any of the aforementioned phases or passes, as well as any other known phases or passes of a compiler. As an illustrative example, a compiler potentially inserts operations, calls, functions, etc. in one or more phases of compilation, such as insertion of calls/operations in a front-end phase of compilation and then transformation of the calls/operations into lower-level code during a transformation phase. Note that during dynamic compilation, compiler code or dynamic optimization code may insert such operations/calls, as well as optimize the code for execution during runtime. As a specific illustrative example, binary code (already compiled code) may be dynamically optimized during runtime. Here, the program code may include the dynamic optimization code, the binary code, or a combination thereof.
Similar to a compiler, a translator, such as a binary translator, translates code either statically or dynamically to optimize and/or translate code. Therefore, reference to execution of code, application code, program code, or other software environment may refer to: (1) execution of a compiler program(s), optimization code optimizer, or translator either dynamically or statically, to compile program code, to maintain software structures, to perform other operations, to optimize code, or to translate code; (2) execution of main program code including operations/calls, such as application code that has been optimized/compiled; (3) execution of other program code, such as libraries, associated with the main program code to maintain software structures, to perform other software related operations, or to optimize code; or (4) a combination thereof.
Referring now to
In various embodiments, system agent domain 1710 handles power control events and power management, such that individual units of domains 1730 and 1760 (e.g. cores and/or graphics engines) are independently controllable to dynamically operate at an appropriate power mode/level (e.g. active, turbo, sleep, hibernate, deep sleep, or other Advanced Configuration Power Interface like state) in light of the activity (or inactivity) occurring in the given unit. Each of domains 1730 and 1760 may operate at different voltage and/or power, and furthermore the individual units within the domains each potentially operate at an independent frequency and voltage. Note that while only shown with three domains, understand the scope of the present invention is not limited in this regard and additional domains may be present in other embodiments.
As shown, each core 1730 further includes low level caches in addition to various execution units and additional processing elements. Here, the various cores are coupled to each other and to a shared cache memory that is formed of a plurality of units or slices of a last level cache (LLC) 1740A-1740N; these LLCs often include storage and cache controller functionality and are shared amongst the cores, as well as potentially among the graphics engine too.
As seen, a ring interconnect 1750 couples the cores together, and provides interconnection between the core domain 1730, graphics domain 1760 and system agent circuitry 1710, via a plurality of ring stops 1752A-1752N, each at a coupling between a core and LLC slice. As seen in
As further depicted, system agent domain 1710 includes display engine 1712 which is to provide control of and an interface to an associated display. System agent domain 1710 may include other units, such as: an integrated memory controller 1720 that provides for an interface to a system memory (e.g., a DRAM implemented with multiple DIMMs; coherence logic 1722 to perform memory coherence operations. Multiple interfaces may be present to enable interconnection between the processor and other circuitry. For example, in one embodiment at least one direct media interface (DMI) 1716 interface is provided as well as one or more PCIe™ interfaces 1714. The display engine and these interfaces typically couple to memory via a PCIe™ bridge 1718. Still further, to provide for communications between other agents, such as additional processors or other circuitry, one or more other interfaces (e.g. an Intel® Quick Path Interconnect (QPI) fabric) may be provided.
Turning to
Embodiments are not limited to computer systems. Alternative embodiments of the present invention can be used in other devices such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications can include a micro controller, a digital signal processor (DSP), system on a chip, network computers (NetPC), set-top boxes, network hubs, wide area network (WAN) switches, or any other system that can perform one or more instructions in accordance with at least one embodiment.
In this illustrated embodiment, processor 1802 includes one or more execution units 1808 to implement an algorithm that is to perform at least one instruction. One embodiment may be described in the context of a single processor desktop or server system, but alternative embodiments may be included in a multiprocessor system. System 1800 is an example of a ‘hub’ system architecture. The computer system 1800 includes a processor 1802 to process data signals. The processor 1802, as one illustrative example, includes a complex instruction set computer (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor, for example. The processor 1802 is coupled to a processor bus 1810 that transmits data signals between the processor 1802 and other components in the system 1800. The elements of system 1800 (e.g. graphics accelerator 1812, memory controller hub 1816, memory 1820, I/O controller hub 1824, wireless transceiver 1826, Flash BIOS 1828, Network controller 1834, Audio controller 1836, Serial expansion port 1838, I/O controller 1840, etc.) perform their conventional functions that are well known to those familiar with the art.
In one embodiment, the processor 1802 includes a Level 1 (L1) internal cache memory 1804. Depending on the architecture, the processor 1802 may have a single internal cache or multiple levels of internal caches. Other embodiments include a combination of both internal and external caches depending on the particular implementation and needs. Register file 806 is to store different types of data in various registers including integer registers, floating point registers, vector registers, banked registers, shadow registers, checkpoint registers, status registers, and instruction pointer register.
Execution unit 1808, including logic to perform integer and floating point operations, also resides in the processor 1802. The processor 1802, in one embodiment, includes a microcode (ucode) ROM to store microcode, which when executed, is to perform algorithms for certain macroinstructions or handle complex scenarios. Here, microcode is potentially updateable to handle logic bugs/fixes for processor 1802. For one embodiment, execution unit 1808 includes logic to handle a packed instruction set 1809. By including the packed instruction set 1809 in the instruction set of a general-purpose processor 1802, along with associated circuitry to execute the instructions, the operations used by many multimedia applications may be performed using packed data in a general-purpose processor 1802. Thus, many multimedia applications are accelerated and executed more efficiently by using the full width of a processor's data bus for performing operations on packed data. This potentially eliminates the need to transfer smaller units of data across the processor's data bus to perform one or more operations, one data element at a time.
Alternate embodiments of an execution unit 1808 may also be used in micro controllers, embedded processors, graphics devices, DSPs, and other types of logic circuits. System 1800 includes a memory 820. Memory 1820 includes a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, flash memory device, or other memory device. Memory 1820 stores instructions and/or data represented by data signals that are to be executed by the processor 1802.
Note that any of the aforementioned features or aspects of the invention may be utilized on one or more interconnect illustrated in
While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.
A design may go through various stages, from creation to simulation to fabrication. Data representing a design may represent the design in a number of manners. First, as is useful in simulations, the hardware may be represented using a hardware description language or another functional description language. Additionally, a circuit level model with logic and/or transistor gates may be produced at some stages of the design process. Furthermore, most designs, at some stage, reach a level of data representing the physical placement of various devices in the hardware model. In the case where conventional semiconductor fabrication techniques are used, the data representing the hardware model may be the data specifying the presence or absence of various features on different mask layers for masks used to produce the integrated circuit. In any representation of the design, the data may be stored in any form of a machine readable medium. A memory or a magnetic or optical storage such as a disc may be the machine readable medium to store information transmitted via optical or electrical wave modulated or otherwise generated to transmit such information. When an electrical carrier wave indicating or carrying the code or design is transmitted, to the extent that copying, buffering, or re-transmission of the electrical signal is performed, a new copy is made. Thus, a communication provider or a network provider may store on a tangible, machine-readable medium, at least temporarily, an article, such as information encoded into a carrier wave, embodying techniques of embodiments of the present invention.
A module as used herein refers to any combination of hardware, software, and/or firmware. As an example, a module includes hardware, such as a micro-controller, associated with a non-transitory medium to store code adapted to be executed by the micro-controller. Therefore, reference to a module, in one embodiment, refers to the hardware, which is specifically configured to recognize and/or execute the code to be held on a non-transitory medium. Furthermore, in another embodiment, use of a module refers to the non-transitory medium including the code, which is specifically adapted to be executed by the microcontroller to perform predetermined operations. And as can be inferred, in yet another embodiment, the term module (in this example) may refer to the combination of the microcontroller and the non-transitory medium. Often module boundaries that are illustrated as separate commonly vary and potentially overlap. For example, a first and a second module may share hardware, software, firmware, or a combination thereof, while potentially retaining some independent hardware, software, or firmware. In one embodiment, use of the term logic includes hardware, such as transistors, registers, or other hardware, such as programmable logic devices.
Use of the phrase ‘to’ or ‘configured to,’ in one embodiment, refers to arranging, putting together, manufacturing, offering to sell, importing and/or designing an apparatus, hardware, logic, or element to perform a designated or determined task. In this example, an apparatus or element thereof that is not operating is still ‘configured to’ perform a designated task if it is designed, coupled, and/or interconnected to perform said designated task. As a purely illustrative example, a logic gate may provide a 0 or a 1 during operation. But a logic gate ‘configured to’ provide an enable signal to a clock does not include every potential logic gate that may provide a 1 or 0. Instead, the logic gate is one coupled in some manner that during operation the 1 or 0 output is to enable the clock. Note once again that use of the term ‘configured to’ does not require operation, but instead focus on the latent state of an apparatus, hardware, and/or element, where in the latent state the apparatus, hardware, and/or element is designed to perform a particular task when the apparatus, hardware, and/or element is operating.
Furthermore, use of the phrases ‘capable of/to,’ and or ‘operable to,’ in one embodiment, refers to some apparatus, logic, hardware, and/or element designed in such a way to enable use of the apparatus, logic, hardware, and/or element in a specified manner. Note as above that use of to, capable to, or operable to, in one embodiment, refers to the latent state of an apparatus, logic, hardware, and/or element, where the apparatus, logic, hardware, and/or element is not operating but is designed in such a manner to enable use of an apparatus in a specified manner.
A value, as used herein, includes any known representation of a number, a state, a logical state, or a binary logical state. Often, the use of logic levels, logic values, or logical values is also referred to as 1's and 0's, which simply represents binary logic states. For example, a 1 refers to a high logic level and 0 refers to a low logic level. In one embodiment, a storage cell, such as a transistor or flash cell, may be capable of holding a single logical value or multiple logical values. However, other representations of values in computer systems have been used. For example the decimal number ten may also be represented as a binary value of 1010 and a hexadecimal letter A. Therefore, a value includes any representation of information capable of being held in a computer system.
Moreover, states may be represented by values or portions of values. As an example, a first value, such as a logical one, may represent a default or initial state, while a second value, such as a logical zero, may represent a non-default state. In addition, the terms reset and set, in one embodiment, refer to a default and an updated value or state, respectively. For example, a default value potentially includes a high logical value, i.e. reset, while an updated value potentially includes a low logical value, i.e. set. Note that any combination of values may be utilized to represent any number of states.
The embodiments of methods, hardware, software, firmware or code set forth above may be implemented via instructions or code stored on a machine-accessible, machine readable, computer accessible, or computer readable medium which are executable by a processing element. A non-transitory machine-accessible/readable medium includes any mechanism that provides (i.e., stores and/or transmits) information in a form readable by a machine, such as a computer or electronic system. For example, a non-transitory machine-accessible medium includes random-access memory (RAM), such as static RAM (SRAM) or dynamic RAM (DRAM); ROM; magnetic or optical storage medium; flash memory devices; electrical storage devices; optical storage devices; acoustical storage devices; other form of storage devices for holding information received from transitory (propagated) signals (e.g., carrier waves, infrared signals, digital signals); etc, which are to be distinguished from the non-transitory mediums that may receive information there from.
Instructions used to program logic to perform embodiments of the invention may be stored within a memory in the system, such as DRAM, cache, flash memory, or other storage. Furthermore, the instructions can be distributed via a network or by way of other computer readable media. Thus a machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), but is not limited to, floppy diskettes, optical disks, Compact Disc, Read-Only Memory (CD-ROMs), and magneto-optical disks, Read-Only Memory (ROMs), Random Access Memory (RAM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), magnetic or optical cards, flash memory, or a tangible, machine-readable storage used in the transmission of information over the Internet via electrical, optical, acoustical or other forms of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.). Accordingly, the computer-readable medium includes any type of tangible machine-readable medium suitable for storing or transmitting electronic instructions or information in a form readable by a machine (e.g., a computer).
The following examples pertain to embodiments in accordance with this Specification. One or more embodiments may provide an apparatus, a system, a machine readable storage, a machine readable medium, and a method to provide a circuit board including a top ground plane, a bottom ground plane, a pin field of a connector with a plurality of pins including a plurality of differential pin pairs, one or more ground pins, and one or more sideband pins, where at least a particular one of the sideband pins is positioned within the pin field adjacent to a first pin of a first one of the differential pin pairs. One or more ground vias are provided on the circuit board positioned to correspond to the particular sideband pin.
In one example, the particular sideband pin is immediately between the first pin and a second pin of a second one of the differential pin pairs.
In one example, the ground via provides a ground return for energy emitted by one or both of the first and second pins during signaling on one or both of the first and second differential pin pairs.
In one example, the ground via mitigates crosstalk appearing on the sideband during signaling on either or both the first and second differential pin pairs.
In one example, the plurality of pins further includes a third pin and a fourth pin, and a particular one of the ground pins is positioned immediately between the third and fourth pins.
In one example, the third pin is included in a third differential pin pair.
In one example, the circuit board further includes one or more additional ground vias corresponding to the particular ground pin.
In one example, the third and fourth pins and ground pin are on an edge of the pin field and the ground via is positioned outside of the pin field.
In one example, the third pin is included in the first differential pair and the fourth pin is included in the second differential pair.
In one example, each ground via passes through the circuit board and is connected to both the top ground plane and to the bottom ground plane.
In one example, the ground via is placed a minimum allowed distance from the particular sideband pin.
In one example, the one or more ground vias include at least two ground vias.
In one example, the at least two ground vias are aligned parallel to the first differential pair.
In one example, the at least two ground vias are positioned to provide a path for routing of one or more conductive paths within the circuit board.
In one example, the one or more ground vias include at least three ground vias positioned around the perimeter of the particular sideband pin.
In one example, the pin field is laid out according to a PCIe-based specification.
In one example, the sideband pin includes a clock pin.
In one example, the first differential pin pair corresponds to a high speed differential channel and the sideband pin corresponds to a lower speed sideband channel.
One or more embodiments may provide an apparatus, a system that includes a baseboard including a top ground plane and a bottom ground plane, a connector, and a card device connected to the baseboard by the connector. The connector can include a pin field including a plurality of pins, where the plurality of pins includes a plurality of differential pin pairs, one or more ground pins, and one or more sideband pins. At least a particular one of the sideband pins is positioned within the pin field immediately between a first pin of a first one of the differential pin pairs and a second pin of a second one of the differential pin pairs, and one or more ground vias positioned to correspond to the particular sideband pin, where the one or more ground vias connect to both the top and bottom ground planes of the baseboard.
One or more embodiments may provide an apparatus, a system, a machine readable storage, a machine readable medium, and a method to provide a connector including a pin field including a plurality of pins, where the plurality of pins includes a plurality of differential pin pairs, one or more ground pins, and one or more sideband pins, where at least a particular one of the sideband pins is positioned within the pin field immediately between a first pin of a first one of the differential pin pairs and a second pin of a second one of the differential pin pairs. The connector can further include a top ground plane, a bottom ground plane, and one or more ground vias positioned within a distance of the particular sideband pin, where the one or more ground vias connect to both the top and bottom ground planes.
In one example, the distance corresponds to a minimum allowed distance from the particular sideband pin.
In one example, the ground vias mitigate against crosstalk appearing on the particular sideband pin during signaling on one or both of the first and second differential pin pairs.
Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
In the foregoing specification, a detailed description has been given with reference to specific exemplary embodiments. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense. Furthermore, the foregoing use of embodiment and other exemplarily language does not necessarily refer to the same embodiment or the same example, but may refer to different and distinct embodiments, as well as potentially the same embodiment.
This application claims benefit to U.S. Provisional Patent Application Ser. No. 62/204,575, filed Aug. 13, 2015 and to U.S. patent application Ser. No. 14/865,220 filed Sep. 25, 2015, the contents of which are incorporated by reference herein in their entirety.
| Number | Date | Country | |
|---|---|---|---|
| 62204575 | Aug 2015 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 14865220 | Sep 2015 | US |
| Child | 16043091 | US |
