Patent Application
20060044173
This application is related to Japanese Patent Application No. 2004-246850 filed on Aug. 26, 2004, whose priority is claimed under 35 USC §119, the disclosure of which is incorporated herein by reference in its entirety.
The present invention relates to a pipelined A/D converter, and more particularly relates to a technology of correcting the output of an A/D converter.
As the stages 11, so-called 1.5-bit stages are typically used (see, for example, a doctoral dissertation by Shingo Hatanaka, “Study of the design of low-voltage, high-precision pipelined A/D converter” (Osaka University, 2002)).
The 1.5-bit stage operates as follows. A state, in which the switch 28 is closed and the capacitors 24 and 25 are each connected at the other end to the input terminal of the analog signal Vin, and a state, in which the switch 28 is opened and the capacitors 24 and 25 are connected at the other end to the output terminal of the operational amplifier 23 and to the output terminal of the D/A converter 22, respectively, are repeated alternately, whereby an analog signal Vout, which is input to the successive stage, is generated.
If the capacity values of the capacitors 24 and 25 are represented by C1 and C2, respectively, the analog input/output characteristics of the 1.5-bit stage are expressed as the following function.
where Vref is the maximum amplitude of the analog signal Vin.
When the capacity value of the feedback capacitor is equal to that of the sampling capacitor, that is, when C1=C2, the analog input/output characteristics of the 1.5-bit stage take desired values. Specifically, the gain of the operational amplifier 23 becomes “2”, and the discontinuity width in the nonlinear portions (i.e., the portions in which Vin=±Vref/4) in the function is Vref, which corresponds to one bit.
However, it is very difficult to make the feedback and sampling capacitors have the same capacity value, so there is actually some difference in capacity value between these capacitors. This capacity value difference results in an error in the gain, thereby causing the analog input/output characteristic of the stage to change. More specifically, when the sampling capacitor has a larger capacity value than the feedback capacitor (i.e., when C1<C2), the discontinuity width becomes greater than one bit. When the sampling capacitor has a smaller capacity value than the feedback capacitor (i.e., when C1>C2), the discontinuity width becomes smaller than one bit.
When the discontinuity width exceeds one bit, a repeat code, a code repeated multiple times, occurs as an output error of the pipelined A/D converter. On the other hand, when the discontinuity width is smaller than one bit, a missing code, a specific code that is not output, occurs. Empirically, correction of a missing code is easier than that of a repeat code. Therefore, in the pipelined A/D converter, the sampling capacitor is preferably smaller in capacity value than the feedback capacitor at least in the first several stages. Nevertheless, the conventional pipelined A/D converter finds difficulty in discriminating which of these capacitors has a larger capacity value and which has a smaller capacity value, and changing them dynamically.
Furthermore, at present it is known that the capacity value difference is the main cause for deterioration of the analog input/output characteristics of the stages and that the elimination of this difference leads to improvements in the INL (integral non-linearity) performance of the pipelined A/D converter. However, in the case of a pipelined A/D converter having a resolution of 12 bits or more, the allowable difference is about 0.04% or less. It is very difficult to correct such a difference within the analog signal range, and difference correction by digital processing is thus required.
In view of the above problems, it is therefore an object of the present invention to provide a pipelined A/D converter in which the type of output error can be controlled. Furthermore, another object of the present invention is to correct, by digital processing, an error in the output of the pipelined A/D converter caused by a difference in capacity value between a feedback capacitor and a sampling capacitor.
In order to achieve the above objects, an inventive pipelined A/D converter includes a plurality of cascade-connected stages, wherein at least one of the stages is a variable. stage that includes: an A/D converter for converting an analog input to the variable stage to digital form; a D/A converter for converting a digital output of the A/D converter to analog form; an operational amplifier; first and second capacitors; and a set of switches for selecting, as a connection state for the first and second capacitors, either a first connection state, in which the first capacitor is used for feedback of the operational amplifier and the second capacitor is used for output sampling of the D/A converter, or a second connection state that is opposite to the first connection state.
In the inventive pipelined A/D converter, it is possible to select which of the first and second capacitors in the variable stage functions as a feedback capacitor and which functions as a sampling capacitor, thereby controlling the type of error occurring in the output of the pipelined A/D converter. For example, when the first and second capacitors are put in the connection state that makes the sampling capacitor have a smaller capacity value than the feedback capacitor, the error in the output of the pipelined A/D converter is a missing code.
The inventive pipelined A/D converter preferably further includes: a digital calculation section for sequentially shifting digital outputs of the respective stages and adding resultant shifted digital values together; an input selecting section for selecting either a normal input signal or a test signal as the analog input to the variable stage; a stage evaluation section for estimating an error in an analog output of the variable stage, the error resulting from a difference in capacity value between the first and second capacitors; a correction value calculation section for calculating a digital correction value for correcting a digital output of the digital calculation section, based on an intermediate output of the digital calculation section and the analog output error estimated by the stage evaluation section; and an output correction section for correcting the digital output of the digital calculation section based on the digital correction value calculated by the correction value calculation section. Preferably, with the test signal being supplied to the variable stage, the stage evaluation section estimates the analog output error based on a difference between digital outputs of the digital calculation section or digital outputs of the output correction section produced when the first and second capacitors in the variable stage are put in the first connection state and when the first and second capacitors in the variable stage are put in the second connection state, respectively.
Then, the stage evaluation section estimates the error in the analog output of the variable stage based on a difference between the digital outputs of the digital calculation section or the digital outputs of the output correction section produced when the first and second capacitors in the variable stage are put in the first and second connection states. By using the difference between the digital outputs, errors caused by the other stages and contained in the digital outputs thereof are canceled out, such that the error of the target variable stage is reflected strongly. It is therefore possible to estimate an error in the analog output of any variable stage, regardless of the presence or absence of errors in the outputs of the other stages, thereby facilitating the error estimation process. The correction value calculation section then calculates the digital correction value based on the estimated analog output error and an intermediate output of the digital calculation section. Based on the digital correction value, the output correction section corrects the digital output of the digital calculation section. Since the intermediate output of the digital calculation section is used to calculate the digital correction value, the latency of the pipelined A/D converter does not deteriorate.
Also, the inventive pipelined A/D converter preferably further includes: an input selecting section for selecting either a normal input signal or a test signal as the analog input to the variable stage; a control section for controlling the set of switches in the variable stage; and a stage evaluation section for determining which of the first and second capacitors in the variable stage has a larger capacity value and which has a smaller capacity value. Preferably, with the test signal being supplied to the variable stage, the stage evaluation section makes the determination about the capacity values based on digital outputs of the pipelined A/D converter produced when the first and second capacitors in the variable stage are put in the first connection state and when the first and second capacitors in the variable stage are put in the second connection state, respectively; and preferably, the control section controls the set of switches in the variable stage, based on a result of the capacity-value determination made by the stage evaluation section, in such a manner that either of the first and second capacitors that has a larger capacity value is used for feedback of the operational amplifier.
Then, the stage evaluation section determines which of the first and second capacitors in the variable stage has a larger capacity value and which has a smaller capacity value, based on the outputs of the pipelined A/D converter produced when the first and second capacitors in the variable stage are put in the first and second connection states. And based on the result of this determination about the capacity values, the control section controls the set of switches in the variable stage in such a manner that either of the first and second capacitors that has a larger capacity value is used for feedback of the operational amplifier. As a result, the error in the output of the pipelined A/D converter is a missing code.
Moreover, in the inventive pipelined A/D converter, the test signal is preferably at a level that makes the level of analog input/output for stages successive to the variable stage into which the test signal is input be about a median value of a maximum amplitude of the analog input/output.
An inventive method for correcting an error in an output of the pipelined A/D converter includes: an input selecting step of selecting which signal is input to the variable stage; a connection state selecting step of performing switching between the first and second connection states for the first and second capacitors in the variable stage, with a test signal selected in the input selecting step being supplied to the variable stage; an error estimation step of estimating an error in an analog output of the variable stage caused by a difference in capacity value between the first and second capacitors, based on a difference between outputs of the pipelined A/D converter produced when the first and second capacitors are put in the first connection state and when the first and second capacitors are put in the second connection state, respectively, in the connection state selecting step; a correction value calculation step of calculating a digital correction value for correcting an output of the digital calculation section, based on an intermediate output of the digital calculation section and the analog output error estimated in the error estimation step; and an output correction step of correcting the digital output of the digital calculation section based on the digital correction value calculated in the correction value calculation step.
Then, in the error estimation step, an error in the analog output of the variable stage is estimated based on a difference between the digital outputs of the digital calculation section or the digital outputs of the output correction section produced when the first and second capacitors in the variable stage are put in the first and second connection states. By using the difference between the digital outputs, errors caused by the other stages and contained in the digital outputs thereof are canceled out, such that the error of the target variable stage is reflected strongly. It is therefore possible to estimate an error in the analog output of any variable stage, regardless of the presence or absence of errors in the outputs of the other stages, thereby facilitating the error estimation process. In the correction value calculation step, the digital correction value is calculated based on the estimated analog output error and an intermediate output of the digital calculation section. Then, in the output correction step, the digital output of the digital calculation section is corrected based on the digital correction value. Since the intermediate output of the digital calculation section is used in calculating the digital correction value, the latency of the pipelined A/D converter does not deteriorate.
As described above, according to the present invention, it is possible to control the type of error in the output of the pipelined A/D converter so that a missing code, which can be corrected relatively easily, occurs as an error in the output. Also, for correction of the output of the pipelined A/D converter, a digital correction value is calculated relatively easily for any variable stage. Furthermore, the INL performance of the pipelined A/D converter is improved without causing the latency of the pipelined A/D converter to deteriorate.
Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.
The switch 26A, controlled by the control section 13, switches among the input terminal of the analog signal Vin, the output terminal of the operational amplifier 23, and the output terminal of the D/A converter 22, so that the other end of the capacitor 24 is connected to one of these terminals. Similarly, the switch 27A, controlled by the control section 13, switches among the input terminal of the analog signal Vin, the output terminal of the operational amplifier 23, and the output terminal of the D/A converter 22, so that the other end of the capacitor 25 is connected to one of these terminals. The switch 28, controlled by the control section, opens/closes the circuit between the inverting input terminal and the output terminal of the operational amplifier 23.
The switches 26A, 27A, and 28 provide the following two connection states for the capacitors 24 and 25. In the first connection state, the capacitor 24 is used for feedback of the operational amplifier 23, while the capacitor 25 is used for output sampling of the D/A converter 22. In the second connection state, the capacitor 24 is used for output sampling of the D/A converter 22, while the capacitor 25 is used for feedback of the operational amplifier 23. More specifically, in the first connection state, a state, in which the switch 28 is closed and the capacitors 24 and 25 are each connected at the other end to the input terminal of the analog signal Vin, and a state, in which the switch 28 is opened and the capacitors 24 and 25 are connected at the other end to the output terminal of the operational amplifier 23 and to the output terminal of the D/A converter 22, respectively, are repeated alternately. On the other hand, in the second connection state, a state, in which the switch 28 is closed and the capacitors 24 and 25 are each connected at the other end to the input terminal of the analog signal Vin, and a state, in which the switch 28 is opened and the capacitors 24 and 25 are connected at the other end to the output terminal of the D/A converter 22 and to the output terminal of the operational amplifier 23, respectively, are repeated alternately. The selection between the first and second connection states is made under the control of the control section 13. In this manner, in the variable stages 11A the functions of the capacitors 24 and 25 can be switched under the control of the control section 13.
It should be noted that the configurations of the switches 26A, 27A, and 28 shown in
Referring back to
The input selecting sections 14 are provided corresponding to the variable stages 11A, and select, under the control of the control section 13, which signal is input to the corresponding variable stage 11A. Specifically, each input selecting section 14 selects a normal input signal or a test signal. In this embodiment, for the initial variable stage 11A, the normal input signal is an analog input to the pipelined A/D converter, while for the second and successive variable stages 11A, the normal input signal is the analog output from the variable stage 11A prior to that stage. On the other hand, the test signal is an analog signal having a given size. The test signal may be generated by a not-shown D/A converter or the like.
The stage evaluation section 15 estimates an error in the analog output of each variable stage 11A based on the digital output of the output correction section 17. Hereinafter, an error in the analog output of the variable stage 11A will be discussed. When the feedback capacitor and the sampling capacitor in the variable stage 11A have the same capacity value, the error in the analog output of the variable stage 11A will be zero. However, as described above, there is actually a difference between the capacity values of these two capacitors. For example, when the feedback capacitor has a larger capacity value than the sampling capacitor, error characteristics such as shown in
More specifically, the characteristic value is estimated as follows. First, with a test signal being input to a variable stage 11A whose characteristic value is to be estimated (an object variable stage 11A), the digital output of the pipelined A/D converter, in which the capacitors 24 and 25 in the object variable stage 11A are put in the first connection state, is obtained. Next, the digital output of the pipelined A/D converter, in which the capacitors 24 and 25 in the object variable stage 11A are put in the second connection state, is obtained. The difference between these digital outputs is then calculated. The magnitude of this difference corresponds to a difference in capacity value between the feedback capacitor and the sampling capacitor. It is therefore possible to estimate the characteristic value of the object variable stage 11A from this difference between the digital outputs. By calculating the difference between the digital outputs of the pipelined A/D converter obtained when the capacitors 24 and 25 are in the first and second connection states, errors in the digital outputs of the stages 11 and variable stages 11A whose characteristic values are not to be estimated (non-object stages) are cancelled out. That is, by eliminating the effects of the errors in the outputs of the non-object stages, it becomes possible to estimate the characteristic value more precisely for any variable stage 11A.
It is preferable that the difference-calculation step mentioned above be repeated multiple times (about a hundred times, for example) and that the characteristic value estimation be performed based on the multiple differences obtained by the repeated calculation steps. For example, those multiple differences are added together and the characteristic value may be estimated based on the resultant total value. This is because noise may be superimposed on the digital output of the pipelined A/D converter, and if the number of difference-calculation steps repeated is small, the characteristic value may not be estimated accurately.
Also, when the input analog signal varies in the range from −Vref to +Vref, that is, when the maximum amplitude is Vref, a value close to ±Vref/2 (i.e., a value equal to +Vref/2 or a value within a range of about +100 mV of ±Vref/2) is preferably selected as the test signal value. In other words, the test signal is preferably at a level that makes the analog input/output level for the stages successive to the variable stage 11A into which the test signal is input be about the median value of the maximum amplitude thereof. For instance, in the above example, if the input level is set at about ±Vref/2, the output level will be close to zero (see
The above-mentioned process steps for estimating the characteristic value of the variable stage 11A will be described with reference to a flow chart shown in
Referring back to
The correction value calculation sections 16, which are provided corresponding to the variable stages 11A, each imitate the output error characteristics of the corresponding variable stage 11A based on a characteristic value estimated by the stage evaluation section 15. Each correction value calculation section 16 receives an output from the digital calculation section 12 and outputs an error in the digital output of the corresponding variable stage 11A as the digital correction value. This corresponds to a correction value calculation step. Since the digital correction value calculation can be performed well based on a digital output having a relatively low resolution, each correction value calculation section 16 calculates the digital correction value based on an intermediate output from the digital calculation section 12. The digital calculation section 12 includes digital calculation cores 121 corresponding to the respective stages. Each digital calculation core 121 adds the digital output of the corresponding stage to a digital value obtained by shifting the digital output of the stage prior to that corresponding stage by one bit. The correction value calculation sections 16 each receive a value output from the corresponding digital calculation core 121 as the intermediate output of the digital calculation section 12. Since the digital correction values output from the respective correction value calculation sections 16 are subjected at a time to arithmetic processing performed by the output correction section 17, delay devices 18 are provided as necessary so as to make the intermediate outputs be received by the correction value calculation sections 16 at a time.
In this embodiment as described above, for each of the variable stages 11A, an error in output, occurring due to a difference in capacity value between the feedback and sample capacitors in the variable stage 11A, is estimated, and a digital correction value is calculated based on the estimated error. With the digital correction values obtained in this manner, the digital output of the pipelined A/D converter is corrected. In estimating the output error for each variable stage 11A, output errors with respect to the other stages, particularly, later stages, do not have to be eliminated in advance, thereby facilitating the output error estimation process. Moreover, since the intermediate outputs of the digital calculation section 12 are used in calculating the digital correction values, the latency of the pipelined A/D converter does not deteriorate.
It should be noted that the correction value calculation sections 16 may be designed so as to imitate reversed-polarity output error characteristics for the corresponding variable stage 11A. In that case, the output correction section 17 adds the digital correction values output from the correction value calculation sections 16 to the digital output of the digital calculation section 12.
It should be also noted that the stage evaluation section 15 may be designed so as to estimate the characteristic value of each variable stage 11A based on the digital output of the digital calculation section 12, instead of based on the digital output of the output correction section 17. This is because errors in the outputs of the stages other than the stage whose characteristic value is estimated are canceled out by calculating a difference between the digital outputs of the digital calculation section 12.
The stage evaluation section 15A determines, for each variable stage 11A, which is the greater and which is the smaller in capacity value, the feedback capacitor or the sampling capacitor, based on the digital output of the digital calculation section 12. The configuration of each variable stage 11A is similar to that described in the first embodiment, and
More specifically, which capacitor has a greater capacity value and which has a smaller capacity value is determined as follows. First, with a test signal being input to an object variable stage 11A, the digital output of the pipelined A/D converter, in which the capacitors 24 and 25 in the object variable stage 11A are put in the first connection state, is obtained. Next, the digital output of the pipelined A/D converter, in which the capacitors 24 and 25 in the object variable stage 11A are put in the second connection state, is obtained. Based on the relationship between these two digital outputs in terms of magnitude, which of the capacitors 24 and 25 has a greater capacity value and which has a smaller capacity value is determined.
The control section 13A changes the connection state of the capacitors 24 and 25 in each variable stage 11A under the control of the stage evaluation section 15A. More specifically, the control section 13A controls the set of switches in each variable stage 11A in such a manner that one of the capacitors 24 and 25 that has a larger capacity value is used as the feedback capacitor.
As described above, in this embodiment, the sampling capacitor is smaller in capacity value than the feedback capacitor in each variable stage 11A, such that an error in the output of the pipelined A/D converter is a missing code that can be corrected relatively easily.
The preferable level of the test signal is the same as described in the first embodiment. Also, as in the first embodiment, it is preferable that the comparison of the digital outputs of the pipelined A/D converter be repeated multiple times for the same variable stage 11A.
Although the foregoing describes the embodiments of the present invention, the present invention is not limited to a pipelined A/D converter that includes 1.5-bit stages. According to the present invention, the above-described effects are achieved in a pipelined A/D converter that includes 2.5-bit stages or other stages.
As described above, the inventive pipelined A/D converters, which are capable of high-speed, high-resolution A/D conversion and have excellent INL performance, are applicable, e.g., as front end portions of digital still cameras or the like that are required to have all of these features.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2004-246850 | Aug 2004 | JP | national |
