Pipelined residue to mixed base converter and base extension processor

Abstract

An information processor receives a residue number as an input and generates a mixed base number correspopnding to the residue number and a redundant residue digit corresponding to the residue number. The information processor includes a plurality of optical arithmetic and logic units (OALUs) arranged in channels and stages. Each digit of the residue number corresponds to a channel. Each channel produces a mixed base digit associated with the residue input number. The stages are serially arranged to successively generate mixed base digits corresponding to the residue number by performing modular multiplication and modular subtraction. Delay circuits are arranged parallel to the plurality of OALUs such that all of the mixed base digits are transmitted from the information processor at the same time. An additional channel of OALUs calculates the redundant residue digit based on the mixed base digits.

Description

BACKGROUND OF THE INVENTION

The invention is in the field of information processing. Specifically, the invention relates to conversion from residue number system (RNS) representations of data to mixed base number system representations of data and to extending the base of RNS numbers.

The RNS has received considerable attention in recent times as an effective tool for performing single step, parallel computation of sums, differences, and products. A system employing the RNS may be used for high speed, real time, parallel processing of data.

A difficulty associated with actually achieving fast computation with the RNS is that a RNS representation of a number does not provide explicit sign and magnitude information. The lack of explicit sign and magnitude information hinders overflow detection and rescaling. The capability to detect overflow is a fundamental requirement of any general purpose computer. A slow overflow detection system slows the speed of the entire computational process.

Residue Arithmetic and Its Application to Computer Technology, N.S. Szabo and R.I. Tanaka, (McGraw Hill, New York, 1967), "Residue Arithmetic: A Tutorial with Examples," F.J. Taylor Computer Vol. 17, No. 5, pp. 50-62 (May 1984), and U.S. Pat. No. 4,797,843 issued to Falk et al on Jan. 10, 1989, all incorporated by reference, provide general background information on the RNS and the mixed base number system.

Optical information processors which are ideally suited to perform the parallel computations required in RNS arithmetic are currently under development. There are fundamental differences between optical processors based on optical circuits in which the information carriers are photons and electronic processors based on electronic circuits in which the information carriers are electrons. In optical circuits the photon carriers do not interact with one another, while in electronic circuits the electron carriers do interact with one another. This fact means that in optical circuits interconnect possibilities exist that do not exist with electronic circuits. In particular, optical circuits allow parallel architectures which perform arithmetic and logical operations in completely parallel, single step processes. Since the speed of optical devices is essentially limited to the time it takes for a photon to transit a device, no faster computation time is possible.

Co-pending application 07/414,475, filed Sep. 29, 1989 entitled "Residue Addition Overflow Detection Processor" by T.L. Houk filed concurrently herewith and incorporated herein by reference, discloses a high speed RNS addition overflow detection processor. The residue addition overflow detection processor disclosed in this copending application requires a high speed base extension circuit and a high speed residue to mixed base converter. This application describes a pipelined residue to mixed base converter and base extension processor suitable for use in the residue addition overflow detection processor cited above.

Co-pending application 07/414,474, filed Sep. 29, 1989 entitled "Parallel Residue to Mixed Base Converter" by R.A. Falk also discloses a residue to mixed base converter suitable for use in the residue addition overflow detection processor cited above. The mixed base converters of the "Parallel Residue to Mixed Base Converter" copending application and the instant application are complementary. The mixed base converter of the "Parallel Residue to Mixed Base Converter" copending application performs conversion in a single step; however, it requires more hardware than the instant invention. The instant invention requires less hardware than the converter of the "Parallel Residue to Mixed Base Converter" co-pending application, although the instant invention requires several processing steps. Accordingly, the instant invention would be employed where hardware minimization is a major concern, whereas the converter of the "Parallel Residue to Mixed Base Converter" co-pending application could be employed where minimization of operational time is paramount.

U.S. Pat. No. 4,752,904 issued to Paul, No. 4,709,345 issued to Vu, No. 4,528,641 issued to Burrows, and No. 4,281,391 issued to Huang disclose residue to mixed base converters which use ROMs (read only memory) and latches, adders, or complex processors to implement the conversion process. The inventions disclosed in these patents require complex hardware, and are thus unsuitable for many applications.

Accordingly, there is a need for a simple and high speed base extension processor and for a residue to mixed base converter which requires a minimum of complex hardware.

SUMMARY OF THE INVENTION

It is an object of the invention, therefore, to provide a simple and high spaced base extension processor.

Another object of the invention is to provide a residue to mixed base converter which requires a minimum of complex hardware.

Another object of the invention is to provide a base extension processor and a pipelined residue to mixed base converter which uses optical technologies to realize an efficient processor and converter, and which can be efficiently used in conjunction with other optical processing elements.

According to a first aspect of the invention there is provided an information processor which receives a residue number as an input. The information processor includes a plurality of optical arithmetic and logic units (OALUs) arranged in channels and stages. Each digit of the residue input number corresponds to a channel which produces a mixed base digit associated with the residue input number. The stages are serially arranged to successively generate mixed base digits corresponding to the residue number by performing modular multiplication and modular subtraction. The information processor can also include delay circuits arranged parallel to the plurality of OALUs so that all of the mixed base digits are transmitted from the information processor at essentially the same time. The mixed base digits can also be used to generate a redundant residue digit in a separate channel.

According to a second aspect of the invention, there is provided an information processor which receives a residue number as an input. This information processor includes a plurality of arithmetic units arranged in a plurality of stages. Odd stages of the plurality of stages perform first arithmetic operations in parallel. Even stages of the plurality of stages perform second arithmetic operations in parallel. The odd and even stages alternately perform the first operations and second operations to generate at least one mixed base digit corresponding to the residue number. The at least one mixed base digit can also be used to generate a redundant residue digit.

According to a third aspect of the invention there is provided a method of processing a residue input number to generate mixed base digits corresponding to the residue input number. In this method, the residue input number is received and then a first digit of the residue input number is subtracted from other digits of the residue input number. In parallel with this subtracting, the first digit of the residue input number is delayed in time. Then, each of the other digits of the residue input number is multiplied by multiplicative inverses to produce a signal indicative of a second mixed base digit. In parallel with this multiplying, the signal representing the first digit of the residue input number is delayed in time. The second mixed base digit can be used to generate a redundant residue digit.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is described below with reference to the accompanying drawings, wherein:

FIG. 1 is a table illustrating decimal, residue, and mixed base representations of the decimal numbers 0 through 29;

FIG. 2 illustrates an example of overflow occurring in RNS addition;

FIG. 3 is a table which lists multiplicative inverses of decimal numbers 1, 2, 3, and 4;

FIG. 4 illustrates the RNS ring associated with FIGS. 1 and 2;

FIG. 5 illustrates a numerical example;

FIG. 6 is a table illustrating decimal, residue, and mixed base representations of the decimal numbers -15 to 14;

FIG. 7 illustrates the RNS ring associated with FIG. 6;

FIG. 8 is a table illustrating decimal, residue, and mixed base representations of the decimal numbers -15 to 14 in which the third mixed base digit indicates the sign of the number;

FIG. 9 is a table illustrating decimal, residue, and mixed base representations of the decimal numbers 0 to 40 with a redundant modulus of 7;

FIG. 10 illustrates a numerical example;

FIG. 11 illustrates a numerical example;

FIG. 12 illustrates a pipelined residue to mixed base converter and base extension processor according to a first preferred embodiment;

FIG. 13 illustrates a Fourier transform pattern recognition OALU configured as an adder;

FIG. 14 illustrates a Fourier transform pattern recognition OALU configured as a multiplier;

FIG. 15 illustrates an RNS ring representing positive and negative values;

FIG. 16 lists values corresponding to the FIG. 15 ring;

FIG. 17 illustrates a pipelined residue to mixed base converter and base extension processor according to a second preferred embodiment;

FIG. 18 illustrates a pipelined residue to mixed base converter and base extension processor according to a third preferred embodiment;

FIG. 19 illustrates a pipelined residue to mixed base converter and base extension processor according to a fourth preferred embodiment;

FIG. 20 illustrates a residue addition overflow detection processor which utilizes a residue to mixed base converter and base extension processors of the instant invention;

FIG. 21 illustrates a numerical example; and

FIG. 22 illustrates a numerical example.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Residue and Mixed Base Number Theory

An integer is represented in the RNS by writing down an n-tuple where the i.sup.th digit is the remainder, r.sub.i, after division of the integer by an associated modulus, m.sub.1. FIG. 1 lists RNS representations of the decimal numbers 0 to 29, when the moduli are 2, 3, and 5. For example, the decimal number 7 is represented as 211 in RNS representation. If the moduli are chosen to be mutually prime, then all integers within the range of zero to the product of the moduli minus one can be uniquely represented.

The importance of the residue number system to numerical processing is that the operations of addition, subtraction, and multiplication can be performed without the use of carry operations between the moduli. In other words, each digit in the n-tuple can be operated on independently and in parallel. For example, if n-tuples X, having digits x.sub.1 ... x.sub.n, and y, having digits y.sub.1 ... y.sub.n, are added to produce Z, having digits z.sub.1 ... z.sub.n, then the i.sup.th digit is given by:

z.sub.i =(X.sub.i +Y.sub.i) mod m.sub.i ; (1)

The mod function takes the number in front of "mod," in this case x.sub.i + y.sub.i, divides this number by the number after "mod," in this case m.sub.i, and substitutes the remainder for the entire function. Equation (1) may also be expressed in shorthand notation as:

Z.sub.i =.vertline.X.sub.i +Y.sub.i .vertline.m.sub.i (2)

In a similar fashion, in RNS multiplication the product of x.sub.i and y.sub.i, x.sub.i .multidot. y.sub.i, is divided by m and the remainder is substituted for the entire function.

The power of RNS representation is that an operation on large numbers can be broken down into small parallel modular operations. For example, a 16 bit binary number can be represented in RNS using the five moduli 5, 7, 11, 13 and 17. Multiplication of two 16 bit binary numbers produces a 32 bit intermediate result and requires 31 carry operations. In contrast, modular arithmetic devices can perform the same multiplication operation in one step per modulus, all steps being performed simultaneously in parallel.

The high speed potential of RNS arithmetic may be effectively exploited by optical computers that excel at parallel operations. Optical computers making use of RNS arithmetic promise at least an order of magnitude improvement in computational speed over standard electronic, binary computers.

A difficulty with RNS representation is that magnitude comparisons can not be determined by a simple one-to-one digit comparison. For example, as seen from FIG. 1, in RNS representation the decimal number 16 which is represented in RNS representation as 110, appears smaller than the decimal number 8, which is represented in RNS representation as 320.

Another difficulty associated with RNS representation is that the occurrence of overflow resulting from addition operations can not be readily detected. For example, if the decimal number 18, which is represented in RNS representation as 300, is added to decimal number 19, which is represented in RNS representation as 411, the RNS result would be 211, as illustrated in FIG. 2. In the range 0-29, the RNS representation 211 corresponds to decimal number 7. There is no way to determine by inspection that overflow has occurred and that the correct sum is not 7. In order to implement a general purpose computer, overflow detection is required.

The multiplicative inverse is useful in solving equations in the RNS. The number a is the multiplicative inverse of b mod m if 0 > a > m and .vertline. a.multidot.b .vertline. .sub.m = 1.=1. The multiplicative inverse a is denoted as ##EQU1## FIG. 3 lists the multiplicative inverses of 1, 2, 3, and 4 where m is equal to five. In the general case there is no convenient explicit expression for obtaining the multiplicative inverse of a number. However, if m is a prime number, the multiplicative inverse may be obtained by Fermat's Theorem. Detailed theory concerning the r multiplicative inverse and Fermat's Theorem is discussed in the Szabo and Tanaka text cited above. The implementation of the multiplicative inverse operation in the invention will be described in further detail in connection with the hardware description.

RNS representation and addition overflow can be illustrated by visualizing RNS representation as a ring such as depicted in FIG. 4. It is this periodic or ring property which complicates overflow detection in the RNS representation. If RNS representation is to be unambiguous in computation, a computational system must be implicitly restricted to a single range. There are only a finite number of positions in the RNS ring. In the example illustrated in FIG. 4, there are 30 finite positions. If each of these positions is occupied by one number within the range, the RNS forms a nonredundant ring. A redundant RNS has more positions on the ring than unique members to be represented.

If two large numbers within the range are added, for example decimal 18 and decimal 19, the sum will be an overflow number which also corresponds to a number within the range, for example decimal number 7, represented in RNS as 211. A number within the predefined range is said to be "valid" while a number outside the predefined range is said to be "invalid." An analogous situation occurs in binary computers of fixed word length.

One method of obtaining overflow information requires mixed base representations of the arithmetic operands. Thus, in order to detect overflow an efficient mixed base converter is required. While the mixed base converter described in this application will be described with respect to its use in an overflow detection processor, by way of example, it is understood that the mixed base converter described in this application can be used in other applications where mixed base conversion is required.

A number X may be expressed in mixed base form according to the following equations: ##EQU2##

The terms w.sub.1, ... , w.sub.j are the bases and are related to the moduli of an associated RNS representation according to Equation (4). The terms a.sub.1, ... , a.sub.n are the mixed base digits.

Any positive integer in the interval ##EQU3## may be represented in accordance with equation (5), and each integer has a unique representation. FIG. 1 lists the mixed base digits for decimal numbers 0 through 29. In FIG. 1, w.sub.1 is 1, w.sub.2 is the modulus 2, and w.sub.3 is 6, the product of the modulus 2 and the modulus 3. Thus the decimal number 10 is represented as 120, where a.sub.1 is O, a.sub.2 is 2, and a.sub.3 is 1. Decimal numbers may be expressed in the form of Equation (3) by choosing w.sub.1 equal to 1, w.sub.2 equal to 10, w.sub.3 equal to 100, and so on. Binary numbers may be expressed in the form of Equation (3) by choosing w.sub.1 equal to 1, w.sub.2 equal to 2, w.sub.3 equal to 4, and so on.

A mixed base system can be arranged such that:

a.sub.j < m.sub.j (6) resulting in the property that: ##EQU4##

The arrangement of Equation (6) results in an ordered sequencing of the mixed base digits. As can be seen from Equation (7), this ordered sequencing allows direct magnitude determination by a comparison of the digits. For example, the mixed base number 220, decimal number 16, can be readily determined to be greater than the mixed base number 110, decimal number 8, since the most significant digit of 220 is greater than the most significant digit of 110.

Mixed base digits a.sub.1 , ... , a.sub.n may be computed by performing sequential operations on equation (5). Equation (5) is first taken modulo m.sub.1. Since all terms except the last term are multiples of m.sub.1, Equation (5) becomes:

X mod m.sub.1 = a.sub.1 mod m.sub.1 (8)

Since a.sub.1 <m.sub.1 in accordance with equation (6), a.sub.1 mod m.sub.1 = a.sub.1 and therefore:

X mod m.sub.1 = a.sub.1 (9)

Hence, the least significant mixed base digit a.sub.1 equals the first residue digit X mod m.sub.1, or r.sub.1. TO find r.sub.2, the next most significant digit, a.sub.1 is subtracted from both sides of Equation (5), both sides of the equation are divided by m.sub.1 and then the equation is taken modulo m.sub.2. These manipulations result in:

[(X-a.sub.1)/m.sub.1 ]mod m.sub.2 = a.sub.2 (10)

The Division Remainder Zero Theorem developed in the Szabo and Tanaka text, cited above, states that given two numbers or expressions, b and c, the following property holds ##EQU5##

By using Equation (11) with b equal to (X-a.sub.1) and c equal to m.sub.1, Equation (10) becomes: ##EQU6##

This process is repeated by performing successive subtraction and division steps in RNS until all mixed base digits, including any redundant mixed base digits are calculated. A numerical example illustrating use of Equations (11) and (12) is given in FIG. 5 where r.sub.1 = 1, r.sub.2 = 4, and r.sub.3 = 1, 1, and where m.sub.1 = 3, m.sub.2 = 5, and m.sub.3 = 2. In FIG. 5, steps for different moduli are carried out in parallel. For example, steps 4a, 4b, and 4c are carried out in parallel. FIG. 5 shows that residue digits r.sub.1 = 1, r.sub.2 = 4, and r.sub.3 = 1 correspond to mixed base digits a.sub.1 = 1, a.sub.2 = 1, and a.sub.3 = 1. The residue number r.sub.1 = 1, r.sub.2 = 4, and r.sub.3 = 1 and the mixed base number a.sub.1 = 1, a.sub.2 = 1 and a.sub.3 =1 correspond to decimal 19 using these moduli.

The RNS to mixed base procedures described above can be used to convert from RNS to decimal representation, for human scrutiny, or to binary representation for electronic computer usage. Conversion to decimal or binary is performed by converting the RNS digits into mixed base digits and then inserting the mixed base digits into Equation (5), representing the mixed base digits and their bases in decimal or binary, respectively, then calculating X. If the computation of X were done in RNS arithmetic, an arithmetic and logic unit the size of the product of the moduli would be required. Such an arithmetic and logic unit would be prohibitively large. By converting a number from RNS to a mixed base binary or decimal representation and then calculating X in accordance with Equation (5), the need for a large arithmetic and logic unit is eliminated.

One consequence of converting from RNS to mixed base representation is that time delays associated with carry propagation in the mixed base conversion process will result in the decimal or binary representations being calculated after RNS calculations have been completed. Thus only a fraction of the numbers being processed by an RNS based processor can be converted into decimal or binary representations without becoming a bottleneck.

Negative numbers may also be implicitly represented in RNS representation For example, FIG. 6 illustrates how the integers from -15 to 14 may be represented in RNS form. FIG. 7 illustrates the ring corresponding to FIG. 6.

Although RNS arithmetic involving negative numbers can be performed by forming a correspondence table between the negative numbers and associated positive numbers and performing intermediate computation using positive number RNS, it is frequently more useful to treat negative-and-positive-number RNS in a more direct fashion, as illustrated in FIG. 8. In FIG. 8, the order of the RNS digits is arranged such that the m.sub.3 modulus is 2. The other moduli, 5 and 3, are arranged in descending order from left to right as m.sub.2 and m.sub.1 respectively. The mixed base weights for this new order is computed in accordance with equation (4) and mixed base digits a.sub.3, a.sub.2, and a.sub.1 are tabulated in FIG. 8. FIG. 8 shows that a.sub.3 can be used to determine whether an associated RNS number is positive or negative. That is, a.sub.3 is O for all non-negative numbers and 1 for all negative numbers. FIG. 8 is analogous to the two's complement binary representation in which numbers with 1 as the most significant bit are negative and in which the most negative number immediately follows the most positive number.

A non-redundant RNS can be made redundant by the use of an additional, redundant modulus m.sub.r. The addition of one or more moduli to a RNS is called extension of the base. The base extension processor generates the residue digit or digits corresponding to the redundant modulus or moduli using the nonredundant residue digits.

An addition overflow detection processor which employs an additional modulus enlarges the ring to a size to which overflow could not occur, performs the addition, and determines whether or not the sum is within the valid range of the original non-redundant ring. Thus, an efficient base extension processor is required for overflow detection processors. While the base extension processor described in this application will be described with respect to its use in an addition overflow detection processor by way of example, it is understood that the base extension processor of the instant application can be used in other applications where base extension is required, for example, a multiplication overflow processor. Several numerical examples will be discussed first in order to better understand the hardware descriptions below.

A new modulus m.sub.r =7 is used in conjunction with m.sub.3 =5, m.sub.2 =3, and m.sub.1 =. A new modulus of 7 is chosen because 7 is prime relative to the other modulus. Choosing a relative prime additional modulus ensures that mixed base digit computations and base extension, to be discussed further below, are possible.

The new redundant RNS, in the illustrative example, has moduli of 7, 5, 3, and 2 and a ring circumference M.sub.r of the product of 2, 3, 5, and 7, or 210. Representations are valid in the range 0 to 29 inclusive and invalid in the range 30 to 209 inclusive. Validity can be determined by converting a number from RNS representation into mixed base representation and examining the fourth mixed base digit a.sub.r (or alternatively a.sub.4). This fourth mixed base digit a.sub.r is zero for valid numbers and non-zero for invalid numbers as illustrated in FIG. 9. The use of the a.sub.r digit as a validity indicator, and thus an overflow indicator, can be understood from an examination of Equation (4). Since the base w.sub.4 associated with the redundant fourth digit a.sub.r is the product of m.sub.1, m.sub.2, and m.sub.3, the base w.sub.4 is equal to 2.multidot.3.multidot.5, or 30. Therefore, a.sub.r will have a non-zero number when the number to be represented is in the invalid range greater than 29.

The general form of the mixed base expansion resulting from the use of a redundant modulus is: ##EQU7## Or alternatively:

X = a.sub.r M +...+ a.sub.1 (14) where M is the circumference of the non-redundant ring and is calculated in accordance with the following equation: ##EQU8## The examples described herein will use only one redundant modulus. However, it is understood that more than one redundant modulus can be added by simply repeating the base extension process.

FIG. 10 illustrates a numerical example of how a.sub.r (or alternatively a.sub.4) can be calculated in terms of the multiplicative inverses of the moduli

and in terms of the redundant residue digit .vertline.X.vertline..sub.7 using the mixed base conversion procedure described above. In FIG. 10, positive numbers are carried through the process by adding instead of subtracting. For example, in step 4d, 6 is added to .vertline.X.vertline..sub.7 rather than substracting 1. Since step 4d is associated with a modulus of 7, adding 6 has the same effect as subtracting 1. The number 6 is called the additive inverse of 1 when the modulus is 7.

Since a.sub.r is equal to zero for X to be valid, the expression obtained in step 14 of FIG. 10 for a.sub.r (or alternatively a.sub.4) can be set equal to zero and solved for .vertline.X.vertline..sub.7. The value of .vertline.X.vertline..sub.7 is the redundant residue digit which results from the use of an additional redundant modulus. The redundant mixed base digit a.sub.r is set equal to zero as follows: ##EQU9## For Equation (16) to be true the following Equation must be true: ##EQU10## Solving Equation (17) for .vertline.X.vertline..sub.7 results in .vertline.X.vertline..sub.7 being equal to 5 as follows: ##EQU11##

The procedure illustrated in FIG. 10 can be simplified by noting that the divisor of .vertline.X.vertline..sub.7 in Equation (16) is the non-redundant ring q circumference M, that is, m.sub.1 .multidot.m.sub.2 .multidot.m.sub.3 or 3.multidot.5.multidot.2.

Further, the division by ##EQU12## is unnecessary since this term cancels out in manipulating Equation (16) into Equation (17). Therefore only the additive terms, i.e., the "2" term in steps 12 and 14 of FIG. 10 and in Equations (16)-(21) need be carried through the process as illustrated in FIG. 11.

The simplified process is illustrated in FIG. 11. FIG. 11 illustrates the same process as illustrated in FIG. 10 but with the simplification discussed above. In FIG. 11, step 2d, .vertline.X.vertline..sub.7 is arbitrarily assumed to be zero. While .vertline.X.vertline..sub.7 is not necessarily zero, this arbitrary assumption is permissible since only the additive term is used to calculate a final result. The general simplified form of .vertline.X.vertline. m.sub.r, the redundant residue digit, is given by the following equation: ##EQU13## where N is the order of the most significant nonredundant modulus;

r is the order of the redundant modulus; and

S is the additive term carried through the conversion process.

Equations 22 and 18 may be compared to verify that Equation 18 fits the general form of Equation 22.

The range of numbers being represented in a RNS is implicit in the residue to mixed base conversion process described above with respect to FIG. 5.

For example, if residue digits r.sub.1 = 1, r.sub.2 = 1, and r.sub.3 = 4 corresponding to moduli of m.sub.1 = 2, m.sub.2 = 3, and m.sub.3 = 5 are processed as discussed above, the resulting mixed base digits a.sub.1 = 1, a.sub.2 = 0, and a.sub.3 = 3 correspond to decimal 19. However, as illustrated in FIG. 6, residue digits r.sub.1 = 1, r.sub.2 = 1, and r.sub.3 = 4 could correspond to decimal -11 in negative-and-positive residue representation.

Converter and Processor Hardware

FIG. 12 illustrates a pipelined residue to mixed base converter and base extension processor 100 according to a first preferred embodiment of the invention. The converter/processor 100 illustrated in FIG. 12 receives residue input digits r.sub.1, r.sub.2, and r.sub.3, representing number X, and outputs mixed base digits a.sub.1, a.sub.2, and a.sub.3 representing number X, and .vertline.X.vertline. m.sub.4, the redundant residue digit corresponding to a modulus of m.sub.4.

The converter/processor 100 can be used in conjunction with optical processing systems such as those disclosed in U.S. Pat. No. 4,797,843 issued Jan. 10, 1989, entitled "Parallel Optical Arithmetic/Logic Unit;" and in copending applications Ser. No. 07/019,761, filed Feb. 27, 1987, entitled "Optical Cross Bar Arithmetic/ Logic Unit;" Ser. No. 07/219,392, filed July 15, 1988, entitled "Optical Computer Including Pipelined Conversion of Numbers to Residue Representation;" and Ser. No. 07/233,610, filed Aug. 18, 1988, entitled "Optical Computer Including Parallel Residue to Binary Conversion;" all incorporated herein by reference.

The converter/processor 100 is a pipelined processor, which means that all numbers in a computational stream are given the same algorithmic treatment. Output numbers appear at the same rate as input numbers are fed into the converter/ processor 100. A constant time delay exists between receipt of an input number and transmission of its associated output number.

The converter/processor 100 receives residue input digit r.sub.1 via optical signal line 51, r.sub.2 via optical signal line 52, and r.sub.3 via optical signal line 53. Each of signal lines 51, 52 and 53 includes individual signal lines to transmit an input digit in a one-of-many format For example, if r.sub.1 corresponds to a modulus of m.sub.1 = 3, then signal line 51 includes three individual signal lines only one of which is active at any given time. If a first individual signal line is active then r.sub.1 is 0, if a second individual signal line is active then r.sub.1 is 1, and if a third individual signal line is active then r.sub.1 is 2.

Residue input digit r.sub.1 is supplied to a delay circuit 10, and adders 30, 31 and 32 via signal line 51. Residue input digit r.sub.2 is supplied to adder 30 via signal line 52. Residue input digit r.sub.3 is supplied to adder 31 via signal line 53. The adder 32 also receives a 0 input via a signal line 54. Processing in the delay circuit 10, the adder 30, the adder 31, and the adder 32 occurs in parallel.

Since r.sub.1 is the first mixed base digit, a.sub.1, r.sub.1 is maintained in synchronism with the first stage of processing occurring in adders 30, 31 and 32 so that r.sub.1 is available as a.sub.1. The delay circuit 10 is designed to delay the r.sub.1 signal received in the delay circuit 10 by the period of time it takes the adders 30, 31, and 32 to complete their processing. This provision of a delay circuit(s) in parallel with an arithmetic circuit(s) such as the adders 30, 31, and 32 is important to ensuring the synchronism of the converter/processor 100. Examples of delay circuits, adders, and multipliers will be described in further detailed below after describing the overall operation of the converter/processor 100.

Adders 30, 31, and 32 are residue arithmetic adders with the b input connected to form (-b) mod m or m-b, the additive inverse of b mod m. By use of the additive inverse the adders 30, 31, and 32 perform subtraction. Adder 30 subtracts r.sub.1 from r.sub.2 using modulo m.sub.2 subtraction and outputs on signal line 56 a signal corresponding to .vertline.a.sub.2 m.sub.1 .vertline..sub.m .sub.2. The operation performed by the adder 30 is analogous to step 4b of the numerical example illustrated in FIG. 11. Adder 31 subtracts r.sub.1 from r.sub.3 using modulo m.sub.3 subtraction and transmits on signal line 57 a signal corresponding to .vertline.a.sub.3 m.sub.1 m.sub.2 .vertline.m.sub.3 + .vertline.a.sub.2 m.sub.1 .vertline.m.sub.3. The operation performed by the adder 31 is analogous to step 4c of FIG. 11. Adder 32 subtracts r.sub.1 from zero using modulo m.sub.4 subtraction and transmits on signal line 58 a signal corresponding to .vertline.a.sub.4 m.sub.1 m.sub.2 m.sub.3 .vertline. m.sub.4 + .vertline.a.sub.3 m.sub.1 m.sub.2 .vertline.m.sub.4 + .vertline.a.sub.2 m.sub.1 .vertline.m.sub.4. The operation performed by the adder 32 is analogous to step 4d of FIG. 11. The operations performed in delay circuit 10 and adders 30, 31 and 32 constitute the first stage of processing.

In the second stage of processing, the r.sub.1 signal transmitted on signal line 55 is delayed by a delay circuit 11 and is transmitted on signal line 59. The signal transmitted on signal line 56 is received in a multiplier 40. Multiplier 40 multiplies the value of the signal received from signal line 56 by the multiplicative inverse of the first modulus ##EQU14## using modulo m.sub.2 multiplication and transmits on signal line 60 a signal corresponding to a.sub.2, analogous to step 6a of FIG. 11. In a similar manner, a multiplier 41 transmits on signal line 61 a signal corresponding to .vertline.a.sub.3 m.sub.2 .vertline.m.sub.3 + .vertline.a.sub.2 .vertline.m.sub.3 and a multiplier 42 transmits on signal line 62 a signal corresponding to .vertline.a.sub.4 m.sub.2 m.sub.3 .vertline.m.sub.4 + .vertline.a.sub.3 m.sub.2 .vertline.m.sub.4 + .vertline.a.sub.2 .vertline.m.sub.4. The operations performed by multipliers 41 and 42 are analogous to steps 6b and 6c of FIG. 11, respectively.

In the third processing stage, the a.sub.1 signal on signal line 59 is delayed by delay circuit 12. The a.sub.2 signal is delayed by delay circuit 13. The a.sub.2 signal is also provided to adders 33 and 34 via signal line 60. The adder 33 subtracts a.sub.2 from the value received via signal line 61 using modulo m.sub.3 subtraction and transmits on signal line 65 a signal corresponding to .vertline.a.sub.3 m.sub.2 .vertline.m.sub.3. The operation performed by the adder 33 is analogous to step 8b of FIG. 11. The adder 34 subtracts a.sub.2 from the value received via signal line 62 using modulo m.sub.4 subtraction and transmits on signal line 66 a signal corresponding to .vertline.a.sub.4 m.sub.2 m.sub.3 .vertline.m.sub.4 +.vertline.a.sub.3 m.sub.2 .vertline.m.sub.4, analogous to step 8c of FIG. 11.

In the fourth processing stage the a.sub.1 and a.sub.2 signals are delayed by delay circuits 14 and 15, respectively. The value transmitted via signal line 65 is multiplied by a multiplicative inverse using modulo m.sub.3 multiplication in multiplier 43 to transmit on signal line 69 a value corresponding to a.sub.3, the third mixed base digit, analogous to step 10a of FIG. 11. The value transmitted via signal line 66 is multiplied using modulo m.sub.4 multiplication by a multiplicative inverse in a multiplier 44 to transmit on signal line 70 a value corresponding to .vertline.a.sub.4 m.sub.3 .vertline.m.sub.4 + .vertline.a.sub.3 .vertline.m.sub.4, analogous to step 10b of FIG. 11.

In the fifth processing stage the a.sub.1, a.sub.2, and a.sub.3 signals are delayed by delay circuits 16, 17 and 18, respectively. The a.sub.3 value transmitted via signal line 69 is subtracted from the value received via signal line 70 by an adder 35 to transmit on signal line 74 a sum value S, analogous to step 12b of FIG. 11.

In the sixth processing stage the a.sub.1, a.sub.2, and a.sub.3 signals are delayed by delay circuits 19, 20, and 21. Delay circuits 19, 20, and 21 transmit values of mixed base digits a.sub.1, a.sub.2, and a.sub.3 on signal lines 81, 82, and 83, respectively The mixed base digits a.sub.1, a.sub.2, and a.sub.3 represent the same number as r.sub.1, r.sub.2, and r.sub.3 received by the first processing stage. The S value transmitted on signal line 74 is multiplied by .vertline.-m.sub.1 m.sub.2 .vertline.m.sub.4 using modulo m.sub.4 multiplication in multiplier 45 in accordance with Equation 22. This multiplied value is transmitted from the multiplier 45 on signal line 84 as .vertline.X.vertline.m.sub.4, the redundant residue digit.

As described above, base extension performed by the converter/processor 100 requires only one additional parallel channel of residue computation plus one multiplication step beyond that required for mixed base digit extraction. If residue to mixed base conversion is required but extension of the base is not required then adders 32, 34, and 35 and multipliers 42, 44, and 45, and associated signal lines need not be provided Similarly, if only base extension is required, then delay circuits 10 through 21 and associated signal lines need not be provided.

If additional, that is, more than one, redundant residue digits are desired, then additional computational channels can be placed in parallel with adders 32, 34, and 35 and multipliers 42, 44, and 45, without increasing the processing time of the converter/processor.

The adder and multipliers of the converter/ processor 100 are optical arithmetic and logic units (OALUs). The OALUs employed can be the Fourier transform pattern recognition type described in the '843 patent cited above or the optical cross-bar type described in copending application 07/019,761 cited above. Both of these OALUs perform residue additions and multiplications of two numbers, accepting numerical inputs in the one-of-many format.

FIG. 13 illustrates a Fourier transform pattern recognition OALU 200 configured to add two numbers a and b using modulo 3 addition. In Figure 13, inputs from point-light sources 220, 221, 222, 223, 224, and 225 form a spatial pattern corresponding to a given separation of point-light sources. Lenses 230, 231, 232, 233, and 234 produce Fourier transforms of the source configuration. Filters 240, 241, 242, 243, and 244 allow light energy to pass when the light energy results from a specific spatial pattern. The output of a filter passes through lens 250, 251, 252, 253, or 254 and is detected by collector 260, 261, 262, 263, or 264. The pattern of the point-light sources and the detection values of the filters accomplish the addition process.

FIG. 14 illustrates a Fourier transform pattern recognition OALU 300 configured to multiply two input numbers using modulo 5 multiplication. In FIG. 14, one input is fixed at the multiplicative inverse ##EQU15## The multiplier of FIG. 14 is constructed and operated similarly to the adder 200 of FIG. 13. Alternatively, any other RNS optical adder or multiplier can be used as the adders and multipliers of the converter/processor 100. The multipliers can also be fixed interconnect pattern multipliers which exploit the ring property of residue arithmetic to convert a variable input into the desired product. These fixed interconnect pattern multipliers are described in "Optical Computation Using Residue Arithmetic" by A. Huang, Y. Toshida, J.W. Goodman, and S. Ishihara in Applied Optics 18, 149-162 (1979), incorporated herein by reference.

Delay circuits of the converter/processor 100 can be an adder configured OALU such as described above in which one operand is zero, or a multiplier configured OALU in which one operand is one.

The pipelined base extension processor illustrated in FIG. 12 could produce incorrect results if negative residue input numbers are used because the process carried out by the processor implicitly assumes that redundant mixed base digit a.sub.r is zero. For example, FIG. 15 illustrates a portion of a redundant ring with moduli of m.sub.1 =3, m.sub.2 =5, m.sub.3 =2, and m.sub.4 =7. FIG. 16 lists values corresponding to the FIG. 15 ring. As discussed above, the processor described with respect to FIG. 12 would calculate a redundant residue digit, .vertline.X.vertline..sub.7, of 5 if X=19 in the form of r.sub.1 =1, r.sub.2 =4, and r.sub.3 =1 were input to the processor. However, as illustrated by FIG. 8, r.sub.1 =1, r.sub.2 =4, and r.sub.3 =1 could represent X=-11. As illustrated in FIG. 15, X=-11 corresponds to a ring position of 199 and therefore X=-11 has a redundant residue digit of 199 mod 7 or 3. As this example illustrates, the processor of the first embodiment must have prior information of the sign of the input number to avoid errors in extending the base of a RNS.

Providing a signal indicating the sign of the input number, while feasible, would make a system employing the processor more complex, therefore it is desirable to design a base extension processor which does not require a sign signal.

One method of deriving a correct redundant residue digit is to determine what number must be entered into adder 32 of FIG. 12 to get the correct redundant residue digit. Either O or M mod m.sub.r (m.sub.r is the same as m.sub.4 in the examples described above) must be entered into adder 32 to calculate a correct redundant residue digit. However, at the first stage of processing of FIG. 12 whether to enter O or M mod m.sub.r into adder 32 is not known. A determination of whether to enter O or M mode m.sub.r can only be made after a.sub.3 is calculated by multiplier 43 since a.sub.3 indicates the sign of a residue number, as discussed with respect to FIG. 8.

A duplicate channel can be added in parallel with the channel comprised of adders 32, 34, and 35 and multipliers 42, 44, and 45 as illustrated in FIG. 17 as converter/processor 500. In FIG. 17, primed numbers are used to designate components which are analogous to those described with respect to FIG. 12. This converter/processor 500 has M mod m.sub.r entered into a first stage adder 36. The converter/processor 500 carries out calculations using O and M mod m.sub.r respectively, and then value of .vertline.X.vertline.m.sub.4 from the appropriate channel is selected by selector 90 based on the value of a.sub.3.

Using a duplicate channel requires more hardware, therefore the process described below is preferable where hardware minimization is a paramount concern. As discussed above, if the residue input number is negative the following relationship holds:

a.sub.r =m.sub.r -1=.vertline.-1.vertline.m.sub.r (23) For example, applying Equation (23) to a.sub.r, or a.sub.4, of step 14 of FIG. 10 results in: ##EQU16## Which can be solved for .vertline.X.vertline..sub.7 as follows: .vertline.X.vertline..sub.7 =.vertline.-3.multidot.5.multidot.2+(-1).multidot.3.multidot.5.multidot.2.vertline..sub.7 =.vertline.-60.vertline..sub.7 =3 (25) A value of .vertline.X.vertline..sub.7 equal to 3 is the correct redundant residue digit for a negative input number X. The value of the left-hand side of Equation (24) is the output from the adder 35 of FIG. 12. In the special case of m.sub.N being equal to 2, a.sub.N is O for positive numbers and 1 for negative numbers. Thus, a.sub.N can be used as a factor to turn .vertline.-1.vertline.m.sub.r off for positive numbers or .vertline.-1.vertline.m.sub.r on for negative numbers in the computation of a.sub.r as expressed by the following equation: a.sub.r =a.sub.N (m.sub.r -1)=.vertline.-a.sub.N .vertline.m.sub.r (26) Assuming m.sub.N (m.sub.N is m.sub.3 in the examples described above) is 2, a.sub.N is 0 for positive numbers and 1 for negative numbers. Thus, a.sub.N can be used to determine a.sub.r according to the following equation: a.sub.r =a.sub.N (m.sub.r -1) =.vertline.-a.sub.N .vertline.m.sub.r (27) As seen by inspection of Equation (27) when a.sub.N is 0, a.sub.r is 0 and when a.sub.N is 1, a.sub.r is .vertline.-1.vertline.m.sub.r.

If S denotes the output from the N-th adder in the m.sub.r channel, then substitution of S into Equation (27) yields: ##EQU17## If m.sub.N is used to denote M/m.sub.N then Equation (28) can be solved for .vertline.X.vertline.m.sub.r as follows:

.vertline.X.vertline.m.sub.r =.vertline.-Ma.sub.N -m.sub.N S.vertline.m.sub.r (29)

FIG. 18 illustrates a converter/processor which implements Equation 29 to calculate redundant residue digit .vertline.X.vertline.m.sub.4. The converter/processor 600 of FIG. 18 is similar to converter/processor 100 of FIG. 12 except for the addition of an adder 91 to implement the subtraction operation of Equation 29. The converter/processor requires one more processing stage than the converter/processor 100.

Equation (29) can be rearranged to produce the following equation:

.vertline.X.vertline.m.sub.r =.vertline. .vertline.-m.sub.N .vertline.m.sub.r .multidot..vertline.m.sub.N a.sub.N +S.vertline.m.sub.r (30)

If the a input to the N-th modulo m.sub.r adder (adder 35 in the embodiment described above) is denoted by S' then the following equation holds:

S=S'-a.sub.N (31)

Applying Equation 31 to the sum inside Equation 30 as follows and recognizing that m.sub.N is 2 results in Equation 32: ##EQU18##

Applying Equation 32 to Equation (30) results in the following Equation:

.vertline.X.vertline.m.sub.r =.vertline. .vertline.-m.sub.N .vertline.m.sub.r .multidot..vertline.a.sub.N +S'.vertline.m.sub.r .vertline.m.sub.r (33)

FIG. 19 illustrates a converter/processor 700 which implements Equation 33. The converter/ processor 700 illustrated in FIG. 19 is similar to the converter/processor 100 of FIG. 12 except that the adder 35 of converter/processor 100, which subtracts its b input from its a input, has been replaced with an adder 93, which adds its b input to its a input.

All of the base extension processors illustrated in FIGS. 17, 18, and 19 have the advantage of not requiring a priori knowledge of the sign of an input number.

FIG. 20 illustrates a residue addition overflow detection processor which utilizes a residue to mixed base converter and base extension processor as described above. In FIG. 20 a residue addition overflow detection processor 900 adds a first non-redundant residue input number X and a second non-redundant residue input number Y. The overflow detection processor 900 includes a first base extension circuit 910 which receives the first non-redundant residue input number X and which generates a first redundant residue digit X mod m.sub.r, and a second base extension circuit 920, parallel to the first base extension circuit 91? , which receives the second non-redundant residue input number Y and generates a second redundant residue digit Y mod m.sub.r.

An adder 930 receives the first non-redundant residue input number X and the first redundant residue digit X mod m.sub.r as a first operand, and receives the second non-redundant residue input number Y and the second redundant residue digit Y mod m.sub.r as a second operand. The adder 930 adds the first operand to the second operand using modular addition to produce a sum in residue representation.

A residue to mixed base converter 940 receives the sum, converts the sum into mixed base representation, and outputs digits corresponding to the mixed base representation. If the redundant mixed base digit a.sub.r is zero then overflow has not occurred in the addition of the first non-redundant residue input number to the second non-redundant residue input number. If the redundant mixed base digit is not zero then overflow has occurred.

The foregoing description has been set forth merely to illustrate preferred embodiments of the invention and is not intended to be limiting. Since modification of the described embodiments incorporating the spirit and substance of the invention may occur to persons skilled in the art, the scope of the invention should be limited solely with respect to the appended claims and equivalents. For example, electrical signals can be used instead of optical signals depending on the particular application. Conversion and processing of an arbitrary number of input digits and an arbitrary number of redundant moduli can be implemented in accordance with the description above. The highest order modulus m.sub.N can be greater than two. For example, the embodiment illustrated in FIG. 17 can be used when m.sub.N =5 and when m.sub.N =3. FIGS. 21 and 22 list numerical values when m.sub.N =5 and when m.sub.N =3, respectively.

Claims

1. An information processor receiving a residue number as an input, said information processor comprising:

a plurality of arithmetic units arranged in a plurality of sequentially arranged stages, odd stages of said plurality of stages performing first arithmetic operations in parallel, even stages of said plurality of stages performing second arithmetic operations in parallel;

said odd and even stages alternately performing said first operations and said second operations to generate at least one mixed base digit corresponding to said residue number.

2. An information processor as set forth in claim 1, wherein said first operations are one of modular additions and modular subtractions, and said second operations are modular multiplications.

3. An information processor as set forth in claim 2, wherein said first and second operations are performed such that an equation in a general form of; ##EQU19## is solved for at least one a.sub.k, where k=1, ... N.

4. An information processor as set forth in claim 3, further comprising at least one delay circuit arranged such that said information processor processes information in a synchronous pipelined manner.

5. An information processor as set forth in claim 4, wherein said plurality of arithmetic units and said at least one delay circuit are arranged in a plurality of non-redundant residue channels such that one channel is associated with each digit of said at least one mixed base digit.

6. An information processor as set forth in claim 5, wherein said arithmetic units are optical arithmetic units.

7. An information processor as set forth in claim 5, further comprising a first redundant residue channel arranged parallel to said nonredundant residue channels; said first redundant residue channel including arithmetic units which calculate a first redundant residue digit based on said residue number.

8. An information processor as set forth in claim 7, wherein said arithmetic units are optical arithmetic units.

9. An information processor as set forth in claim 7, wherein an N-th arithmetic unit performing first operations in said first redundant residue channel adds a.sub.N to a sum S', said sum S' generated from stages prior to said N-th arithmetic unit performing first operations, where a.sub.N is a highest order non-redundant mixed base digit and N is a positive integer.

10. An information processor as set forth in claim 7, wherein:

a first arithmetic unit of said first redundant residue channel utilizes an input of zero; and wherein said information processor further comprises;

a second redundant residue channel arranged parallel to said first redundant residue channel, said second redundant residue channel including arithmetic units to calculate a second redundant residue digit based on said residue number, said second redundant residue channel utilizing an input of .vertline.M.vertline.m.sub.r, where M is a product of non-redundant moduli and m.sub.r is a redundant modulus; and

a selector selecting said first or second redundant residue digits based on a value of a highest order non-redundant mixed base digit.

11. An information processor as set forth in claim 7, further comprising a final stage arithmetic unit adding M.multidot.a.sub.N to a value received from a last arithmetic unit of said first redundant residue channel, where M is a product of non-redundant moduli and a.sub.N is a highest order non-redundant mixed base digit.

12. A method of processing a residue input number signal to generate a mixed base digits signal corresponding to said residue input number signal, comprising the steps of:

(a) receiving said residue input number signal;

(b) subtracting a first digit signal of said residue input number signal from other digit signals of said residue input number signal to generate first stage signals, said first digit signal indicative of a first mixed base digit;

(c) in parallel with step (b), time delaying a signal identical to said first digit signal;

(d) multiplying each of said first stage signals by multiplicative inverse signals to produce a second mixed base digit signal indicative of a second mixed base digit;

(e) in parallel with step (d), time delaying said signal identical to said first digit signal.

13. A method according to claim 12, further comprising the steps of:

(f) repeatedly subtracting mixed base digit signals and multiplying by multiplicative inverse signals in a synchronous pipelined fashion such that additional mixed base digit signals are generated.

14. A method according to claim 13, further comprising these steps performed in synchronism with steps (a) through (f):

(g) subtracting said first digit signal of said residue input number signal from a zero signal;

(h) repeatedly subtracting mixed base digit signals and multiplying by multiplicative inverse signals in a synchronous pipelined fashion such that a first sum signal, is generated;

(i) subtracting a highest order mixed base digit signal from said first sum signal to produce a second signal; and

(j) multiplying said second signal by a first multiplier signal to produce a first redundant residue digit signal associated with said residue input number signal, said first redundant residue digit signal representing a correct redundant residue digit when said residue input number signal represents a non-negative number.

15. A method according to claim 13 further comprising these steps performed in synchronism with steps (a) through (f):

(k) subtracting said first digit signal of said residue input number signal from a zero signal;

(1) repeatedly subtracting mixed base digit signals and multiplying by multiplicative inverse signals in a synchronous pipelined fashion such that a first sum signal is generated;

(m) adding a highest order mixed base digit signal to said first sum signal to produce a second signal; and

(n) multiplying said second signal by a multiplier signal to produce a first redundant residue digit signal associated with said residue input number signal, said first redundant residue digit signal representing a correct redundant residue digit when said residue input number signal represents a negative number and when said residue input number signal represents a non-negative number.

16. A method according to claim 14, further comprising these steps (o) thorough (r) performed in synchronism with steps (a) through (f) and steps (g) through (j):

(o) subtracting said first digit signal of said residue input number signal from a signal representing a number based on a non-redundant ring circumference;

(p) repeatedly subtracting mixed base digit signals and multiplying by multiplicative inverse signals in a synchronous pipelined fashion such that a third sum signal is generated;

(q) subtracting a highest order mixed base digit signal from said third sum signal to produce a fourth signal;

(r) multiplying said fourth signal by a second multiplier signal to produce a second redundant residue digit signal associated with said residue input number signal;

(s) after completion of steps (a) through (r), selecting one of said first redundant residue digit signal and said second redundant residue digit signal based on a highest order mixed base digit signal to produce a fifth signal, said fifth signal representing a correct redundant residue digit when said residue input number signal represents a negative number and when said residue input number signal represents a non-negative number.

17. A method according to claim 14, further comprising the step of:

(t) after steps (a) through (j), adding a signal representing M.multidot.a.sub.N to said first redundant residue digit signal, where M is a product of nonredundant moduli and a.sub.N is a highest order mixed base digit, to produce a sixth signal, said sixth signal representing a correct redundant residue digit when said residue input number signal represents a negative number and when said residue input number signal represents a non-negative number.

18. An information processor receiving a residue number as an input, said information processor comprising:

a plurality of optical arithmetic and logic units (OALUs) arranged in channels and stages, each digit of said residue number corresponding to a channel which produces a mixed base digit associated with said residue number; said stages serially arranged to successively generate mixed base digits corresponding to said residue number by performing modular multiplication and modular subtraction; and

delay circuits arranged parallel to said plurality of OALUs such that all of said mixed base digits are transmitted from said information processor at essentially the same time.

19. An information processor as set forth in claim 18, wherein said modular multiplication and modular subtraction is performed to solve an equation in the general form of; ##EQU20## for each a.sub.j, J=1, ... N, where a.sub.j is a mixed base digit corresponding to said residue number, and m.sub.i are moduli of a residue number system.

20. An information processor as set forth in claim 19, further comprising at least one additional channel of OALUs for calculating a redundant residue digit, which corresponds to said residue number, based on said mixed base digits.