Embodiments of the present disclosure relate to a pixel array substrate and a driving method thereof, a display panel, and a display device.
An organic light-emitting diode (OLED) display panel has the advantages of the thin thickness, light weight, wide viewing angle, active luminescence, continuously adjustable luminous color, low cost, fast response speed, low energy consumption, low driving voltage, wide operating temperature range, simple production process, high luminous efficiency, flexible display, etc., and has been widely used in the display fields of mobile phones, tablet computers, digital cameras, etc.
At least one embodiment of the present disclosure provides a pixel array substrate, and the pixel array substrate includes: a plurality of pixel units arranged in a plurality of pixel rows, and common electrodes distributed in the plurality of pixel rows; and each of the plurality of pixel units includes a light emitting element, first electrodes of light emitting elements of a plurality of pixel units in each of the plurality of pixel rows are electrically connected with each other to form a common electrode in the each of the plurality of pixel rows, and the common electrodes in the plurality of pixel rows are insulated from each other.
For example, in the pixel array substrate provided by an embodiment of the present disclosure, the common electrode in the each of the plurality of pixel rows is configured to receive a first power signal to set the light emitting elements of the plurality of pixel units in the each of the plurality of pixel rows in a reverse bias state during a non-light emitting phase of the plurality of pixel units in the each of the plurality of pixel rows, and to receive a second power signal to set the light emitting elements of the plurality of pixel units in the each of the plurality of pixel rows in a forward bias state during a light emitting phase of the plurality of pixel units in the each of the plurality of pixel rows.
For example, the pixel array substrate provided by an embodiment of the present disclosure further includes a plurality of power signal lines in one-to-one correspondence with the plurality of pixel rows; and the common electrode in the each of the plurality of pixel rows is connected with a power signal line corresponding to the each of the plurality of pixel rows, and the first power signal and the second power signal are transmitted to the common electrode in the each of the plurality of pixel rows via the power signal line corresponding to the each of the plurality of pixel rows.
For example, the pixel array substrate provided by an embodiment of the present disclosure further includes a pixel defining layer for defining the plurality of pixel units; and the pixel defining layer includes a plurality of via holes, and the common electrode in the each of the plurality of pixel rows is connected with the power signal line corresponding to the each of the plurality of pixel rows through at least one of the plurality of via holes.
For example, the pixel array substrate provided by an embodiment of the present disclosure further includes a plurality of auxiliary cathodes in one-to-one correspondence with the plurality of via holes; and the common electrode in the each of the plurality of pixel rows is connected with at least one of the plurality of auxiliary cathodes through at least one of the plurality of via holes, and the power signal line corresponding to the each of the plurality of pixel rows is connected with the at least one of the plurality of auxiliary cathodes.
For example, in the pixel array substrate provided by an embodiment of the present disclosure, each of the plurality of pixel units further includes a driving circuit, a storage capacitor and a driving control circuit; a first terminal of the driving circuit is connected with a first node, a second terminal of the driving circuit is connected with a second node, and a control terminal of the driving circuit is connected with a third node and is configured to control a driving current flowing through the first node and the second node for driving the light emitting element; a second electrode of the light emitting element is connected with the second node; a first terminal of the storage capacitor is coupled to the control terminal of the driving circuit, and a second terminal of the storage capacitor is coupled to the second terminal of the driving circuit; and the driving control circuit is configured to respectively apply a reference voltage signal and a data voltage signal to the control terminal of the driving circuit in response to a scan signal, and to provide a first voltage to the first node in response to a light emitting control signal, and to reset the second node in response to a reset signal.
For example, in the pixel array substrate provided by an embodiment of the present disclosure, the driving circuit includes a driving transistor, a first electrode of the driving transistor serves as the first terminal of the driving circuit, a second electrode of the driving transistor serves as the second terminal of the driving circuit, and a gate electrode of the driving transistor serves as the control terminal of the driving circuit.
For example, in the pixel array substrate provided by an embodiment of the present disclosure, the driving control circuit includes: a switching circuit, configured to respectively apply the reference voltage signal and the data voltage signal to the control terminal of the driving circuit in response to the scan signal.
For example, in the pixel array substrate provided by an embodiment of the present disclosure, the switching circuit includes a first transistor, a gate electrode of the first transistor is connected with a scan signal terminal to receive the scan signal, a first electrode of the first transistor is connected with a data signal terminal to receive the reference voltage signal and the data voltage signal, and a second electrode of the first transistor is connected with the third node.
For example, in the pixel array substrate provided by an embodiment of the present disclosure, the driving control circuit further includes: a light emitting control circuit, configured to provide the first voltage to the first node in response to the light emitting control signal.
For example, in the pixel array substrate provided by an embodiment of the present disclosure, the light emitting control circuit includes a second transistor, a gate electrode of the second transistor is connected with a light emitting control signal terminal to receive the light emitting control signal, a first electrode of the second transistor is connected with a first power terminal to receive the first voltage, and a second electrode of the second transistor is connected with the first node.
For example, in the pixel array substrate provided by an embodiment of the present disclosure, the driving control circuit further includes: a reset circuit, configured to reset the second node in response to the reset signal.
For example, in the pixel array substrate provided by an embodiment of the present disclosure, the reset circuit includes a third transistor, a gate electrode of the third transistor is connected with a reset signal terminal to receive the reset signal, a first electrode of the third transistor is connected with a reset voltage terminal to receive a reset voltage, and a second electrode of the third transistor is connected with the second node.
For example, in the pixel array substrate provided by an embodiment of the present disclosure, each of the plurality of pixel units further includes a first capacitor, a first terminal of the first capacitor is coupled to the first electrode of the light emitting element, and a second terminal of the first capacitor is coupled to the second electrode of the light emitting element.
At least one embodiment of the present disclosure further provides a display panel, and the display panel includes the pixel array substrate provided by any one of the embodiments of the present disclosure.
At least one embodiment of the present disclosure further provides a display device, and the display device includes the display panel provided by any one of the embodiments of the present disclosure.
At least one embodiment of the present disclosure further provides a driving method of a pixel array substrate, and the driving method includes: providing, during a non-light emitting phase of the plurality of pixel units in each of the plurality of pixel rows, a first power signal to the common electrode in the each of the plurality of pixel rows, so as to set the light emitting elements of the plurality of pixel units in the each of the plurality of pixel rows in a reverse bias state; and providing, during a light emitting phase of the plurality of pixel units in the each of the plurality of pixel rows, a second power signal to the common electrode in the each of the plurality of pixel rows, so as to set the light emitting elements of the plurality of pixel units in the each of the plurality of pixel rows in a forward bias state.
For example, in the driving method provided by an embodiment of the present disclosure, each of the plurality of pixel units further includes a driving circuit, a storage capacitor, a switching circuit, a light emitting control circuit and a reset circuit; a first terminal of the driving circuit is connected with a first node, a second terminal of the driving circuit is connected with a second node, and a control terminal of the driving circuit is connected with a third node and is configured to control a driving current flowing through the first node and the second node for driving the light emitting element; a second electrode of the light emitting element is connected with the second node; a first terminal of the storage capacitor is coupled to the control terminal of the driving circuit, and a second terminal of the storage capacitor is coupled to the second terminal of the driving circuit; the switching circuit is configured to respectively apply a reference voltage signal and a data voltage signal to the control terminal of the driving circuit in response to a scan signal; the light emitting control circuit is configured to provide a first voltage to the first node in response to a light emitting control signal; the reset circuit is configured to reset the second node in response to a reset signal; the non-light emitting phase includes a reset phase, a compensation phase and a data writing phase; and the driving method further includes: during the reset phase, inputting the reset signal, the scan signal and the reference voltage signal, so that the reset circuit and the switching circuit are turned on, the reset circuit resets the light emitting element, the switching circuit writes the reference voltage signal into the control terminal of the driving circuit, and the reference voltage signal is stored in the storage capacitor; during the compensation phase, inputting the scan signal, the light emitting control signal and the reference voltage signal, so that the switching circuit, the driving circuit and the light emitting control circuit are turned on, the switching circuit continuously writes the reference voltage signal into the control terminal of the driving circuit to maintain a voltage of the control terminal of the driving circuit, and the light emitting control circuit compensates for the driving circuit; during the data writing phase, inputting the scan signal and the data voltage signal, so that the switching circuit is turned on, the switching circuit writes the data voltage signal into the control terminal of the driving circuit, and the data voltage signal is stored in the storage capacitor; and during the light emitting phase, inputting the light emitting control signal, so that the light emitting control circuit and the driving circuit are turned on, and the driving circuit applies the driving current to the light emitting element so as to drive the light emitting element to emit light.
In order to clearly illustrate the technical solution of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described in the following; it is obvious that the described drawings are only related to some embodiments of the present disclosure and thus are not limitative of the present disclosure.
In order to make objects, technical details and advantages of the embodiments of the present disclosure apparent, the technical solutions of the embodiment will be described in a clearly and fully understandable way in connection with the drawings related to the embodiments of the present disclosure. It is obvious that the described embodiments are just a part but not all of the embodiments of the present disclosure. Based on the described embodiments herein, those skilled in the art can obtain other embodiment(s), without any inventive work, which should be within the scope of the present disclosure.
Unless otherwise defined, all the technical and scientific terms used herein have the same meanings as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terms “first,” “second,” etc., which are used in the description and the claims of the present application for disclosure, are not intended to indicate any sequence, amount or importance, but distinguish various components. Also, the terms “a,” “an” or “the,” etc., are not intended to indicate a limitation of quantity, but rather indicate the presence of at least one. The terms “comprise,” “comprising,” “include,” “including,” etc., are intended to specify that the elements or the objects stated before these terms encompass the elements or the objects and equivalents thereof listed after these terms, but do not preclude the other elements or objects. The phrases “connect”, “connected”, etc., are not intended to define a physical connection or mechanical connection, but may include an electrical connection, directly or indirectly. “Upper”, “lower”, “left”, “right”, etc. are only used to indicate the relative positional relationship, and when the absolute position of the object to be described is changed, the relative positional relationship may also change accordingly.
The present disclosure will be described below through several specific embodiments. In order to keep the description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and known components (members) may be omitted. When any component of the embodiments of the present disclosure appears in more than one drawing, the component is denoted by the same or similar reference numeral in each drawing.
As shown in
As shown in
In addition, as shown in
When the display panel 1 displays a frame of image, in each pixel unit 50, the pixel circuit 100 generates a driving current flowing through the light emitting element 200 to drive the light emitting element 200 to emit light according to a data signal provided by the data driving circuit under the control of signals (e.g., a scan signal, a reset signal, a light emitting control signal, etc.) provided by the gate driving circuit, so as to display.
During a reset phase, the scan signal SN is at a high level, so as to turn on the first transistor T1, and the data signal DATA (i.e., a reference voltage signal Vref) at this time is transmitted to the third node N3 via the first transistor T1, so as to reset the first terminal of the storage capacitor C0 to Vref; the light emitting control signal EM is at a low level, so as to turn off the second transistor T2; and when the reset signal RS is at a high level, the third transistor T3 is turned on, and the reset voltage Vsus is transmitted to the second node N2 via the third transistor T3, so as to reset the second terminal of the storage capacitor C0 and the second terminal of the first capacitor C1 to Vsus. Therefore, in this phase, the data signal stored in the storage capacitor C0 and the gate voltage of the driving transistor T0 can be initialized. In addition, at the end of the reset phase, the voltage difference across the storage capacitor C0 is Vref−Vsus, which is greater than the threshold voltage Vth of the driving transistor T0 (i.e., Vref−Vsus>Vth). Thus, the driving transistor T0 can be in an on state.
During a compensation phase, the scan signal SN is at a high level, so as to turn on the first transistor T1, and the reference voltage signal Vref is transmitted to the third node N3 via the first transistor T1 to maintain the first terminal of the storage capacitor C0 at Vref; the reset signal RS is at a low level, so as to turn off the third transistor T3; and the light emitting control signal EM is at a high level, so as to turn on the second transistor T2. Because the driving transistor T0 is in an on state at the beginning of the compensation phase (i.e., at the end of the reset phase), the first voltage VDD can charge the second node N2 (i.e., the second terminal of the storage capacitor C0) via the second transistor T2 and the driving transistor T0. According to the characteristics of the driving transistor T0 itself (i.e., there exists the threshold voltage Vth), when the second terminal of the storage capacitor C0 and the second terminal of the first capacitor C1 are charged to Vref−Vth, the driving transistor T0 is turned off and the charging process ends. At the end of the compensation phase, the voltage difference across the storage capacitor C0 is Vth, that is, the compensation for the threshold voltage of the driving transistor T0 itself is realized.
During a data writing phase, the reset signal RS is at a low level, so as to turn off the third transistor T3; the light emitting control signal EM is at a low level, so as to turn off the second transistor T2; and when the scan signal SN is at a high level, the first transistor T1 is turned on, and the data signal DATA (i.e., a data voltage signal Vdata) at this time is transmitted to the third node N3 via the first transistor T1, and is stored in the storage capacitor C0 for turning on the driving transistor T0 in a subsequent light emitting phase to supply the driving current for the light emitting element 200.
During a light emitting phase, the scan signal SN is at a low level, so as to turn off the first transistor T1; the reset signal RS is at a low level, so as to turn off the third transistor T3; and the light emitting control signal EM is at a high level, so as to turn on the second transistor T2. At this time, the driving current generated in response to the voltage signal (i.e., the voltage signal stored in the storage capacitor C0 at the end of the data writing phase), which is applied to the gate electrode of the driving transistor T0 and is related to Vdata, is supplied to the light emitting element 200 via the driving transistor T0, so as to drive the light emitting element 200 to emit light.
In research, the inventors of the present application have found that the light emitting element 200 (e.g. an organic light-emitting diode) also has a capacitance Coled itself. In the above-mentioned data writing phase, because both the second transistor T2 and the third transistor T3 are turned off, there is no direct current path through the second node N2, and the second node N2 is in a floating state; and while the first transistor T1 is turned on, the potential of the third node N3 jumps from Vref to Vdata. Due to the bootstrap effect of the storage capacitor C0, the potential of the second node N2 will also change accordingly. Because the storage capacitor C0, the first capacitor C1 and the capacitance Coled of the light emitting element 200 are coupled to each other, the potential change of the second node N2 is:
a (Vdata−Vref), where a=C0/(C0+C1+Coled).
Therefore, at this time, the voltage difference between the gate electrode and the source electrode of the driving transistor T0 is:
V
GS=(Vdata−Vref)·(1−a)+Vth
Furthermore, during the light emitting phase, the driving current supplied by the driving transistor T0 is:
where I represents the driving current and β represents a constant value.
In addition, the inventors of the present application have also found that, as shown in
At least one embodiment of the present disclosure provides a pixel array substrate, which includes a plurality of pixel units arranged in a plurality of pixel rows, and common electrodes distributed in the plurality of pixel rows. Each pixel unit includes a light emitting element; and first electrodes of light emitting elements of a plurality of pixel units in each pixel row are electrically connected with each other to form a common electrode in the each pixel row, and the common electrodes in the plurality of pixel rows are insulated from each other.
Some embodiments of the present disclosure further provide a driving method, a display panel and a display device corresponding to the above pixel array substrate.
As for the pixel array substrate provided by the above embodiment of the present disclosure, when driving the pixel units in the pixel array substrate to emit light, by adjusting the voltage of the common electrode in each pixel row, the light emitting elements of the pixel units in each pixel row are in a reverse bias state during a non-light emitting phase of the pixel units in each pixel row, and the light emitting elements of the pixel units in each pixel row are in a forward bias state during a light emitting phase of the pixel units in each pixel row, so that the brightness of the light emitting elements can be accurately controlled and the display quality is improved.
Some embodiments of the present disclosure and examples thereof will be described in detail below with reference to the accompanying drawings.
For example, the common electrodes 205 shown in
For example, in the pixel array substrate 20, the common electrode 205 in each pixel row is configured to receive a first power signal to set the light emitting elements 200 of the plurality of pixel units 50 in the each pixel row in a reverse bias state during a non-light emitting phase of the plurality of pixel units 50 in the each pixel row, and to receive a second power signal to set the light emitting elements 200 of the plurality of pixel units 50 in the each pixel row in a forward bias state during a light emitting phase of the plurality of pixel units 50 in the each pixel row. For example, the first power signal is at a high level which is capable of making the light emitting elements 200 in a reverse bias state, and the second power signal is at a low level (e.g., a ground level) which is capable of making the light emitting elements 200 in a forward bias state. For example, in some examples, the first power signal and the second power signal can be provided by a driving circuit similar to the gate driving circuit. For example, the driving circuit can also be formed on the pixel array substrate 20 in the form of GOA; alternatively, the gate driving circuit itself can provide the first power signal and the second power signal according to the requirements of the present disclosure; and alternatively, the first power signal and the second power signal can be provided by an integrated circuit driving chip, and for example, the integrated circuit driving chip can be bonded to the pixel array substrate 20 in the form of chip on film (C0F). It should be noted that the manner in which the first power signal and the second power signal are provided is not limited in the present disclosure.
For example, as shown in
For example, in some examples, the organic thin film layer 210 can include a multi-layer structure composed of a hole injecting layer, a hole transporting layer, a light emitting layer (e.g. formed of an organic electroluminescent material), an electron transporting layer and an electron injecting layer, and can further include a hole blocking layer and an electron blocking layer. The hole blocking layer can be disposed, for example, between the electron transporting layer and the light emitting layer, and the electron blocking layer can be disposed, for example, between the hole transporting layer and the light emitting layer. The arrangement and material of each layer in the organic layer 210 can be with reference to common designs, without being limited in the embodiments of the present disclosure.
It should be noted that the materials, structures and formation methods of the cathode 205, the anode 209 and the organic thin film layer 210 of the light emitting element 200 are not limited in the embodiments of the present disclosure.
For example, as shown in
For example, in some examples, especially in the case where the pixel array substrate 20 is used for a top-emission type organic light-emitting diode display panel, in order to take light transmittance into consideration, the transparent cathode of the light emitting element 200 has a thin thickness, resulting in poor conductivity of the common electrode 205. In order to improve the conductivity of the common electrode 205, as shown in
It should be noted that the arrangement manner of the auxiliary cathodes of the pixel array substrate provided by the embodiments of the present disclosure is not limited. The power signal line 18 can be electrically connected with the auxiliary cathode so as to be electrically connected with the common electrode indirectly, or can be directly electrically connected with the common electrode without being electrically connected with the auxiliary cathode, which is not limited in the present disclosure. In addition, whether the pixel array substrate is provided with the auxiliary cathode is not limited in the embodiments of the present disclosure.
It should be noted that
For example, as shown in
For example, as shown in
For example, as shown in
It should be noted that it is illustrative that the driving control circuit 165 in
In addition, other circuit structures of the pixel circuit shown in
For example, one example of the pixel circuit 150 shown in
For example, with reference to
For example, with reference to
For example, with reference to
For example, with reference to
It should be noted that it is illustrative that the pixel circuit 150 shown in
For example, as shown in
It should be noted that in some embodiments of the present disclosure, the capacitor (e.g., the storage capacitor C0 and the first capacitor C1) can be a capacitive component fabricated by a process. For example, the capacitive component is implemented by fabricating specific capacitor electrodes, and each electrode of the capacitor can be implemented by a metal layer, a semiconductor layer (e.g., doped polysilicon), etc. In some embodiments, the capacitor can also be a parasitic capacitance between various components, and can be realized by a transistor itself together with other components and circuits. The connection manners of the capacitors are not limited to the manners described above, and can also be other suitable connection manners, as long as the potential of the corresponding node can be stored.
It should be noted that in the description of various embodiments of the present disclosure, the first node N1, the second node N2 and the third node N3 do not represent actual components, but rather junction points of related electrical connections in the circuit diagram.
In addition, the transistors in the embodiments of the present disclosure are all described by taking N-type transistors as examples. In this case, the first electrode of the transistor is a drain electrode, and the second electrode thereof is a source electrode. It should be noted that the present disclosure includes but is not limited to this case. For example, one or more transistors in the pixel circuit 100 provided by the embodiments of the present disclosure can also adopt P-type transistors. In this case, the first electrode of the transistor is the source electrode, and the second electrode thereof is the drain electrode. All that is needed is to connect respective electrodes of transistors of the selected type with reference to the connection manners of respective electrodes of the corresponding transistors in the embodiments of the present disclosure and to allow the corresponding voltage terminals to provide corresponding high-level voltages or low-level voltages. When an N-type transistor is adopted, Indium Gallium Zinc Oxide (IGZO) can be used as the active layer of the thin film transistor. Compared with using Low Temperature Poly Silicon (LTPS) or amorphous silicon (such as hydrogenated amorphous silicon) as the active layer of the thin film transistor, the size of the transistor can be effectively reduced and leakage current can be prevented.
At least one embodiment of the present disclosure further provides a driving method corresponding to the pixel array substrate 20 provided by the above embodiments. The method includes: providing, during a non-light emitting phase of the plurality of pixel units 50 in each pixel row, a first power signal to the common electrode 205 in the each pixel row, so as to set the light emitting elements 200 of the plurality of pixel units 50 in the each pixel row in a reverse bias state; and providing, during a light emitting phase of the plurality of pixel units 50 in the each pixel row, a second power signal to the common electrode 205 in the each pixel row, so as to set the light emitting elements 200 of the plurality of pixel units 50 in the each pixel row in a forward bias state.
Hereinafter, by taking that the pixel circuit 150 of the pixel unit 50 in the pixel array substrate 20 shown in
It should be noted that, as shown in
It should also be noted that the potential level in the signal timing chart shown in
For example, as shown in
For example, as shown in
The pixel array substrate provided by the embodiments of the present disclosure can be driven by adopting the driving method described above, so that the brightness of the light emitting elements can be accurately controlled and the display quality can be improved.
At least one embodiment of the present disclosure further provides a display panel, which includes the pixel array substrate provided by any one of the above embodiments. The display panel can further include a gate driving circuit, a data driving circuit, etc. The description of the gate driving circuit, the data driving circuit, etc., can be with reference to the specific description of the organic light-emitting diode display panel 1 shown in
For example, in some examples, the display panel can include an integrated circuit driving chip, and the aforementioned first power signal and second power signal are provided by the integrated circuit driving chip. For example, the integrated circuit driving chip can be bonded to the pixel array substrate in the form of chip on film (C0F). For example, in some other examples, a driving circuit similar to the gate driving circuit can be provided on the pixel array substrate of the display panel, and the aforementioned first power signal and second power signal are provided by the driving circuit. For example, in further other examples, the gate driving circuit itself on the pixel array substrate can provide the aforementioned first power signal and second power signal. The present disclosure is not limited to these cases.
The technical effects of the display panel provided by the embodiments of the present disclosure can be with reference to the related description of the pixel array substrate 20 in the above embodiments, and details will not be described here again.
At least one embodiment of the present disclosure further provides a display device, which includes the display panel provided by any one of the above embodiments.
The display device in the present embodiment can be any product or component having a display function, such as a display, a television, an electronic paper display device, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator, etc. It should be noted that the display device can also include other conventional components or structures. For example, in order to realize necessary functions of the display device, those skilled in the art can set other conventional components or structures according to specific application scenarios, without being limited in the embodiments of the present disclosure.
The technical effects of the display device provided by the embodiments of the present disclosure can be with reference to the related description of the pixel array substrate 20 in the above embodiments, and details will not be described here again.
For the present disclosure, the following statements should be noted:
(1) The accompanying drawings involve only the structure(s) in connection with the embodiment(s) of the present disclosure, and other structure(s) can be referred to common design(s).
(2) For the purpose of clarity only, in accompanying drawings for illustrating the embodiment(s) of the present disclosure, the thickness and size of a layer or a structure may be enlarged or narrowed, that is, the drawings are not drawn in a real scale.
(3) In case of no conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.
What have been described above are only specific implementations of the present disclosure, the protection scope of the present disclosure is not limited thereto. Any changes or modifications easily occur to those skilled in the art within the technical scope of the present disclosure should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.
Filing Document | Filing Date | Country | Kind |
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PCT/CN2019/078328 | 3/15/2019 | WO | 00 |