Patent Application
20170048470
CMOS (Complementary Metal-Oxide-Semiconductor) image sensors constitute a well-established technology finding applications in various massive markets, e.g. mobile phone cameras, automotive, medical imaging, surveillance . . . Still, noise and dynamic range are two major areas demanding further performance improvement in solid-state imaging.
Various techniques have been proposed to adapt the response of CMOS image sensors to different intra-scene lighting conditions, from low light levels to bright regions. This capability is commonly known as high dynamic range. Numerous performance trade-offs are involved in each of these techniques. Ideally, the highest possible dynamic range must be reached without impacting on two critical parameters of the sensor, namely pixel size and noise.
One of the better reported techniques in terms of large extension of the dynamic range with little impact on the pixel size is dynamic well capacity adjustment. It was originally applied in CCD (Charge-Coupled Device) image sensors. In CMOS, this technique presents a major disadvantage, namely the increase of both temporal and spatial noise on the pixel signal. This drawback is directly related to the sub-threshold operation of the reset transistor at the end of every adjustment of the well capacity during the photo-integration period. The temporal noise added from this sub-threshold operation is strongly dependent on CMOS technological parameters, in turn leading to high spatial variation of the pixel response, i.e. fixed pattern noise. The sub-threshold temporal noise also contributes to generate large dips in the signal-to-noise ratio.
The present disclosure provides a pixel cell with the ability to carry out High Dynamic Range (HDR) imaging without the disadvantages found in current pixel cells. In one embodiment, the pixel cell comprises at least a reset device with asymmetric conduction and having at least three terminals. The first terminal can be connected to a tunable voltage source, the second terminal can be connected to the charge storage node, and the third terminal can control the flow of current from the first terminal into the second terminal.
In another embodiment, the present disclosure provides a method for obtaining a high-dynamic-range read-out signal from a pixel cell. The method can comprise first applying a reset pulse on the charge storage node through the reset device with asymmetric conduction in order to start the pixel data acquisition. The method can additionally comprise charge carriers being generated from radiation impinging on the photo-sensing element and stored on the charge storage node. The method can additionally comprise, after a first time interval of the photo-integration period, the voltage level at the first terminal of the reset device being decreased. The method can additionally comprise, after a second time interval of the photo-integration period, at least a second reset pulse being applied on the charge storage node through the reset device with asymmetric conduction. The method can additionally comprise charge carriers being again generated from radiation impinging on the photo-sensing element and stored on the charge storage node.
Embodiments of the disclosure provide a solution to carry out High Dynamic Range (HDR) imaging based on dynamic well capacity adjustment without incurring additional spatial-temporal noise and consequent Signal-to-Noise Ratio (SNR) dips caused by the sub-threshold operation of a CMOS (Complementary Metal-Oxide-Semiconductor) reset transistor in a pixel cell.
Embodiments of the disclosure employ realizations of transistors other than CMOS, e.g. Tunnel Field-Effect Transistors (TFETs), featuring asymmetric conduction between two of its terminals, where asymmetric conduction means that current can only flow in one direction between those two terminals. In some embodiments, one of such realizations plays the role of the pixel reset transistor in order to exploit the asymmetric conduction to perform dynamic well capacity adjustment. As a result, the sources of spatial-temporal noise arising from the sub-threshold operation of the pixel reset transistor in CMOS implementations are removed.
It should be noted that, although the disclosure will be described below in connection with use in a three-transistor (3T) pixel cell, the disclosure has equal applicability to other pixel cell realizations, e.g. a four-transistor (4T) cell, where a transistor can be employed to partially remove photo-generated charge according to the level of impinging photon flux.
During operation, the charge storage node (104) is initially reset to a prescribed voltage by temporally asserting the digital gate control signal (102) of the reset device (103). Once (102) is de-asserted, the photo-integration period associated with an image capture starts. During this period, photo-generated electrons accumulate at the storage node (104), decreasing its voltage as electrons are negative charge carriers. The photo-generated charge can eventually exceed the capacity of the node (104) due to a high photon flux impinging the pixel. In order to adjust the response of the pixel to such a high photon flux, the voltage level at node (101) is first decreased. The gate control signal (102) is then temporally asserted again. Owing to the asymmetric conduction of the reset device (103), part of the charge accumulated at the storage node (104) will be removed if the voltage level at this node (104) is below the voltage level at node (101). Otherwise, the charge stored at node (104) remains unaffected. The gate control signal (102) is then de-asserted and photo-integration resumes. The adjustment of the pixel response by the method just described can be performed several times during the image capture. For each of these adjustments, the assertion of the gate control signal (102) is preceded by a decrease of the voltage level at node (101). The pixel data acquisition ends when the switch transistor (107) is turned on. The pixel voltage at the storage node (104) is then buffered by the source-follower transistor (105) and conveyed to the column output (108) for read-out.
Pixel array (401) is a two-dimensional (2D) array of pixel cells. In one embodiment, all of the pixel cell transistors are CMOS devices except for the reset transistor, which is realized by a different combination of solid-state materials in order to give rise to asymmetric conduction in the aforementioned terms. In another embodiment, only some of the pixel cell transistors are CMOS devices. Yet in another embodiment, no CMOS transistor is present at the pixel cell. Pixel array (401) may be implemented as a front-side illuminated sensor or as a back-side illuminated sensor.
Circuitry for stored charge adjustment (403) generates the gate control signal (102) and the signal at node (101) during image capture in order to exploit the asymmetric conduction of the reset device for fitting the pixel response to the impinging photon flux. In one embodiment, signals (101) and (102) are generated by circuitry (403) as rolling shutter signals for the progressive acquisition of the image pixel data. In another embodiment, signals (101) and (102) are generated by circuitry (403) as global shutter signals for the simultaneous acquisition of the entire image pixel data. Row control circuitry (402) and column biasing and read-out circuitry (404) operate jointly for the activation of the switch transistor (107) and subsequent read-out of the column output (108) respectively. Column biasing and read-out circuitry (404) may include amplification circuitry, correlated double sampling circuitry, analog-to-digital conversion or otherwise.
This application claims the benefit of, and priority to, U.S. Provisional Application Ser. No. 62/203,214, filed Aug. 10, 2015, which is incorporated herein by reference in its entirety.
This invention was made in part with Government support under grant no. 1344531, awarded by the National Science Foundation, and grant no. N00014-14-1-0355 awarded by the Office of Naval Research. The U.S. government has certain rights in the invention.
| Number | Date | Country | |
|---|---|---|---|
| 62203214 | Aug 2015 | US |
