Patent Application
20190012948
The present disclosure relates to an active matrix display device and, more specifically, relates to an active matrix display device including a current-driven self-luminescent display elements, such as an organic EL display device, and a driving method therefor, and a pixel circuit in such a display device.
As display elements included in display devices, there have been known electrooptical elements in each of which luminescence is controlled using voltage applied to the electrooptical element and electrooptical elements in each of which luminescence is controlled using current passing through the electrooptical element. A representative example of the electrooptical element in which luminance is controlled using voltage applied to the electrooptical element is a liquid crystal display element. Meanwhile, a representative example of the electrooptical element in which luminance is controlled using current passing through the electrooptical element is an organic electroluminescence (EL) element. An organic EL element is also referred to as an organic light-emitting diode (OLED). Organic EL display devices using organic EL elements, which are self-luminescent electrooptical elements, can easily be reduced in thickness, reduced in power consumption, achieve high luminescence, and the like compared with liquid crystal display devices, which requires back light, color filters, and the like. Hence, the development of organic EL display devices has been actively pursued in recent years.
As a driving method for an organic EL display device, a passive matrix method (also referred to as a “simple matrix method”) and an active matrix method are known. Organic EL display devices adopting the passive matrix method have simple configurations while having difficulties in being increased in size and achieving higher resolution. In contrast, organic EL display devices adopting the active matrix method (referred to as “active-matrix organic EL display devices” below) can easily be increased in size and achieve higher resolution compared with the organic EL display devices adopting the passive matrix method.
In a general active matrix display device configured to display color images, a plurality of pixel circuits arranged in a matrix are provided. Each pixel of a display image is constituted by three sub pixels, i.e., an R sub pixel displaying red, a G sub pixel displaying green, and a B sub pixel displaying blue, and each of the sub pixels is formed by a single pixel circuit. In such an active-matrix organic EL display device, each of the pixel circuits includes: an organic EL element emitting any one of red, green, and blue lights; a capacitor holding a voltage as sub pixel data that determines the light emission intensity of the organic EL element; an input transistor as a switching element for controlling writing of sub pixel data to the capacitor; and a drive transistor controlling current supply to the organic EL element.
Some organic EL display devices are configured, for the purpose of reducing luminance variations in a display image due to variations in characteristics of the drive transistors, such that a current to be supplied to the organic EL element by each of the drive transistors (referred to as a “drive current” below) is taken out to an external unit of the corresponding pixel circuit to measure the drive current and that sub pixel data to be written into each of the pixel circuits is corrected on the basis of a result of the measurement to compensate the variations in characteristics. A method of compensating variations in characteristics of drive transistors by using such a configuration is referred to as an “external compensation method” below.
PTL 1 (WO 2014/021201) discloses an organic EL display device adopting such an external compensation method. In this organic EL display device, a data driver transmits, to a controller 10, first and second measurement data respectively corresponding to first and second measurement data voltages, and the controller updates threshold voltage correction data and gain correction data on the basis of the first and second measurement data Im while correcting image data on the basis of the threshold voltage correction data and the gain correction data. With this configuration, both threshold voltage compensation and gain compensation for a drive transistor are performed for each pixel circuit while performing display.
In relation to the present disclosure, PTL 2 (JP 2005-148749 A) discloses a pixel circuit having a configuration in which the number of transistors and the number of capacitors necessary for a single pixel are reduced compared with known configurations. This pixel circuit is constituted by a driver, a sequential controller, and three organic EL elements OLED (R), OLED (G), and OLED (B). The driver is constituted by a drive transistor, an input transistor, and a capacitor. The sequential controller is constituted by a transistor T13(R) controlling light emission of the organic EL element OLED(R) for red, a transistor T13(G) controlling light emission of the organic EL element OLED(G) for green, and a transistor T13(B) controlling light emission of the organic EL element OLED(B) for blue and is provided with emission lines EM1, EM2, and EM3 as wiring lines for sequentially turning on the transistors T13(R), T13(G), and T13(B) for light emission control.
PTL 1: WO 2014/021201 pamphlet
PTL 2: JP 2005-148749 A
In an organic EL display device adopting the external compensation method, each pixel circuit includes a transistor as a switching element for measurement of a drive current (referred to as a “monitor control transistor” below) in addition to the capacitor, the input transistor, and the drive transistor that are described above. In other words, each pixel circuit includes at least three transistors and one capacitor. Hence, each circuit forming each pixel constituted by three sub pixels includes at least nine transistors and three capacitors. For this reason, it is difficult to achieve higher resolution of a display image by such an organic EL display device. Moreover, such an organic EL display device needs to include a function for the measurement of a drive current and correction of sub pixel data, based on a result of the measurement (referred to as an “external compensation function” below) for each data signal line for transferring a voltage signal as sub pixel data from an external unit (driving circuit) to each pixel circuit, and thus the cost of an integrated circuit (IC) as a driving circuit increases.
In view of the above, an object of the present disclosure is to provide: a display device that is an active matrix display device using an external compensation method, the active matrix display device including a current-driven self-luminescent display element and that can display a high-resolution color image while suppressing an increase in cost; and a pixel circuit for the display device.
A first aspect of the disclosure is a pixel circuit provided in a display device including a plurality of data lines and a plurality of writing control lines intersecting with the plurality of data lines, the pixel circuit corresponding to any one of the plurality of data lines and to any one of the plurality of writing control lines, the pixel circuit including:
a prescribed number of display elements configured to emit light of a prescribed number of primary colors by being driven by currents, the prescribed number being three or more;
a prescribed number of light emission control transistors configured to serve as switching elements connected to the prescribed number of display elements in series and controlling lighting/lighting-out of the prescribed number of display elements;
a data holding capacity configured to hold data voltages for controlling drive currents of the prescribed number of display elements;
an input transistor configured to serve as a switching element including a control terminal connected to a corresponding one of the plurality of writing control lines and controlling voltage supply from corresponding data line of the plurality of data lines to the data holding capacity;
a drive transistor configured to supply a drive current corresponding to the data voltage to a display element connected to each of the light emission control transistors that is in an ON state among the prescribed number of display elements; and
a monitor control transistor configured to serve as a switching element disposed between a prescribed position in the pixel circuit and the corresponding data line to be able to transmit a current or a voltage in the pixel circuit to the corresponding data line.
A second aspect of the disclosure is a display device including:
a plurality of data lines;
a plurality of writing control lines intersecting with the plurality of data lines;
a plurality of pixel circuits according to the first aspect of the disclosure each corresponding to any one of the plurality of data lines and to any one of the plurality of writing control lines and disposed in a matrix along the plurality of data lines and the plurality of writing control lines;
a plurality of light emission control lines, a prescribed number of the plurality of light emission control lines being disposed for each of the plurality of writing control lines, the prescribed number being equal to the prescribed number of the light emission control transistors;
a plurality of monitor control lines corresponding to the plurality of writing control lines and disposed along the plurality of writing control lines, and each connected to a control terminal of the monitor control transistor in a corresponding one of the plurality of pixel circuits;
a data line driving circuit configured to apply a plurality of data signals to the plurality of data lines, the plurality of data signals representing a color image to be displayed;
a writing control line driving circuit configured to selectively drive the plurality of writing control lines;
a monitor control line driving circuit configured to drive the plurality of monitor control lines;
a light emission control line driving circuit configured to drive the plurality of light emission control lines and cause the prescribed number of light emission control transistors in each of the pixel circuits to sequentially turn into an ON state in each of frame periods;
a measurement circuit configured to measure a current or a voltage in each of the plurality of pixel circuits via the monitor control transistor in the pixel circuit and the data line corresponding to the pixel circuit; and
a drive control circuit configured to control the data line driving circuit, the writing control line driving circuit, the monitor control line driving circuit, and the light emission control line driving circuit.
A third aspect of the disclosure is that, in the second aspect of the disclosure,
in a case where the color image is displayed by the plurality of pixel circuits, the drive control circuit
divides each of the frame periods into a prescribed number of subframe periods corresponding to the prescribed number of primary colors,
controls the writing control line driving circuit and causes the plurality of writing control lines to sequentially turn into an active state in each of the subframe periods,
controls the data line driving circuit to apply, in each of the subframe periods, signals representing an image of a primary color corresponding to the subframe period among images of the prescribed number of primary colors constituting the color image, as the plurality of data signals, to the plurality of data lines,
controls the monitor control line driving circuit to maintain monitor control transistors in the plurality of pixel circuits in an OFF state, and
controls the light emission control line driving circuit to cause, in each of the subframe periods, only a light emission control transistor connected in series to the display element to emit a light in the primary color corresponding to the subframe period among the prescribed number of light emission control transistors in each of the plurality of pixel circuits, to change to an ON state while causing the prescribed number of light emission control transistors in each of the plurality of pixel circuits to sequentially turn into an ON state for prescribed time periods in each of the frame periods.
A fourth aspect of the disclosure, in the third aspect of the disclosure, further includes a selection signal generation circuit configured to generate a prescribed number of selection signals becoming active in the prescribed number of subframe periods in each of the frame periods,
wherein the light emission control line driving circuit includes
a plurality of demultiplexers corresponding to the plurality of writing control lines and each connected to the prescribed number of light emission control lines corresponding to corresponding one of the writing control lines,
a light emission control line activation circuit configured to output a plurality of light emission enable signals to the plurality of demultiplexers,
a plurality of pull-down transistors each functioning as a switching element provided for each of the plurality of light emission control lines and including a first conduction terminal and a second conduction terminal, the first conduction terminal being connected to corresponding light emission control line, the second conduction terminal being supplied with a prescribed voltage indicating an inactive state, and
a light emission control line deactivation circuit configured to control on/off of the plurality of pull-down transistors,
each of the plurality of demultiplexers includes a prescribed number of activation control transistors being a prescribed number of activation control transistors corresponding to the prescribed number of respective light emission control lines connected to the demultiplexer and each functioning as a switching element including a first conduction terminal and a second conduction terminal, the first conduction terminal being supplied with a light emission enable signal output from the light emission control line activation circuit to the demultiplexer, the second conduction terminal being connected to the corresponding one of the plurality of light emission control lines,
the selection signal generation circuit supplies the prescribed number of selection signals to respective control terminals of the prescribed number of activation control transistors in each of the plurality of demultiplexers, and
in a case where the color image is displayed by the plurality of pixel circuits, the drive control circuit
controls the light emission control line activation circuit and the selection signal generation circuit and causes the plurality of light emission control lines to sequentially turn into an active state to cause the light emission control transistors connected to the display elements of one of light emission colors in the plurality of pixel circuits to sequentially turn into an ON state in each subframe period corresponding to the light emission color, and
controls the light emission control line deactivation circuit and causes the plurality of light emission control lines caused to sequentially turn into the active state by the light emission control line activation circuit, to sequentially turn into an inactive state to thereby cause the prescribed number of light emission control transistors in each of the pixel circuits to sequentially turn into an ON state in the respective prescribed periods.
A fifth aspect of the disclosure is that, in the second aspect of the disclosure,
in a case of measuring a current or a voltage in each of the plurality of pixel circuits corresponding to any one writing control line of the plurality of writing control lines,
the drive control circuit controls the monitor control line driving circuit to cause only the monitor control transistor in each of the plurality of pixel circuits corresponding to the one writing control line to be in an ON state, and
the measurement circuit measures a current or a voltage of each of the plurality of pixel circuits corresponding to the one writing control line via the monitor control transistor in the pixel circuit and the data line corresponding to the pixel circuit.
A sixth aspect of the disclosure is that, in the fifth aspect of the disclosure,
in a case of measuring a current or a voltage in each of the plurality of pixel circuits corresponding to any one writing control line of the plurality of writing control lines, the drive control circuit controls the light emission control line driving circuit to cause at least the prescribed number of light emission control transistors of each of the plurality of pixel circuits corresponding to the one writing control line to be an OFF state.
A seventh aspect of the disclosure is that, in any one of the second to sixth aspects of the disclosure,
a transistor configuring each of the plurality of pixel circuits is a thin film transistor in which a channel layer is formed of an oxide semiconductor.
An eighth aspect of the disclosure is a driving method for a display device, the display device including
a plurality of data lines,
a plurality of writing control lines intersecting with the plurality of data lines,
a plurality of pixel circuits each corresponding to any one of the plurality of data lines and to any one of the plurality of writing control lines and disposed in a matrix along the plurality of data lines and the plurality of writing control lines,
a plurality of light emission control lines, a prescribed number of the plurality of light emission control lines being disposed for each of the plurality of writing control lines, the prescribed number being equal to the prescribed number of the light emission control transistors, and
a plurality of monitor control lines corresponding to the plurality of writing control lines and disposed along the plurality of writing control lines,
each of the plurality of pixel circuits including
a prescribed number of display elements configured to emit respective light of a prescribed number of primary colors by being driven by currents, the prescribed number being three or more,
a prescribed number of light emission control transistors configured to serve as switching elements connected to the prescribed number of display elements in series and controlling lighting/lighting-out of the prescribed number of display elements,
a data holding capacity configured to hold data voltages for controlling drive currents of the prescribed number of display elements,
an input transistor configured to serve as a switching element including a control terminal connected to the corresponding one of the plurality of writing control lines and controlling voltage supply from corresponding data line of the plurality of data lines to the data holding capacity,
a drive transistor configured to supply a drive current corresponding to the data voltage to a display element connected to each of the light emission control transistors that is in an ON state among the prescribed number of display elements, and
a monitor control transistor configured to serve as a switching element including a control terminal connected to the monitor control line, disposed along the corresponding writing control line disposed between a prescribed position in the pixel circuit and the corresponding data line to be able to transmit a current or a voltage in the pixel circuit to the corresponding data line, the driving method including:
a data line drive step of applying a plurality of data signals representing a color image to be displayed to the plurality of data lines;
a writing control line drive step of selectively driving the plurality of writing control lines;
a monitor control line drive step of driving the plurality of monitor control lines; and
a light emission control line drive step of driving the plurality of light emission control lines to cause the prescribed number of display elements in each of the plurality of pixel circuits to sequentially turn into a lit state in each of the frame periods.
Other aspects of the disclosure are apparent from descriptions of the above-described first to eighth aspects of the disclosure and embodiments to be described later, descriptions thereof are omitted.
In a display device including pixel circuits according to the first aspect of the disclosure, the prescribed number of display elements configured to emit lights of the prescribed number of primary colors are included in each of the pixel circuits, the prescribed number being three or more. The display element in a lit state is sequentially switched among the prescribed number of display elements in each pixel circuit in each frame period, and thereby a color image is displayed by sequential additive color mixture. With this configuration, the number of pixel circuits and the area of a display necessary to display a color image at certain resolution (number of pixels) can be significantly reduced in comparison with a known method of forming each pixel of a color image to be displayed by using a certain number of pixel circuits at the same resolution, the certain number being equal to the number of primary colors. Moreover, such a reduction in number of pixel circuits also reduces the number of data lines accordingly, and hence the contents of circuits in a data-side driving circuit is also significantly reduced. Moreover, in a case where the monitor control transistor is included in each pixel circuit to provide a configuration of measuring a current or a voltage in each pixel circuit as in the disclosure, i.e., a case of employing an external compensation method, a circuit (measurement unit circuit) for measurement is provided for each data line in the data-side driving circuit, and hence effects of the reduction in contents of circuits in the data-side driving circuit as a result of the reduction in number of pixel circuits as above are more significant. Hence, it is possible to significantly reduce not only the number of pixel circuits necessary to display a color image at the same resolution as that in a known case but also the contents of circuits in the data-side drive circuit, which makes it possible to display a high-resolution color image while suppressing an increase in cost in an active matrix display device using the external compensation method.
The display device according to the second aspect of the disclosure is an active matrix display device using the external compensation method including pixel circuits according to the first aspect of the disclosure and configured to display a color image in a field sequential method, and exerts similar effects to those according to the first aspect of the disclosure.
According to a third aspect of the disclosure, in a case where a color image is displayed on the basis of input signals from an external unit without measuring a current or a voltage in each pixel circuit (in a case of acting in a normal display mode), each frame period is divided into a prescribed number of subframe periods corresponding to the prescribed number of primary colors, the plurality of writing control lines are sequentially turned into an active state in each subframe period while signals representing an image of the primary color corresponding to the subframe period are applied to the plurality of data lines as a plurality of data signals, and each pixel data indicating the image of the primary color is written into the corresponding pixel circuit and held as a data voltage. Moreover, the prescribed number of light emission control transistors in each pixel circuit are sequentially turned into an ON state at respective prescribed intervals in each frame period. Consequently, the prescribed number of display elements in each pixel circuit are sequentially turned into a lit state for respective prescribed periods (one subframe periods, normally) to emit light at the intensity corresponding to the written pixel data. In this way, the color image represented by the input signals is displayed by sequential additive color mixture. The display device according to the third aspect of the disclosure for displaying a color image in a field sequential method is also an active matrix display device using the external compensation method including pixel circuits according to the first aspect of the disclosure, and exerts similar effects to those according to the first or second aspect of the disclosure.
In the fourth aspect of the disclosure, the light emission control line driving circuit is configured by one demultiplexer provided so as to correspond to each writing control line, the light emission control line activation circuit configured to output a light emission enable signal to each demultiplexer, one pull-down transistor provided for each light emission control line, and the light emission control line deactivation circuit configured to control on/off of each pull-down transistor. Each light emission enable signal output from the light emission control line activation circuit is supplied to the prescribed number of light emission control lines in a time division manner by the prescribed number of activation control transistors included in the demultiplexer, on the basis of selection signals from the selection signal generation circuit. With this configuration, the plurality of light emission control lines are sequentially turned into an active state, and thereby the light emission control transistors connected to the display elements of a certain light emission color in the pixel circuits are sequentially turned into an ON state in each subframe period corresponding to the light emission color. Light emission control lines sequentially turned into an active state are sequentially turned into an inactive state by the pull-down transistors connected to the light emission control lines being turned on by the light emission control line deactivation circuit. Consequently, the prescribed number of light emission control transistors in each pixel circuit are sequentially turned into an ON state at respective prescribed intervals. According to the fourth aspect of the disclosure, similar effects to those of the third aspect of the disclosure can be obtained, and also a color image can be displayed in a similar field sequential method to that of the third aspect of the disclosure while the light emission line control driving circuit is implemented by relatively small contents of circuits.
According to the fifth aspect of the disclosure, in a case of measuring a current or a voltage in each pixel circuit corresponding to any one writing control line, only the monitor control transistor in each pixel circuit corresponding to the one writing control line is turned into an ON state, and the measurement circuit measures a current or a voltage in each pixel circuit corresponding to the one writing control line via the monitor control transistor in the pixel circuit and the data line corresponding to the pixel circuit. The display device according to the fifth aspect of the disclosure for thus measuring a current or a voltage in the pixel circuit is also an active matrix display device using the external compensation method including pixel circuits according to the first aspect of the disclosure, and exerts similar effects to those according to the first or second aspect of the disclosure.
According to the sixth aspect of the disclosure, in a case of measuring a current or a voltage in each pixel circuit corresponding to any one writing control line, at least the light emission control transistors in each pixel circuit corresponding to the one writing control line are all turned into an OFF state. Consequently, the drive transistor in the pixel circuit are electrically separated from any display element, and hence a current or a voltage associated with the drive transistor can be measured more reliably and accurately.
According to the seventh aspect of the disclosure, the transistor configuring each pixel circuit is a thin film transistor in which a channel layer is formed of an oxide semiconductor, and hence power consumption can be reduced in comparison with a case of using thin film transistors of other kinds while similar effects to those in any of the second to sixth aspects of the disclosure can be obtained. Moreover, leak current in the monitor control transistor in each pixel circuit can be extremely small, and hence a current or a voltage in each pixel circuit can be measured at high accuracy.
The eighth aspect of the disclosure exerts similar effects to those of the first or second aspect of the disclosure.
Since effects of other aspects of the disclosure are apparent from descriptions of the effects of the first to eighth aspects of the disclosure and embodiments to be described later, descriptions thereof are omitted.
Embodiments of the present invention will be described below with reference to the accompanying drawings. Note that in each of transistors to be mentioned below, a gate terminal corresponds to a control terminal, and one of a drain terminal and a source terminal corresponds to a first conduction terminal while the other corresponds to a second conduction terminal.
The organic EL panel 6 is supplied with a high level supply voltage VDD and a low level supply voltage VSS necessary for actions of the writing control line driving circuit 300 from the logic power source 610, supplied with a high level supply voltage VDD and a low level supply voltage VSS necessary for actions of the monitor control line driving circuit 400 from the logic power source 620, and supplied with a high level supply voltage VDD and a low level supply voltage VSS necessary for actions of the light emission control line driving circuit 350 from the logic power source 630. Moreover, the organic EL panel 6 is supplied with a high level supply voltage ELVDD from the organic EL high level power source 650 and supplied with a low level supply voltage ELVSS from the organic EL low level power source 640. Note that the high level supply voltage VDD, the low level supply voltage VSS, the organic EL high level supply voltage ELVDD, and the organic EL low level supply voltage ELVSS are all constant voltages (direct-current voltages). In the following, power source lines for supplying the high level supply voltage VDD, the low level supply voltage VSS, the high level supply voltage ELVDD, and the low level supply voltage ELVSS are also denoted respectively by the reference signs “VDD”, “VSS”, “ELVDD”, and “ELVSS”.
Note that, in the following, in a case where the m data lines SL1 to SLm do not need to be distinguished from each other, the data lines are simply denoted by a reference sign “SL”. Similarly, the writing control lines, the monitor control lines, the first light emission control lines, the second light emission control lines, and the third light emission control lines are simply denoted respectively by reference signs “G1_WL”, “G2_Mon”, “EM1”, “EM2”, and “EM3” in some cases. The first to third light emission control lines EM1 to EM3 are also referred to simply as a “light emission control line” collectively. The light emission control lines are denoted by a reference sign “EM”. In addition, in the following, it is assumed that each transistor (the input transistor T1 in each pixel circuit 50) with a gate terminal connected to the corresponding writing control line G1_WL is in an ON state in a case where the writing control line G1_WL is in an active state (a state in which a high level voltage is supplied in the present embodiment) while being in an OFF state in a case where the writing control line G1_WL is in an inactive state (a state in which a low level voltage is supplied, in the present embodiment). Similarly, it is assumed that a transistor (the monitor control transistor Tm in each pixel circuit 50) with a gate terminal connected to the corresponding monitor control line G2_Mon is in an ON state in a case where the monitor control line G2_Mon is in an active state while being in an OFF state in a case where the monitor control line G2_Mon is in an inactive state. In addition, it is assumed that a transistor (each of the light emission control transistors T3 to T5 in each pixel circuit 50) with a gate terminal connected to the corresponding light emission control line EM is in an ON state in a case where the light emission control line EM is in an active state (a state in which a high level voltage is supplied in the present embodiment) while being in an OFF state in a case where the light emission control line EM is in an inactive state (a state in which a low level voltage is supplied, in the present embodiment).
The display control circuit 100 is typically implemented as an integrated circuit (IC). As illustrated in
On the basis of this input signal Sin, the drive controller 110 outputs a writing control signal WCTL for controlling actions of the writing control line driving circuit 300, a monitor control signal MCTL and a monitor enable signal Mon_EN for controlling actions of the monitor control line driving circuit 400, a light emission control signal ECTL for controlling actions of a light emission control line driving circuit 350, a source control signal SCTL for controlling actions of the data-side driving circuit 200, and a light emission switching indication signal Sem for controlling actions of the light emission control signal input switching circuit 360, and also outputs, in the display control circuit 100, a display data signal DA based on the RGB video data signal Din and a gray scale position indication signal PS to be described later. The writing control signal WCTL includes a start pulse signal GSP, a clock signal CLK1, and a clock signal CLK2, to be described later. The monitor control signal MCTL includes a start pulse signal MSP, a clock signal CLK3, and a clock signal CLK4, to be described later. The light emission control signal ECTL includes an activation start pulse signal ESPa, first to third deactivation start pulse signals ESPd1 to ESPd3, the clock signal CLK1, the clock signal CLK2, and a subframe reset signal SUBF_RST, to be described later. The source control signal SCTL includes a start pulse signal SSP, a clock signal SCK, a latch strobe signal LS, and an input/output control signal DWT, to be described later. Note that the monitor enable signal Mon_EN is a signal for controlling whether to enable measurement of a drive current.
The correction data calculator/storage 120 holds correction data to be used for correction of the display data signal DA. The correction data is constituted by an offset value and a gain value. The correction data calculator/storage 120 receives the gray scale position indication signal PS and a monitor voltage Vmo, which is a result of current measurement in the data-side driving circuit 200, and updates the correction data.
The gray scale correction unit 130 performs correction on the display data signal DA output from the drive controller 110 by using correction data DH held in the correction data calculator/storage 120 and outputs the data obtained through the correction as a digital video signal DV. A more detailed description of the constituent elements in the display control circuit 100 will be given later.
The data-side driving circuit 200 selectively performs actions for driving the data lines SL1 to SLm, i.e., actions as the data line driving circuit 210, and actions for measuring a drive current output from each pixel circuit 50 to the corresponding one of the data lines SL1 to SLm, i.e., actions as the current measurement circuit 220. Note that, as described above, the correction data calculator/storage 120 holds an offset value and a gain value as correction data. To update the correction data, measurement of a drive current is performed in the data-side driving circuit 200 on the basis of two kinds of gray scales (a first gray scale P1 and a second gray scale P2: P2>P1).
In the present embodiment, action modes include a normal display mode, in which an image is displayed on the display 500 on the basis of the input signal Sin, and a current measurement mode, in which a current passing through a drive transistor to be described later in each of the pixel circuits 50 connected to either one of the writing control line G1_WL(i) and the monitor control line G2_Mon(i) in one frame period is measured as a drive current. Switching of the action mode between the normal display mode and the current measurement mode may be enabled by including a mode control signal Cm indicating a certain action mode in the input signal Sin or may be enabled by providing a switch for manually switching the action mode in the organic EL display device and thereby generating a mode control signal Cm in accordance with an operation performed on the switch.
In the normal display mode, each of frame periods is divided into the number of subframe periods, the number being equal to the number of primary colors for color image display, i.e., three subframe periods, and pixel data is written into each pixel circuit 50 by sequentially causing the writing control lines G1_WL(1) to G1_WL(n) to turn into an active state in the subframe periods. In the current measurement mode, pixel data is written into each pixel circuit 50 by sequentially causing the writing control lines G1_WL(1) to G1_WL(n) to turn into an active state in the frame periods without dividing each frame period into a plurality of subframe periods, and a current passing through the drive transistor to be described later in each pixel circuit 50 connected to either one of the writing control line G1_WL(i) and the monitor control line G2_Mon(i) in one frame period is measured as a drive current. Note that in the following, a period in which actions for writing pixel data into the pixel circuit 50 in any of the current measurement mode and the normal display mode are performed is referred to as a “normal action period”, and the period in which actions for detecting characteristics of the drive transistor by measuring a drive current in the current measurement mode are performed is referred to as a “characteristics detection process period”. The data-side driving circuit 200 acts as a data line driving circuit 210 in the normal action period while acting as a current measurement circuit 220 in a period of measuring a current passing through each drive transistor (referred to as a “current measurement period” below) in the characteristics detection process period. In the normal display mode, each subframe period is constituted only by the normal action period; meanwhile, in the current measurement mode, each frame period is constituted by the normal action period and the characteristics detection process period including the current measurement period (to be described later in detail).
The writing control line driving circuit 300 drives the writing control lines G1_WL(1) to G1_WL(n) on the basis of the writing control signal WCTL from the display control circuit 100. The monitor control line driving circuit 400 drives the monitor control lines G2_Mon(1) to G2_Mon(n) on the basis of the monitor control signal MCTL and the monitor enable signal Mon_EN from the display control circuit 100 (to be described later in detail). Note that the monitor control line driving circuit 400 sets the monitor enable signal Mon_EN at inactive (low level) in the normal action period to cause all the monitor control lines G2_Mon(1) to G2_Mon(n) to change to an inactive state, i.e., a low level.
The light emission control line driving circuit 350 outputs light emission enable signals to be supplied to the light emission control lines EM1(1) to EM1(n), EM2(1) to EM2(n), and EM3(1) to EM3(n), on the basis of the light emission control signal ECTL from the display control circuit 100 and selection signals SEL1 to SEL3 to be described later output from the light emission control signal input switching circuit 360. The light emission control line driving circuit 350 will be described later in detail.
The light emission control signal input switching circuit 360 outputs the first to third selection signals SEL1, SEL2, and SEL3 on the basis of the light emission switching indication signal Sem from the display control circuit 100, and functions as a selection signal generation circuit. In the present embodiment, as has been already described above, each frame period is divided into the number of subframe periods that is equal to the number of primary colors for color image display, i.e., three subframe periods including first to third subframe periods. The first to third selection signals SEL1, SEL2, and SEL3 are sequentially changed to active (high level) in respective subframe periods. Hence, the first selection signal SEL1 is in a high level in the first subframe period, the second selection signal SEL2 is in a high level in the second subframe period, and the third selection signal SEL3 is in a high level in the third subframe period.
As will be described later, one pixel circuit row is a unit of measurement target (this measurement target pixel circuit row is also referred to as a “compensation target row” below) in the current measurement period. Here, the pixel circuit row is a pixel circuit group constituted by m pixel circuits 50 aligned along a direction in which the writing control line G1_WL(i) extends (horizontal direction) in the display 500 and is also referred to simply as a “row” below. In the current measurement mode, to perform measurement more reliably and accurately, at least first to third light emission control lines EM1(It), EM2(It), and EM3(It) corresponding to the compensation target row are preferably in an inactive state (a state where a low level voltage is supplied). In the present embodiment, all the light emission control lines EM1(1) to EM1(n), EM2(1) to EM2(n), and EM3(1) to EM3(n) are in an inactive state in the current measurement mode. Consequently, in each of all the pixel circuits 50, the drive transistor is electrically separated from the organic EL elements, and all the organic EL elements are in a lit-out state. Moreover, in the current measurement mode, the monitor control line driving circuit 400 supplies an active signal (a high level voltage in the present embodiment) to the monitor control line G2_Mon(It) corresponding to the compensation target row, to cause the monitor control line G2_Mon(It) to be in an active state.
The constituent elements act as described above to drive the data lines SL1 to SLm, the writing control lines G1_WL(1) to G1_WL(n), the monitor control lines G2_Mon(1) to G2_Mon(n), and the light emission control lines EM1(1) to EM1(n), EM2(1) to EM2(n), and EM3(1) to EM3(n), whereby an image is displayed on the display 500 in the normal display mode, and a drive current in the measurement target pixel circuit 50 is measured in the current measurement period in the current measurement mode. In the present embodiment, correction is made to the display data signal DA on the basis of a result of measurement of drive currents, which compensates variations in characteristics of the drive transistors.
The R pixel circuit 50r includes an organic EL element OLED as one light emitting type display element emitting red light, three N channel type transistors (each referred to briefly as an “Nch transistor” below) T1, T2, and Tm, and one capacitor Cst. The transistor T1 functions as an input transistor with a gate terminal connected to the writing control line G1_WL(i) to select the pixel, the transistor T2 functions as a drive transistor controlling supply of a current to the organic EL element OLED according to the voltage held by the capacitor Cst, and the transistor Tm functions as a monitor control transistor with a gate terminal connected to the monitor control line G2_Mon(i) to control whether to perform current measurement for detection of characteristics of the drive transistor. The capacitor Cst functions as a data holding capacity for holding a data voltage indicating the value of the R sub pixel (luminance value) (this capacitor is also referred to as a “data holding capacity” below). The G pixel circuit 50g includes an organic EL element (OLED) emitting green light, instead of the OLED configured to emit red light, but otherwise has a similar configuration to that of the R pixel circuit 50r. The B pixel circuit 50b includes an organic EL element (OLED) emitting blue light, instead of the OLED configured to emit red light, but otherwise has a similar configuration to that of the R pixel circuit 50r.
The data-side driving circuit 200 in this known organic EL display device includes output terminals Torj, Togj, and Tobj to which the data lines SLrj, SLgj, and SLbj are connected respectively (j=1 to m) as illustrated in
In the known organic EL display device as that described above, display of an image configured by n*m pixels requires 3*n*m pixel circuits 50x and 3m data-side unit circuits 211, and each one of the pixel circuits 50x (x=r, g, b) is constituted by three transistors T1, T2, Tm, one capacitor Cst, and one organic EL element OLED.
Each pixel circuit 50 includes one display element group constituted by first to third organic EL elements OLED configured to emit red light, green light, and blue light respectively (indicated by respective reference signs “OLED(R)”, “OLED(G)”, and “OLED(B)” below when distinguishing the organic EL elements from each other), six Nch transistors T1 to T5 and Tm, and one capacitor Cst. The transistor T1 functions as an input transistor configured to select a pixel, the transistor T2 functions as a drive transistor configured to control current supply to the organic EL element selected by the light emission control transistors T3 to T5 to be described later among the three organic EL elements OLED(R), OLED(G), and OLED(B), the transistor Tm functions as a monitor control transistor configured to control whether to perform current measurement for detection of characteristics of the drive transistor, and the transistors T3 to T5 function as light emission control transistors. The capacitor Cst functions as a data holding capacity for holding a data voltage indicating pixel data (a voltage indicating the value (luminance) of a red pixel, a green pixel, or a blue pixel). Note that all the transistors other than the transistor T2 among the transistors T1 to T5 and Tm in each pixel circuit 50 act as switching elements.
The input transistor T1 is disposed between the data line SLj and the gate terminal of the transistor T2. The gate terminal and a source terminal of the input transistor T1 are connected respectively to the writing control line G1_WL(i) and the data line SLj. The drive transistor T2 includes a drain terminal connected to the high level power source line ELVDD, and the data holding capacity Cst is connected between the drain terminal and the gate terminal of the drive transistor T2. A source terminal of the drive transistor T2 is connected to the data line SLj via the monitor control transistor Tm, and the monitor control line G2_Mon(i) is connected to the gate terminal of the monitor control transistor Tm.
The drive transistor T2 is connected to each of the first to third organic EL elements OLED(R), OLED(G), and OLED(B) in series and is also connected to the first to third light emission control transistors T3 to T5 in series. Specifically, the first light emission control transistor T3 is connected to the first organic EL element OLED(R) in series to control supply/block of a drive current to the first organic EL element OLED(R), the second light emission control transistor T4 is connected to the second organic EL element OLED(G) in series to control supply/block of a drive current to the second organic EL element OLED(G), and the third light emission control transistor T5 is connected to the third organic EL element OLED(B) in series to control supply/block a drive current to the third organic EL element OLED(B). In the example illustrated in
The first to third light emission control lines EM1(i), EM2(i), and EM3(i) are connected to the respective gate terminals of the first to third light emission control transistors T3 to T5. As has already been described, a light emission enable signal GGem(i) generated by the light emission control line driving circuit 350 is supplied to the first to third light emission control lines EM1(i), EM2(i), and EM3(i) in a time division manner by a demultiplexer 342 in the light emission control line driving circuit 350 (refer to
In the present embodiment, the transistors T1 to T5 and Tm in the pixel circuit 50 are all N-channel type but may adopt a configuration using a P-channel type TFT. A thin film transistor (abbreviated as “TFT” below) in which a channel layer is formed of an oxide semiconductor, is adopted as each of the transistors T1 to T5 and Tm. The same applies to the transistors in the writing control line driving circuit 300, the monitor control line driving circuit 400, and the light emission control line driving circuit 350. The present invention is also applicable to a configuration using transistors each of which includes a channel layer made of amorphous silicon, polysilicon, microcrystalline silicon, continuous grain silicon (continuous grain silicon), or the like.
An oxide semiconductor layer included in each TFT used in the present embodiment is, for example, an In—Ga—Zn—O based semiconductor layer. The oxide semiconductor layer includes an In—Ga—Zn—O based semiconductor, for example. The In—Ga—Zn—O based semiconductor is ternary oxide of indium (In), gallium (Ga), and zinc (Zn). The ratio (composition ratio) of In, Ga, and Zn is not particularly limited. For example, the ratio may be In:Ga:Zn=2:2:1, In:Ga:Zn=1:1:1, In:Ga:Zn=1:1:2, or the like. A TFT including the In—Ga—Zn—O based semiconductor layer has high mobility (20 times greater mobility than that of an amorphous silicon TFT) and small leak current (leak current smaller than 1/100 of that of an amorphous silicon TFT) and is hence preferably used as each of the transistors T1 to T5 and Tm in the pixel circuit 50. In the present embodiment, not only the pixel circuit 50 corresponding to one monitor control line G2_Mon that is in an active state in the current measurement mode but also the pixel circuits 50 corresponding to n−1 monitor control lines G2_Mon in an inactive state are connected to each of the data lines SLj. Hence, using, as the monitor control transistor Tm, a TFT having a minimal leak current as described above is particularly effective to increase the accuracy in current measurement for detection of the characteristics of the drive transistor T2 in each pixel circuit 50.
The data-side driving circuit 200 in the present embodiment includes one data-side unit circuit 211 for each of the data lines SL1 to SLm as illustrated in
As is apparent from comparison between
With the above-described configuration, the first and second switches 24 and 25 correspond to the switching switch SW in the data-side unit circuit 211 illustrated in
In contrast, when the input/output control signal DWT is in a low level, the first switch 24 is in an off state while the second switch 25 outputs the low level supply voltage ELVSS. Through this operation, the noninverting input terminal and the output terminal of operational amplifier 22 are connected via the resistance element R1 to supply the low level supply voltage ELVSS to the noninverting input terminal of the operational amplifier 22. Consequently, the operational amplifier 22 outputs a voltage corresponding to a drive current output to the data line SLj from the pixel circuit 50 connected to the monitor control line G2_Mon(i) supplied with a high level voltage among the pixel circuits 50 connected to the data line SLj. The output voltage from the operational amplifier 22 is converted into a digital value by the AD converter 23 and is then output as a monitor voltage vmoj. The monitor voltage vmoj output from each of the data-side unit circuit 211 is transmitted to the correction data calculator/storage 120 in the display control circuit 100 as a current measurement result Vmo obtained in the current measurement circuit 220.
As descried above, the data-side unit circuit 211 functions as the current measurement unit circuit 211m in the current measurement period due to the input/output control signal DWT turned into a low level, while functioning as the data voltage output unit circuit 211d in each period other than the current measurement period due to the input/output control signal DWT turned into a high level. Hence, the data-side driving circuit 200 functions as the current measurement circuit 220 in the current measurement period while functioning as the data line driving circuit 210 in each period other than the current measurement period.
Next, a detailed configuration and actions of the display control circuit 100 in the present embodiment will be described.
The status machine 115 is a sequential circuit for which an output signal and the next interior state are determined on the basis of an input signal and the current interior state, and performs concrete actions as follows. Specifically, the status machine 115 outputs a control signal 51, a control signal S2, a monitor enable signal Mon_EN, and a light emission switching indication signal Sem on the basis of the external clock signal CLKin and a matching signal MS. Moreover, the status machine 115 outputs a clear signal CLR for initializing the writing line counter 111 and a clear signal CLR2 for initializing the matching counter 114. Further, the status machine 115 outputs a rewrite signal WE for updating a compensation target line address Addr stored in the compensation target line address storage memory 112.
In the compensation target line address storage memory 112 in the drive controller 110 illustrated in
The matching circuit 113 determines whether the writing count value CntWL output from the writing line counter 111 and the compensation target line address Addr stored in the compensation target line address storage memory 112 match, and outputs the matching signal MS indicating a result of the determination. Note that the writing count value CntWL and the compensation target line address Addr are represented by the same number of bits. In the present embodiment, when the writing count value CntWL and the compensation target line address Addr match, the matching signal MS is set at a high level; when the writing count value CntWL and the compensation target line address Addr do not match, the matching signal MS is set at a low level. The matching signal MS output from the matching circuit 113 is supplied to the status machine 115 and the matching counter 114.
In the present embodiment, the writing control lines G1_WL sequentially turn into an active state on the basis of the clock signals CLK1 and CLK2 after the occurrence of a pulse of the start pulse signal GSP. Moreover, the writing count value CntWL output from the writing line counter 111 is incremented by 1 on the basis of the clock signals CLK1 and CLK2. Accordingly, the writing count value CntWL represents the value of the row of the writing control line G1_WL to be turned into an active state. For example, assume that the clock signal CLK1 rises at a certain time point tx and the writing count value CntWL changes to “50”. Then, the 50-th writing control line G1_WL(50) is in an active state for one horizontal interval from the time point tx. Moreover, the compensation target line address Addr indicating the compensation target row is stored in the compensation target line address storage memory 112, and hence the time point at which the writing count value CntWL and the compensation target line address Addr match is the start time point of the characteristics detection process period.
In the drive controller 110 illustrated in
The image data/source control signal generation circuit 116 outputs the source control signal SCTL and the display data signal DA on the basis of the RGB video data signal Din included in the input signal Sin from an external unit and a control signal 51 supplied from the status machine 115. Note that the control signal 51 includes a signal indicating, for each frame period, whether to start a compensation process (a series of operations for compensating variations in characteristics of the drive transistors) or to start normal actions. The gate control signal generation circuit 117 outputs the writing control signal WCTL, the monitor control signal MCTL, and the light emission control signal ECTL on the basis of the control signal S2 provided from the status machine 115. Note that the control signal S2 includes a signal based on the external clock signal CLKin included in the input signal Sin, for example, a signal controlling clock actions of the clock signals CLK1 to CLK4, and a signal indicating output of each pulse of a start pulse signal GSP and MSP, an activation start pulse signal ESPa, and first to third deactivation start pulse signals ESPd1 to ESPd3.
The gray scale correction unit 130 included in the display control circuit 100 in the configuration illustrated in
As illustrated in
The transistor T31 is connected, at the gate terminal and the drain terminal thereof, to the input terminal 31 (i.e., a diode connection is established) and is connected, at the source terminal thereof, to the first node N1. The transistor T32 is connected, at the gate terminal thereof, to the first node N1, is connected, at the drain terminal thereof, to the input terminal 33, and is connected, at the source terminal thereof, to the output terminal 38. The transistor T33 is connected, at the gate terminal thereof, to the input terminal 32, is connected, at the drain terminal thereof, to the output terminal 38, and is connected, at the source terminal thereof, the low level supply voltage VSS input terminal. The transistor T34 is connected, at the gate terminal thereof, to the input terminal 32, is connected, at the drain terminal thereof, to the first node N1, and is connected, at the source terminal thereof, to the low level supply voltage VSS input terminal.
Next, a function of the unit circuit 30 will be described. When the set signal S is changed to a high level, the transistor T31 changes the electric potential of the first node N1 toward a high level. When the electric potential of the first node N1 is at or near the high level, the transistor T32 supplies the electric potential of the clock signal VCLK to the output terminal 38. When the reset signal R is changed to a high level, the transistor T33 changes the electric potential of the output terminal 38 toward the electric potential of the low level supply voltage VSS. When the reset signal R is changed to a high level, the transistor T34 changes the electric potential of the first node N1 toward the electric potential of the low level supply voltage VSS.
Basic actions of the unit circuit 30 will be described with reference to
At the time point t20, a pulse of the set signal S is supplied to the input terminal 31. The transistor T31 has a diode connection as illustrated in
At a time point t21, the clock signal VCLK changes from a low level to a high level. At the time of the change, the reset signal R is in a low level, and hence the transistor T34 is in an OFF state. Hence, the first node N1 turns into a floating state. As described above, the parasitic capacitance Cgd is formed between the gate terminal and the drain terminal of the transistor T32, and the parasitic capacitance Cgs is formed between the gate terminal and the source terminal of the transistor T32. With this configuration, the electric potential of the first node N1 increases significantly due to a bootstrap effect. As a result of the increase, a high voltage is applied to the gate terminal of the transistor T32. Consequently, the electric potential of the state signal Q (electric potential of the output terminal 38) increases to the high level electric potential of the clock signal VCLK. Note that, in the period from the time point t21 to a time point t22, the reset signal R is in a low level. Accordingly, the transistor T33 is maintained in an OFF state, so that the electric potential of the state signal Q does not decrease during this period.
At the time point t22, the clock signal VCLK changes from a high level to a low level. Consequently, the electric potential of the state signal Q decreases together with a decrease in the electric potential of the input terminal 33, and the electric potential of the first node N1 also decreases via the parasitic capacitances Cgd and Cgs. In addition, at the time point t22, a pulse of the reset signal R is supplied to the input terminal 32. In response to this, the transistor T33 and the transistor T34 turn into an ON state. The change of the transistor T33 into an ON state causes the electric potential of the state signal Q to decrease to a low level, and the change of the transistor T34 into an ON state causes the electric potential of the first node N1 to decrease to a low level.
By taking account of the above-described actions of the unit circuit 30 and the configuration of the shift register 3 illustrated in
Note that the configuration of the unit circuit 30 is not limited to the configuration illustrated in
As illustrated in
As described above, the unit circuit 40 has a similar configuration as that of the unit circuit 30 except for the respect that the output terminal 49 and the transistor T49 are provided. Moreover, the clock signals CLK3 and CLK4 having the waveforms illustrated in
Here, a description will be given of how the monitor enable signal Mon_EN is supplied to the transistor T49 in the unit circuit 40, with reference to
Note that the value or symbol in parentheses attached immediately after each of reference signs indicating constituent components and signals of a unit circuit in a shift register constituting the light emission control line activation circuit 350a, the first to third light emission control line deactivation circuits 350d1 to 350d3, and the like is assumed to indicate the position of the unit circuit in the shift register. Specifically, a reference sign to which “(i)” is attached immediately after indicates a constituent element or a signal in the i-th unit circuit in the shift register.
The shift register 35asr configuring the light emission control line activation circuit 350a is supplied with two-phase clock signals CLK1 and CLK2 as a light emission control clock signal ECK. Here, the clock signals CLK1 and CLK2 are the same as the clock signals CLK1 and CLK2 included in the writing control signal WCTL (refer to
Signals supplied to the input terminals of each stage (each unit circuit) of the shift register 35asr are as follows. At each odd-numbered stage, the first clock signal CLK1 is supplied as the clock signal VCLK. At each odd-numbered stage, the second clock signal CLK2 is supplied as the clock signal VCLK. Moreover, at a certain stage, the first output signal Q1 output from the previous stage is supplied as the set signal S, and the first output signal Q1 output from the subsequent stage is supplied as the first reset signal R1. However, for the first stage, the activation start pulse signal ESPa is provided as the set signal S. Moreover, a subframe reset signal SUBF_RST is provided to all the stages in common as the second reset signal R2.
In the configuration as described above, when a pulse of the activation start pulse signal ESPa as the set signal S is supplied to the first stage of the shift register 35asr, the shift pulse included in the first output signal Q1 output from each stage is sequentially transferred from the first stage to the n-th stage on the basis of the first clock signal CLK1 and the second clock signal CLK2. In response to the transfer of the shift pulse, the first output signals Q1 output from the respective stages sequentially change to a high level, and the second output signals Q2 output from the respective stages sequentially change to high level. Note that the second output signal Q2 output from each stage is supplied to the corresponding light emission control line EM as the light emission enable signal GGem via the demultiplexing circuit 340.
The transistor M1 is connected, at the gate terminal and the drain terminal thereof, to the input terminal 41 (i.e., a diode connection is established) and is connected, at the source terminal thereof, to the first node N1. The transistor M2 is connected, at the gate terminal thereof, to the first node N1, is connected, at the drain terminal thereof, to the input terminal 43, and is connected, at the source terminal thereof, to the output terminal 48. The transistor M3 is connected, at the gate terminal thereof, to the first node N1, is connected, at the drain terminal thereof, to the high level supply voltage VDD input terminal, and is connected, at the source terminal thereof, to the output terminal 49. The transistor M4 is connected, at the gate terminal thereof, to the input terminal 42, is connected, at the drain terminal thereof, to the output terminal 48, and is connected, at the source terminal thereof, to the low level supply voltage VSS input terminal. The transistor M5 is connected, at the gate terminal thereof, to the input terminal 42, is connected, at the drain terminal thereof, to the first node N1, and is connected, at the source terminal thereof, to the low level supply voltage VSS input terminal. The transistor M6 is connected, at the gate terminal thereof, to the input terminal 44, is connected, at the drain terminal thereof, to the output terminal 49, and is connected, at the source terminal thereof, to the low level supply voltage VSS input terminal.
Next, a function of each of constituent elements in this unit circuit 35a will be described. When the set signal S changes to a high level, the transistor M1 changes the electric potential of the first node N1 toward a high level. When the electric potential of the first node N1 at or near the high level, the transistor M2 supplies the electric potential of the clock signal VCLK to the output terminal 48. When the electric potential of the first node N1 at or near the high level, the transistor M3 supplies the electric potential of the high level supply voltage VDD to the output terminal 49. When the first reset signal R1 changes to a high level, the transistor M4 changes the electric potential of the output terminal 48 toward the electric potential of the low level supply voltage VSS. When the first reset signal R1 changes to a high level, the transistor M5 changes the electric potential of the first node N1 toward the electric potential of the low level supply voltage VSS. When the second reset signal R2 changes to a high level, the transistor M6 changes the electric potential of the output terminal 49 toward the electric potential of the low level supply voltage VSS.
Next, a description will be given of actions of the unit circuit 35a in the present embodiment with reference to
At the time point t10, a pulse of the set signal S is supplied to the input terminal 41. The transistor M1 has a diode connection as illustrated in
At a time point t11, the clock signal VCLK changes from a low level to a high level. At the time of the change, the first reset signal R1 is in a low level, and hence the transistor M5 is in an OFF state. Hence, the first node N1 turns into a floating state. As described above, the parasitic capacitance Cgd is formed between the gate terminal and the drain terminal of the transistor M2, and the parasitic capacitance Cgs is formed between the gate terminal and the source terminal of the transistor M2. With this configuration, the electric potential of the first node N1 increases significantly due to a bootstrap effect. As a result of the increase, a high voltage is applied to the transistor M2 and the transistor M3. Consequently, the electric potential of the first output signal Q1 (electric potential of the output terminal 48) increases to the high level electric potential of the clock signal VCLK, and the electric potential of the second output signal Q2 (electric potential of the output terminal 49) increases to the electric potential of the high level supply voltage VDD. Note that, in the period from the time point t11 to the time point t12, the first reset signal R1 is in a low level. Accordingly, the transistor M4 is maintained in an OFF state, so that the electric potential of the first output signal Q1 does not decrease during this period. Note that, in the period from the time point t11 to the time point t12, the second reset signal R2 is in a low level. Accordingly, the transistor M6 is maintained in an OFF state, so that the electric potential of the second output signal Q2 does not decrease during this period.
At the time point t12, the clock signal VCLK changes from a high level to a low level. Consequently, the electric potential of the first output signal Q1 decreases together with a decrease in the electric potential of the input terminal 43, and the electric potential of the first node N1 also decreases via the parasitic capacitances Cgd and Cgs. In addition, at the time point t12, a pulse of the first reset signal R1 is supplied to the input terminal 42. In response to this, the transistor M4 and the transistor MS turn into an ON state. The change of the transistor M4 into an ON state causes the electric potential of the first output signal Q1 to decrease to a low level, and the change of the transistor MS into an ON state causes the electric potential of the first node N1 to decrease to a low level. Note that, the decrease of the electric potential of the first node N1 to a low level causes the transistor M3 to turn into an OFF state, but the second reset signal R2 is maintained in a low level until a time point t13. Thus, the output terminal 49 is maintained in a floating state, and the electric potential of the second output signal Q2 is maintained at the electric potential of the high level supply voltage VDD, in the period from the time point t12 to the time point t13.
At the time point t13, a pulse of the second reset signal R2 is supplied to the input terminal 44. In response to this, the transistor M6 turns into an ON state. As a result, the electric potential of the second output signal Q2 decreases to a low level. Note that a pulse of the subframe reset signal SUBF_RST as the second reset signal R2 is supplied to each unit circuit 35a at the termination of each subframe period. In other words, the time point t13 in
Note that the configuration of the unit circuits 35a is not limited to the configuration illustrated in
The demultiplexing circuit 340 includes a first demultiplexer 342 to an n-th demultiplexer 342 corresponding to respective light emission enable signals GGem(1) to GGem(n) output from the light emission control line driving circuit 350, and the n pixel circuit rows in the display 500 corresponds to the respective n demultiplexers 342. As has already been described, the pixel circuit row is a pixel circuit group configured by m pixel circuits 50 aligned along a direction in which the writing control line G1_WL(i) extends (horizontal direction) in the display 500 (also referred to simply as a “row”). With the following configuration, each demultiplexer 342 supplies the corresponding light emission enable signal GGem(i) to the three light emission control lines EM1(i), EM2(i), and EM3(i) passing through the corresponding pixel circuit row in a time division manner (i=1 to n).
Specifically, as illustrated in
Next, a description will be given of first to third light emission control line deactivation circuits 350d1 to 350d3 included in the light emission control line driving circuit 350 in the present embodiment. Different start pulse signals ESPd1 to ESPd3 are input to the respective first to third light emission control line deactivation circuits 350d1 to 350d3, but the first to third light emission control line deactivation circuits 350d1 to 350d3 have the same configuration and act in accordance with the same clock signals CLK1 and CLK2. In the following, a description will be given of the configurations of the first to third light emission control line deactivation circuits 350d1 to 350d3 all together as a configuration of a k-th light emission control line deactivation circuit 350dk (k=1, 2, 3)
The shift register 35dsr configuring the light emission control line deactivation circuit 350dk is supplied with two-phase clock signals CLK1 and CLK2 as a light emission control clock signal ECK. Here, the clock signals CLK1 and CLK2 are the same as the clock signals CLK1 and CLK2 included in the writing control signal WCTL (refer to
Signals supplied to the input terminals of each stage (each unit circuit) of the shift register 35dsr are as follows. At each odd-numbered stage, the clock signal CLK1 is supplied as the clock signal VCLK, while at each even-numbered stage, the clock signal CLK2 is supplied as the clock signal VCLK. Moreover, at a certain stage, the state signal Q output from the previous stage is supplied as the set signal S, and the state signal Q output from the next stage is supplied as the reset signal R. However, for the first stage (not illustrated in
As illustrated in
Next, basic actions of the unit circuit 35d will be described with reference to
At the time point t30, a pulse of the set signal S is supplied to the input terminal 31. For example, the input terminal 31 of the unit circuit 35d(1) in the first stage is supplied with the deactivation start pulse signal ESPdk as the set signal S. Since the transistor T31 has a diode connection as illustrated in
In consideration of a case where the clock signal CLK1 is supplied as the clock signal VCLK, the clock signal VCLK changes from a low level to a high level at the time point t31. As illustrated in
At the time point t32, the clock signal VCLK changes from a high level to a low level. Consequently, the electric potential of the state signal Q decreases together with a decrease in the electric potential of the input terminal 33, and the electric potential of the first node N1 also decreases via the parasitic capacitances Cgd and Cgs. In addition, at the time point t32, a pulse of the reset signal R is supplied to the input terminal 32. In response to this, the transistor T33 and the transistor T34 turn into ON states. The change of the transistor T33 into an ON state causes the electric potential of the state signal Q to decrease to a low level, and the change of the transistor T34 into an ON state causes the electric potential of the first node N1 to decrease to a low level.
By taking account of the above-described actions of the unit circuits 35d and the configuration of the shift register 35dsr illustrated in
Note that the configuration of the unit circuit 35d is not limited to the configuration illustrated in
To the light emission control line activation circuit 350a, the activation start pulse signal ESPa including a pulse immediately before each subframe period is input from (the drive controller 110 of) the display control circuit 100 (
As has been already described, the light emission control line activation circuit 350a and the first to third light emission control line deactivation circuit 350d1 to 350d3 are supplied with the same clock signals CLK1 and CLK2 (
When signals of different kinds as above are supplied to the light emission control line activation circuit 350a and the light emission control line deactivation circuits 350d1 to 350d3, the light emission control lines EMk(1) to EMk(n) are driven as will be described below (k=1, 2, 3), and the first to third organic EL elements OLED(R), OLED(G), and OLED(B) in each pixel circuit 50 are lit accordingly.
In the first subframe period, the first selection signal SEL1 changes to a high level, so that the activation control transistor Tem1 of each demultiplexer 342 turns into an ON state, and consequently the first light emission control lines EM1(1) to EM1(n) are sequentially changed to a high level as illustrated in
Hence, the voltages of the first light emission control lines EM1(1) to EM1(n) are sequentially changed to a high level at the timings shifted by one horizontal interval in the first subframe period, so that each of the first light emission control lines EM1(1) to EM1(n) is maintained in a high level for a period equal to one subframe period. In the period where the first light emission control line EM1(i) in the i-th row is in a high level, the writing control signal Gw(i) changes to a high level at the beginning of the period to write the data signal Dj (j=1 to m) as R pixel data into each of the pixel circuits 50 in the i-th row (each of the pixel circuits 50 in the i-th pixel circuit row), the first organic EL element OLED(R) in each of the pixel circuits 50 in the i-th row turns into a lit state and emits red light at the intensity corresponding to the R pixel data (i=1 to n).
In the second subframe period, the second selection signal SEL2 changes to a high level, so that the activation control transistor Tem2 of each demultiplexer 342 turns into an ON state, and consequently the second light emission control lines EM2(1) to EM2(n) are sequentially changed to a high level as illustrated in
Hence, the voltages of the second light emission control lines EM2(1) to EM2(n) are changed to a high level at the timings shifted by one horizontal interval in the second subframe period, so that each of the first light emission control lines EM2(1) to EM2(n) is maintained in a high level for a period equal to one subframe period. In the period where the second light emission control line EM2(i) in the i-th row is in a high level, the writing control signal Gw(i) changes to a high level at the beginning of the period to write the data signal Dj (j=1 to m) as G pixel data into each of the pixel circuits 50 in the i-th row, the second organic EL element OLED(G) in each of the pixel circuits 50 in the i-th row turns into a lit state and emits green light at the intensity corresponding to the G pixel data (i=1 to n).
In the third subframe period, the third selection signal SEL3 changes to a high level, so that the activation control transistor Tem3 of each demultiplexer 342 turns into an ON state, and consequently the third light emission control lines EM3(1) to EM3(n) are sequentially changed to a high level as illustrated in
Hence, the voltages of the third light emission control lines EM3(1) to EM3(n) are changed to a high level at the timings shifted by one horizontal interval in the third subframe period, so that each of the third light emission control lines EM3(1) to EM3(n) is maintained in a high level for a period equal to one subframe period. In the period where the third light emission control line EM3(i) in the i-th row is in a high level, the writing control signal Gw(i) changes to a high level at the beginning of the period to write the data signal Dj (j=1 to m) as B pixel data into each of the pixel circuits 50 in the i-th row, and the third organic EL element OLED(B) in each of the pixel circuits 50 in the i-th row turns into a lit state and emits blue light at the intensity corresponding to the B pixel data (i=1 to n).
As described above, in the normal display mode, writing of the R pixel data (R data writing) to each of the pixel circuits 50 is performed in the first subframe period, writing of the G pixel data (G data writing) to each of the pixel circuits 50 is performed in the second subframe period, and writing of the B pixel data (B data writing) to each of the pixel circuits 50 is performed in the third subframe period, on the basis of input signals Sin (refer to
A description will be given below of actions of the organic EL display device according to the present embodiment in the current measurement mode.
First, a description will be given of a control process performed in the display control circuit 100 to cause the writing control line driving circuit 300 and the monitor control line driving circuit 400 to perform desired actions in the current measurement mode. In each frame period, in a state where the monitor enable signal Mon_EN is set to a low level, the compensation target line address Addr indicating the compensation target row is set in the compensation target line address storage memory 112, and the writing line counter 111 is initialized, a pulse of the start pulse signal GSP indicating start of actions of the writing control line driving circuit 300 is output. Moreover, one horizontal period after the pulse of the start pulse signal GSP is output, the pulse of the start pulse signal MSP indicating start of actions of the monitor control line driving circuit 400 is output. After the output of the pulse of the start pulse signal GSP, the writing count value CntWL increases on the basis of the clock signals CLK1 and CLK2.
As described above, the matching circuit 113 determines whether the writing count value CntWL output from the writing line counter 111 and the compensation target line address Addr stored in the compensation target line address storage memory 112 match. When the writing count value CntWL and the compensation target line address Addr match, the matching signal MS supplied to the status machine 115 changes from a low level to a high level. In this operation, the following control is performed by the status machine 115. Note that the time point at which the writing count value CntWL and the compensation target line address Addr match serves as a time point of start of a characteristics detection process period.
One horizontal interval after the time point at which the writing count value CntWL and the compensation target line address Addr match, both the clock signal CLK1 and the clock signal CLK2 are set to a low level. Thereafter, throughout the current measurement period, the clock actions of the clock signals CLK1 and CLK2 are stopped. After the current measurement period ends, the states of the clock signals CLK1 and CLK2 are returned to the states immediately before the start of the current measurement period.
One horizontal interval after the time point at which the writing count value CntWL and the compensation target line address Addr match, both the clock signal CLK3 and the clock signal CLK4 are changed similarly to a normal case. Thereafter, throughout the current measurement period, the clock actions of the clock signals CLK3 and CLK4 are stopped. After the current measurement period ends, the clock actions by the clock signals CLK3 and CLK4 are restarted.
One horizontal interval after the time point at which the writing count value CntWL and the compensation target line address Addr match, the monitor enable signal Mon_EN is set to a high level. Thereafter, throughout the current measurement period, the monitor enable signal Mon_EN is maintained at a high level. After the current measurement period ends, the monitor enable signal Mon_EN is changed to a low level.
In other words, the drive controller 110 in the display control circuit 100 performs the following control process. The drive controller 110 controls the clock signals CLK1 and CLK2 so that only the electric potential of the clock signal supplied to the unit circuit 30 corresponding to the compensation target row among the two clock signals CLK1 and CLK2 is changed at the times of start and end of the current measurement period and so that the clock actions of the clock signals CLK1 and CLK2 are stopped throughout the current measurement period. Moreover, the drive controller 110 controls the clock signals CLK3 and CLK4 so that, after the electric potentials of the clock signals CLK3 and CLK4 are changed at the time of start of the current measurement period, the clock actions of the clock signals CLK3 and CLK4 are stopped throughout the current measurement period. The drive controller 110 also changes the monitor enable signal Mon_EN to be active (high level) only in the current measurement period.
Note that in the current measurement mode, the subframe reset signal SUBF_RST in a high level is supplied to the light emission control line activation circuit 350a, and thereby all the light emission enable signals GGem(1) to GGem(n) are in low level (refer to
A description will be given of actions of the writing control line driving circuit 300 in or around the characteristics detection process period with reference to the contents in the above-descried control process in the display control circuit 100.
At a time point t1, the writing control line G1_WL(It−1) in the (It−1)-th column turns into an active state. Thereby, normal data writing is performed in the (It−1)-th row. Moreover, the change of the writing control line G1_WL(It−1) in the (It−1)-th row into an active state causes the electric potential of the first node N1(It) to increase in the unit circuit 30(It) in the It-th stage in the shift register 3. Note that until the time point immediately before a time point t2, the compensation target line address Addr and the writing count value CntWL do not match.
At the time point t2, the clock signal CLK1 rises. Consequently, the electric potential of the first node N1(It) further increases in the unit circuit 30(It) in the It-th stage. As a result of this, the writing control line G1_WL(It) in the It-th row turns into an active state. In this active state, pre-compensation data is written into each of the pixel circuits 50 in the It-th row. Moreover, at the time point t2, the change of the writing control line G1_WL(It) in the It-th row into an active state causes the electric potential of the first node N1(It+1) to increase in the unit circuit 30(It+1) in the (It+1)-th row in the shift register 3.
At the same time, at the time point t2, due to the rising of the clock signal CLK1, the compensation target line address Addr and the writing count value CntWL match. Consequently, the display control circuit 100 drops the clock signal CLK1 at a time point t3, which is one horizontal interval after the time point t2, and thereafter stops the clock actions of the clock signals CLK1 and CLK2 until the time point of the end of the current measurement period (time point t4). In other words, in the period from the time point t3 to the time point t4, the clock signal CLK1 and the clock signal CLK2 are maintained in a low level.
Note that, at the time point t3, the electric potential of the first node N1(It) decreases in the unit circuit 30(It) in the It-th stage as a result of the drop of the clock signal CLK1. Moreover, the clock signal CLK2 does not rise at the time point t3, and thus the writing control line G1_WL(It+1) in the (It+1)-th row does not turn into an active state. Hence, the reset signal R in a high level is not input to the unit circuit 30(It) in the It-th stage. Consequently, the electric potential of the first node N1(It) in the unit circuit 30(It) in the It-th stage at the time point immediately after the time point t3 is approximately equal to the electric potential at the time point immediately before the time point t2.
In the period from the time point t3 to the time point t4 (current measurement period), measurement of a drive current for detecting the characteristics of the drive transistor T2 is performed. In the current measurement period, the clock actions of the clock signals CLK1 and CLK2 are stopped. Consequently, the electric potential of the first node N1(It) in the unit circuit 30(It) in the It-th stage is maintained in the current measurement period.
At the time point t4, which is the time point of the end of the current measurement period, the display control circuit 100 restarts the clock actions of the clock signals CLK1 and CLK2. At this time, the signal that has been dropped at the time point of the start of the current measurement period (time point t3) of the clock signal CLK1 and the clock signal CLK2 is raised (clock signal CLK1 in the example illustrated in
At the time point t5, the clock signal CLK1 drops, and the clock signal CLK2 rises. In the period after this time point t5, the writing control lines G1_WL sequentially turn into an active state one row by one row. Thereby, normal data writing is performed in each row.
A description will be given of actions of the monitor control line driving circuit 400 in or around the characteristics detection process period with reference to the contents in the above-descried control process in the display control circuit 100.
In the monitor control line driving circuit 400, the state signals Q output from the respective unit circuits 40 in the shift register 4 are sequentially changed to a high level each one horizontal interval on the basis of the clock signals CLK3 and CLK4. For example, in the period from the time point t1 to the time point t2, the state signal Q(It−2) output from the unit circuit 40(It−2) in the (It−2)-th stage is in a high level, and in the period from the time point t2 to the time point t3, the state signal Q(It−1) output from the unit circuit 40(It−1) in the (It−1)-th stage is in a high level. However, in the period before the time point immediately before the time point t3, the monitor enables signal Mon_EN is in a low level, and hence the monitor control line G2_Mon(It−2) in the (It−2) row and the monitor control line G2_Mon(It−1) in the (It−1)-th row do not turn in an active state.
At the time point t2, the compensation target line address Addr and the writing count value CntWL match. Consequently, the display control circuit 100 changes the monitor enable signal Mon_EN from a low level to a high level at the time point t3, which is one horizontal interval after the time point t2. As a result of this, at the time point t3, the transistors T49 in all the unit circuits 40 turn into an ON state. Moreover, at the time point t3, the state signal Q(It) output from the unit circuit 40(It) in the It-th stage changes to a high level. Through the above, the output signal Q2(It) output from the unit circuit 40(It) in the It-th stage changes to a high level, and consequently, the monitor control line G2_Mon(It) in the It-th row turns into an active state.
Moreover, the display control circuit 100 changes the values of the clock signal CLK3 and the clock signal CLK4 at the time point t3 and thereafter stops the clock actions of the clock signals CLK3 and CLK4 in the current measurement period (period from the time point t3 to the time point t4). In the example illustrated in
At the time point t4, which is the time point of the end of the current measurement period, the display control circuit 100 changes the monitor enable signal Mon_EN from a high level to a low level and restarts the clock actions of the clock signals CLK3 and CLK4. In the period from the time point t4 to the time point t5, the state signal Q(It+1) output from the unit circuit 40(It+1) in the (It+1)-th stage is in a high level, but the monitor enable signal Mon_EN is in a low level. Therefore, the monitor control line G2_Mon(It+1) in the (It+1)-th row does not turn into an active state. Similarly, in the period after the time point t5, none of the monitor control lines G2_Mon turns into an active state.
As has already been described, in the normal display mode, to display a color image by sequential additive color mixture, writing of the R pixel data (R data writing) to each pixel circuit 50 is performed in the first subframe period, writing of the G pixel data (G data writing) to each pixel circuit 50 is performed in the second subframe period, and writing of the B pixel data (B data writing) to each pixel circuit 50 is performed in the third subframe period (refer to
In the action example illustrated in
While the writing control line G1_WL(It) is in an active state (a period t2 to t3) immediately before the current measurement period t3 to t4, the input transistor T1 of each pixel circuit (referred to as a “target pixel circuit” below) 50 in the compensation target row It is in an ON state. In this state, the input/output control signal DWT is in a high level, and hence the drive data signal Dj (pre-compensation data) is written into the target pixel circuit 50 as pixel data by the data voltage output unit circuit 211d in each data-side unit circuit 211. More specifically, the drive data signals Dj each indicating a gray scale voltage, which is pre-compensation data, are sequentially written into the pixel circuits 50 in the compensation target row It as pixel data (refer to
At the time point t3, the writing control line G1_WL(It) turns into an inactive state, and the current measurement period starts. In the current measurement period t3 to t4, the input transistor T1 of the target pixel circuit 50 is in an OFF state, and the data voltage corresponding to the pre-compensation pixel data is held in the capacitor Cst of the target pixel circuit. Moreover, at the time point t3, the input/output control signal DWT changes to a low level, and the current measurement unit circuit 211m in each data-side unit circuit 211 is connected to the corresponding data line SLj. Furthermore, the monitor enable signal Mon_EN changes to a high level, and thus the monitor control line G2_Mon(It) turns into an active state (high level). Therefore, the monitor control transistor Tm of the target pixel circuit 50 turns into an ON state. Hence, in the current measurement period t3 to t4, the drive current of the target pixel circuit 50 is supplied to the current measurement unit circuit 211m via the monitor control transistor Tm of the pixel circuit 50 and the data line SLj connected to the monitor control transistor Tm (refer to
Note that in the current measurement mode, since the light emission control transistors T3 to T5 in each pixel circuit 50 are in an OFF state as has been described, all the organic EL elements OLED in the display 500 are in a lit-out state. Moreover, each data line SLj (j=1 to m) is maintained at the low level supply voltage ELVSS by the current measurement unit circuit 211m having the configuration as illustrated in
The monitor voltage vmoj output from each current measurement unit circuit 211m is transmitted to the correction data calculator/storage 120 in the display control circuit 100 as the current measurement result Vmo obtained in the current measurement circuit 220 (refer to
As illustrated in
Next, with reference to
After the characteristics detection process is started, one writing control line G1_WL is selected as a scan target every time a clock pulse of the clock signal CLK1 or the clock signal CLK2 is generated (Step S100). Determination on whether the compensation target line address Addr stored in the compensation target line address storage memory 112 and the writing count value CntWL output from the writing line counter 111 match, is performed (Step S110). As a result of this, when the values match, the process advances to Step S120. When the values do not match, on the other hand, the process advances to Step S112. In Step S112, determination on whether the scan target is the writing control line in the last row, is performed. As a result of this, when the scan target is the writing control line in the last row, the process advances to Step S150. When the scan target is not the writing control line in the last row, on the other hand, the process returns to Step S100. Note that in a case where the process advances to Step S112, normal data writing is performed.
In Step S120, the matching count value CntM is incremented by 1. Thereafter, determination on whether the matching count value CntM is 1 or 2 is performed (Step S130). As a result, when the matching count value CntM is 1, the process advances to Step S132. When the matching count value CntM is 2, on the other hand, the process advances to Step S134. In Step S132, measurement of a drive current based on the first gray scale P1 is performed. In Step S134, measurement of a drive current based on the second gray scale P2 is performed.
After the completion of Step S132 or Step S134, determination on whether the scan target is the writing control line in the last row, is performed (Step S140). As a result of this, when the scan target is the writing control line in the last row, the process advances to Step S150. When the scan target is not the writing control line in the last row, on the other hand, the process returns to Step S100.
In Step S150, the writing count value CntWL is initialized. Thereafter, determination on whether the condition that “the matching count value CntM is 1, and the value of the compensation target line address Addr is the value WL_Max indicating the last row or smaller” is satisfied, is determined (Step S160). As a result of this, when the condition is satisfied, the process advances to Step S162. When the condition is not satisfied, on the other hand, the process advances to Step S164.
In Step S162, the same value is substituted into the compensation target line address Addr in the compensation target line address storage memory 112. Note that this Step S162 does not always need to be provided. In Step S164, determination on whether the condition that “the matching count value CntM is 2, and the value of the compensation target line address Addr is the value WL_Max indicating the last row or smaller” is satisfied, is performed. As a result of this, when the condition is satisfied, the process advances to Step S166. When the condition is not satisfied, on the other hand, the process advances to Step S170. In Step S166, the compensation target line address Addr is incremented by 1. In Step S168, the matching count value CntM is initialized.
In Step S170, determination on whether the condition that “the value of the compensation target line address Addr is equal to a value obtained by adding 1 to the value WL_Max indicating the last row” is satisfied, is performed. As a result of this, when the condition is satisfied, the process advances to Step S180. When the condition is not satisfied, on the other hand, it is assumed that the measurement of a drive current in each of the pixel circuits 50 in one compensation target row has ended although the characteristics detection process for the drive transistors of all the pixel circuits 50 in the display 500 is not completed, and the characteristics detection process in
Next, with reference to
First, measurement of a drive current is performed in the characteristics detection process period as described above (Step S200). The measurement of a drive current is performed on the basis of the two kinds of gray scales (the first gray scale P1 and the second gray scale P2: P2>P1). The measurement of a drive current based on these two kinds of gray scales may be configured such that measurement of a drive current based on the first gray scale P1 is performed in the first frame period of two consecutive frame periods while measurement of a drive current is performed based on the second gray scale P2 in the second frame period. However, the present invention is not limited to this. The timing to start the actions in the current measurement mode and the duration of the actions are determined by the above-described mode control signal Cm. Hence, in the present embodiment, two frame periods in which a drive currents based on the two kinds of gray scales are measured in each of the pixel circuits 50 in one compensation target row may be consecutive, but there may be a frame period in the normal display mode between these two frame periods.
In the present embodiment, measurement of a drive current based on the first gray scale P1 is performed in the first frame period of the above-described two frame periods for measuring a drive current for one compensation target row, and measurement of a drive current based on the second gray scale P2 is performed in the second frame period. More specifically, measurement of a drive current obtained by writing a first measurement gray scale voltage Vmp1 as pixel data into the pixel circuit 50 calculated according to Equation (1) below is performed in the first frame, and measurement of a drive current obtained by writing a second measurement gray scale voltage Vmp2 as pixel data into the pixel circuit 50 calculated according to Equation (2) below is performed in the second frame.
Vmp1=Vcw*Vn(P1)*B(i,j)+Vth(i,j) (1)
Vmp2=Vcw*Vn(P2)*B(i,j)+Vth(i,j) (2)
Here, Vcw is the difference between the gray scale voltage corresponding to the minimum gray scale and the gray scale voltage corresponding to the maximum gray scale (i.e., the range of gray scale voltage). Vn(P1) is a value obtained by normalizing the first gray scale P1 to a value in the range from 0 to 1, and the Vn(P2) is a value obtained by normalizing the second gray scale P2 to a value in the range from 0 to 1. B(i, j) is a normalization coefficient for the pixel at i-th row, j-th column calculated according to Equation (3) below. Vth(i, j) is an offset value for the pixel at i-th row, j-th column (this offset value corresponds to a threshold voltage of the drive transistor).
B=√(β0/β) (3)
Here, β0 is the average value of the gain values of all the pixels, and β is a gain value for the pixel at i-th row, j-th column.
After the measurement of a drive current based on the two kinds of gray scales, the offset value Vth and the gain value β are calculated on the basis of the measurement values (Step S210). The operation in this Step S210 is performed by the correction arithmetic circuit 122 in the correction data calculator/storage 120 (refer to
Ids=β*(Vgs−Yth)2 (4)
Specifically, the offset value Vth expressed by Equation (5) below and the gain value β expressed by Equation (6) below are obtained according to the simultaneous equations of the equation obtained by substituting the measurement result based on the first gray scale P1 into Equation (4) above and the equation obtained by substituting the measurement result based on the second gray scale P2 into Equation (4).
Vth={Vgsp2√(IOp1)−Vgsp1√(IOp2)}/{√(IOp1)−√(IOp2)} (5)
β={√(IOp1)−√(IOp2)}2/(Vgsp1−Vgsp2)2 (6)
Here, IOp1 denotes a drive current as a measurement result based on the first gray scale P1, and IOp2 denotes a drive current as a measurement result based on the second gray scale P2. Moreover, Vgsp1 denotes a gate-source voltage based on the first gray scale P1, and Vgsp2 denotes a gate-source voltage based on the second gray scale P2. As described above, in the present embodiment, the source terminal of the drive transistor T2 in the pixel circuit 50 for which a drive current is measured is maintained at the low level supply voltage ELVSS (refer to
Vgsp1=Vmp1 (7)
Vgsp2=Vmp2 (8)
By using the offset value Vth and the gain value β calculated as described above, the correction data held in the nonvolatile memory 123 in the correction data calculator/storage 120 (refer to
Next, to write the pixel data in the pixel circuit 50 of i-th row, j-th column, the gray scale voltage Vp is calculated according to Equation (9) below by using the offset value Vth and the gain value β (Step S220). This operation in Step S220 is performed by the gray scale correction unit 130 (refer to
Vp=Vcw*Vn(P)*√(β0/β)+Vth+Vf (9)
Here, Vn(P) is a value obtained by normalizing the display gray scale at the pixel of i-th row, j-th column to a value in the range from 0 to 1. Vf denotes a forward voltage of the organic EL element OLED and is assumed to be a known fixed value in the present embodiment. Note that it is assumed that the drain-source voltages of the light emission control transistors T3 to T5 can be ignored.
Thereafter, the gray scale voltage Vp calculated in Step S220 is written into the pixel circuit 50 of i-th row, j-th column as pixel data (Step S230). By performing the above-described compensation process on each of all the pixels, variations in characteristics of the drive transistors can be compensated.
In the above example, in the second frame period of the above-described two frame periods for measuring drive currents for one compensation target, new correction data (offset value and gain value) is calculated on the basis of a result of current measurement based on the first gray scale P1 obtained in the first frame period and a result of current measurement based on the second gray scale P2 obtained in the second frame period. However, in a case where a frame period in the normal display mode exists between the two frame periods in the current measurement mode, new correction data (offset value and gain value) is calculated also in the first frame period, on the basis of a result of current measurement based on the first gray scale P1 obtained in the first frame period and a result of current measurement based on the second gray scale P2 performed for the compensation target row before the first frame period. In this case, in the frame period in the normal display mode between the first frame period and the second frame period, the digital video signal DV is generated by correcting gray scale data indicated by the display data signal DA based on the new correction data in the gray scale correction unit 130 (refer to
In the known organic EL display device, the R pixel circuit 50r, the G pixel circuit 50g, and the B pixel circuit 50b are used to form one pixel in a color image to be displayed, as illustrated in
As illustrated in
As described above, according to the present embodiment, it is possible to reduce not only the contents of the circuits in the display 500, in which the pixel circuits for forming an image to be displayed are arranged in a matrix but also the contents of circuits in the data-side driving circuit, which makes it possible to display a high-resolution color image while minimizing an increase in cost. A detailed description will be given below of such effects of the present embodiment from a quantitative viewpoint.
As illustrated in
In contrast to this, as illustrated in
In both the known organic EL display device and the present embodiment, the transistors included in each pixel circuit are thin film transistors (TFTs). Assume that the length of one TFT (length in the channel length direction) is x and the width of one TFT (length in the channel width direction) is y. Then, an occupation area Sp of the necessary TFTs to form one pixel in the known organic EL display device is equal to the area for forming nine TFTs, which is
Sp=9x*1y=9xy,
as illustrated in
Sq=6x*1y=6xy,
as illustrated in
According to the above, a ratio Rt [%] of the occupation area Sq of the TFTs in the present embodiment to the occupation area Sp of the TFTs in the known organic EL display device is
Rt=Sq/Sp*100=(6xy)/(9xy)*100≈67%.
Hence, according to the present embodiment, the occupation area of the TFTs for implementing the pixel circuits in the display is reduced by approximately 33%.
Moreover, assume that the capacitor Cst as a data holding capacity in the pixel circuit is formed in a rectangular shape with gate wiring line and source or drain wiring line (referred to as “SD wiring line” below) and that the length of a short side of the capacitor Cst included in one pixel circuit is denoted by xc while the length of a long side of the capacitor Cst is denoted by yc. On this assumption, the occupation area Scp of the data holding capacity necessary to form one pixel in the known organic EL display device is the area for forming the three capacitors Cst as the data holding capacity in the three pixel circuits and is, as illustrated in
Scp=3xc*yc.
In contrast to this, the occupation area Scq of the data holding capacity necessary to form one pixel in the present embodiment is the area for forming the capacitor Cst as the data holding capacity in one pixel circuit and is, as illustrated in
Scq=x
c
*y
c.
Note that in
According to the above, a ratio Rc [%] of the occupation area Scq of the data holding capacity in the present embodiment to the occupation area Scp of the data holding capacity in the known organic EL display device is
Rc=Scq/Scp*100=(xcyc)/(3xcyc)*100≈33%.
Hence, according to the present embodiment, the occupation area of the data holding capacity for implementing the pixel circuits in the display is reduced by approximately 67%.
The pixel circuit is formed of the TFTs and the data holding capacity except for the organic EL elements, and thus the occupation area of the pixel circuit for forming one pixel of an image to be displayed can be significantly reduced according to the present embodiment in combination of the above-described effects of the reduction of the occupation area of the TFTs and the above-described effects of the reduction of the occupancy area of the data holding capacity. Hence, the present embodiment is remarkably advantageous in achieving high resolution of a display image compared to the known configuration. Note that, although only the areas for forming the TFTs and data holding capacity are focused above, areas of the wiring line for connecting the TFTs and the contact portions are also reduced in the present embodiment compared to the known configuration. Hence, in actual, more significant reduction effects than those described above can be obtained with respect to the area of the circuits necessary for forming each one pixel according to the present embodiment.
As illustrated in
Note that in the present embodiment, the light emission control line driving circuit 350 is needed (refer to
Next, a description will be given of an active-matrix organic EL display device according to a second embodiment of the present invention.
As has been described, in the above-described first embodiment, the mode control signal Cm indicates, for each frame period, whether to act in the normal display mode or act in the current measurement mode. The organic EL display device according to the above-described first embodiment acts as illustrated in
In this configuration, for example, an action of displaying a color image in a field sequential method and an action of measuring a drive current of each of the pixel circuits 50 in one compensation target row for one frame period and calculating correction data (offset value and gain value) on the basis of a result of the measurement, can be performed as illustrated in the timing chart in
After this, as an action in the current measurement mode, a drive current is measured in each of the pixel circuits 50 in the above-described compensation target row on the basis of the second gray scale P2 in one frame period. Moreover, in the frame period in this current measurement mode, new correction data (offset value and gain value) is calculated on the basis of a result of current measurement based on the second gray scale P2 obtained in this frame period and a result of current measurement based on the first gray scale P1 obtained in the frame period in the current measurement mode immediately before this frame period, to update correction data. Hence, in the frame period in this current measurement mode, actions of measuring a drive current for one compensation target row on the basis of the second gray scale P2 to update correction data (referred to as “1WL(P2) current measurement and correction data calculation” below) are performed. Thereafter, as actions in the normal display mode, FSC normal display in which pixel data is written into each pixel circuit 50 on the basis of gray scale data obtained as a result of correction using correction data obtained as a result of the update in the frame period in the current measurement mode to display a color image, are performed in the certain frame period (N frame period).
In contrast to this, in the second embodiment of the present invention, a period to perform current measurement and data correction calculation, i.e., a period to act in the current measurement mode, is determined in advance without inputting or generating the mode control signal Cm. For example, as will be described below, in a case where a period to act in the current measurement mode is determined on the basis of the time point at which the display device is turned on, a power source ON detection circuit 161 configured to detect that the display device is turned on is provided in or outside the drive controller 110 in the display device, and a power source ON signal Son output from the power source ON detection circuit 161 is input to the status machine 115 in the drive controller 110 as a signal indicating that the display device is turned on, as illustrated in
The organic EL display device according to the present embodiment includes a configuration in which, when the display device is turned on, current measurement based on the first gray scale P1 and current measurement based on the second gray scale P2 are performed for each of all the pixel circuits 50 in the display 500 in the period immediately after the turning-on of the display device, on the basis of the above-described power source ON signal Son and new correction data is calculated on the basis of results of the measurements (such current measurement and correction data calculation are referred to as “all WL current measurement and correction data calculation” below), and acts as illustrated in
The above-described all WL current measurement and correction data calculation in the present embodiment are specifically implemented by a characteristics detection process in the flowchart illustrated in
As described above, in the present embodiment, the timings at and the order in which the actions in the normal display mode (FSC normal display) and the actions in the current measurement mode (current measurement and correction data calculation) are performed are different from those in the above-described first embodiment. However, the configurations of the pixel circuits 50 and the light emission control line driving circuit 350 having characteristics different from the known organic EL display device (
Next, a description will be given of an active matrix organic EL display device according to a third embodiment of the present invention. In the present embodiment, the display device includes a configuration of acting in the current measurement mode in a period where the display device is turned on but is not used (referred to as a “DP disuse period” below). With this configuration, as illustrated in
The organic EL display device according to the present embodiment acts in the current measurement mode in the period of a certain number of frames (N frame period) in the DP disuse period on the basis of the DP disuse signal Sdpn and acts in the normal display mode in the periods other than the DP disuse period. Note that in the DP disuse period, the compensation target row is sequentially changed, similarly to the first embodiment, while current measurement based on the first gray scale P1 and current measurement based on the second gray sale P2 are performed for each compensation target row in two frame periods and correction data is updated (refer to Step S166 in
For example, in a case where the DP disuse detection circuit 163 illustrated in
In the action example illustrated in
As described above, the present embodiment is different from the first embodiment in that the timings at and periods in which the actions in the current measurement mode (current measurement and correction data calculation) are performed are based on detection of the DP disuse period (sleep mode period). However, the configurations of the pixel circuits 50 and the light emission control line driving circuit 350 having characteristics different from the known organic EL display device (
The present invention is not limited to the embodiments described above, and various modifications may be made without departing from the scope of the present invention. A description follows regarding modified examples of the above-described embodiments.
In the above-described embodiments, the light emission control lines EM1(i), EM2(i), and EM3(i), the number of which (three) is equal to the number of the organic EL elements OLED(R), OLED(G), and OLED(B) included in one pixel circuits 50, are provided for each pixel circuit row, and the light emission control line driving circuit 350 includes the first to third light emission control line deactivation circuits 350d1 to 350d3 corresponding to the three respective light emission control lines EM1(i), EM2(i), and EM3(i), as illustrated in
However, by using a pulse signal corresponding to the logical sum of the first to third deactivation start pulse signals ESPd1 to ESPd3, i.e., an integrated deactivation start pulse signal ESPdd including pulses changing to a high level at the same timings as the pulses of the n-th writing control signal Gw(n) in the respective subframe periods as illustrated in
As described above, the integrated deactivation start pulse signal ESPdd changes to a high level at the same timings as the pulses of the n-th (last) writing control signal Gw(n) in the respective subframe periods, and thus the first deactivation signal EM_pd(1) among the n deactivation signals EM_pd(1) to EM_pd(n) output from the light emission control line deactivation circuit 350d, i.e., the deactivation signal EM_pd(1) supplied to the gate terminals of the pull-down transistors Tpd1 to Tpd3 in the first row, changes to a high level and keeps a high level only for one horizontal interval immediately after the pulse of the n-th writing control signal Gw(n), and thereafter second and subsequent deactivation signals EM_pd(2) to EM_pd(n) sequentially change to a high level and keep a high level for one horizontal interval. In contrast, as illustrated in
With the above configuration, even when the light emission control line driving circuit 350 including the configuration illustrated in
Each of the above-described embodiments includes the data-side driving circuit 200 having a function of measuring a current output to each of the data lines SL1 to SLm from each of the pixel circuits 50 on the basis of the drive of the monitor control lines G2_Mon(1) to G2_Mon(n) (refer to
In the present modified example, as illustrated in
The monitor voltage vmoj output from each data-side unit circuit 211 is transmitted to the correction data calculator/storage 120 in the display control circuit 100 as the voltage measurement result Vmo obtained in the voltage measurement circuit in the data-side driving circuit 200 (refer to
The present modified example described above is different from the first embodiment in that a voltage is measured to obtain the characteristics of the drive transistors in each of the pixel circuits 50. However, the configurations of the pixel circuits 50 and the light emission control line driving circuit 350 having characteristics different from the known organic EL display device (
Each of the above-described embodiments is configured to detect the characteristics (offset value and gain value as correction data) of the drive transistor T2 by measuring a current passing through the drive transistor T2 in each pixel circuit 50 in the current measurement mode. However, instead of or together with this, each of the above-described embodiments may be configured to detect the characteristics of the organic EL elements OLED(R), OLED(G), and OLED(B) in the pixel circuit 50. In this case, in the characteristics detection process period for detecting the characteristics of the organic EL element OLED, the writing control line driving circuit 300 drives the writing control line G1_WL(i), the monitor control line driving circuit 400 drives the monitor control line G2_Mon(i), and the light emission control line driving circuit 350 drives the light emission control lines EM1(i), EM2(i), and EM3(i) (i=1 to n), under the control by the display control circuit 100, whereby each of the pixel circuits 50 and the data-side driving circuit 200 acts as described below (refer to
First, a measurement data voltage with which the drive transistor T2 in each of the pixel circuits 50 in the compensation target row is in an OFF state, is supplied to the data holding capacity Cst of the pixel circuit 50 and held. Next, in the current measurement period in the above-described characteristics detection process period, the monitor control line G2_Mon(It) corresponding to the compensation target row is turned into an active state (refer to
As described above, the current passing through each of the organic EL elements OLED(R), OLED(G), and OLED(B) in each of the pixel circuits in the compensation target row is measured, the characteristics of the organic EL elements OLED(R), OLED(G), and OLED(B) are detected from results of the measurement, and results of the detection are held as correction data as in the configuration that characteristics of the drive transistor T2 are detected on the basis of result of measurement of the current passing through the drive transistor T2. The correction data is used to correct each of gray scale voltages indicated by the display data signal DA for image display, as correction data (offset value and gain value) obtained on the basis of the result of measurement of the current passing through the drive transistor T2 (refer to
In the present modified example, the configuration is made to detect the characteristics (offset value and gain value as correction data) of each of the organic EL elements OLED(X) by measuring the current passing through each of the organic EL elements OLED(X) (X=R, G, B) in the pixel circuit 50. Instead of this, a prescribed current may be sequentially supplied to the organic EL elements OLED(X) in the pixel circuit 50 from the data-side driving circuit 200 via the data line SLj, and the voltage of the anode of the organic EL element OLED(X) through which the current passes may be measured via the data line SLj (refer to
In the above-described embodiments, a color image is displayed in a sequential additive color mixture method for displaying an image of colors assigned in three respective subframe periods corresponding to three primary colors. The three primary colors used here are constituted by red, green, and blue, but three primary colors constituted by other colors may be used. Moreover, four or more subframe periods may be included in each frame period, and a configuration may be made as to display a color image in a sequential additive color mixture method for displaying an image of colors assigned in the four or more respective subframe periods.
Note that descriptions have been given of the above-described embodiments by taking an organic EL display device as an example. However, the present invention is applicable to any display device other than an organic EL display device as long as the display device is an active matrix display device including current-driven self-luminescent display elements.
The present application claims priority based on JP 2015-257664 with the title of “PIXEL CIRCUIT, AND DISPLAY DEVICE AND DRIVING METHOD THEREFORE” filed on Dec. 29, 2015, the content of which is incorporated in the present application by reference.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2015-257664 | Dec 2015 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2016/088333 | 12/22/2016 | WO | 00 |
