Patent Application
20240054943
This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0099299, filed on Aug. 9, 2022 in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.
Embodiments of the present inventive concept relate to a pixel circuit and a display device having the pixel circuit. More particularly, embodiments of the present inventive concept relate to a pixel circuit that receives a bias gate signal and a display device having the pixel circuit.
Generally, a display device may include a display panel, a timing controller, a gate driver, and a data driver. The display panel may include a plurality of gate lines, a plurality of data lines, and a plurality of pixel circuits electrically connected to the gate lines and the data lines. The gate driver may provide gate signals to the gate lines. The data driver may provide data voltages to the data lines. The timing controller may control the gate driver and the data driver.
Each of the pixel circuits may include a light emitting element that receives a driving current and emits light. The driving current may charge a capacitor connected to an anode electrode of the light emitting element (or an internal capacitor of the light emitting element), and the light emitting element may emit light with a luminance corresponding to the charged voltage.
Embodiments of the present inventive concept provide a pixel circuit that initializes an anode electrode of a light emitting element.
Embodiments of the present inventive concept also provide a display device having the pixel circuit.
According to embodiments of the present inventive concept, a pixel circuit includes a light emitting element, a write transistor configured to write a data voltage in response to a write gate signal, a driving transistor configured to generate a driving current based on the data voltage and to apply the driving current to the light emitting element, a compensation transistor configured to diode-connect the driving transistor in response to a compensation gate signal, a first initialization transistor configured to apply a first initialization voltage to a control electrode of the driving transistor in response to an initialization gate signal, and a second initialization transistor configured to apply a second initialization voltage to an anode electrode of the light emitting element in response to a bias gate signal having an activation period longer than at least one of the compensation gate signal and the initialization gate signal.
In an embodiment, the activation period of the bias gate signal is greater than or equal to about 480 microseconds.
In an embodiment, the pixel circuit further includes a first emission transistor configured to apply a first power voltage to the driving transistor in response to an emission signal, and a second emission transistor configured to transmit the driving current to the light emitting element in response to the emission signal.
In an embodiment, the bias gate signal has the activation period in an inactivation period of the emission signal.
In an embodiment, the bias gate signal has an activation period after about 2 microseconds or more passes from when the emission signal is inactivated.
In an embodiment, the emission signal is generated based on an emission clock signal, and the emission signal has an activation period of N clock times of the emission clock signal, where N is a positive integer greater than 2.
In an embodiment, the activation period of the bias gate signal is shorter than the N clock times of the emission clock signal.
In an embodiment, the initialization gate signal, the compensation gate signal, and the write gate signal have an activation period in the activation period of the bias gate signal.
In an embodiment, the initialization gate signal has an activation period in the activation period of the bias gate signal, the write gate signal has an activation period in an inactivation period of the bias gate signal, and the compensation gate signal is activated in the activation period of the bias gate signal and is inactivated in the inactivation period of the bias gate signal.
In an embodiment, the initialization gate signal and the compensation gate signal are activated in an inactivation period of the bias gate signal, are inactivated in the activation period of the bias gate signal, and the write gate signal has an activation period in the activation period of the bias gate signal.
According to embodiments of the present inventive concept, a display device includes a display panel including a plurality of pixel circuits, a data driver configured to provide a data voltage to each of the pixel circuits, a gate driver configured to provide a write gate signal, a compensation gate signal, an initialization gate signal, and a bias gate signal to each of the pixel circuits, and a timing controller configured to control the data driver and the gate driver. Each of the pixel circuits includes a light emitting element, a write transistor configured to write the data voltage in response to the write gate signal, a driving transistor configured to generate a driving current based on the data voltage and to apply the driving current to the light emitting element, a compensation transistor configured to diode-connect the driving transistor in response to the compensation gate signal, a first initialization transistor configured to apply a first initialization voltage to a control electrode of the driving transistor in response to the initialization gate signal, and a second initialization transistor configured to apply a second initialization voltage to an anode electrode of the light emitting element in response to the bias gate signal having an activation period longer than at least one of the compensation gate signal and the initialization gate signal.
In an embodiment, the activation period of the bias gate signal is greater than or equal to about 480 microseconds.
In an embodiment, the display device further includes an emission driver configured to provide an emission signal to each of the pixel circuits. Each of the pixel circuits further includes a first emission transistor configured to apply a first power voltage to the driving transistor in response to the emission signal, and a second emission transistor configured to transmit the driving current to the light emitting element in response to the emission signal.
In an embodiment, the bias gate signal has an activation period in an inactivation period of the emission signal.
In an embodiment, the bias gate signal has an activation period after about 2 microseconds or more passes from when the emission signal is inactivated.
In an embodiment, the emission signal is generated based on an emission clock signal, and the emission signal has an activation period of N clock times of the emission clock signal, where N is a positive integer greater than 2.
In an embodiment, the activation period of the bias gate signal is shorter than the N clock times of the emission clock signal.
In an embodiment, the initialization gate signal, the compensation gate signal, and the write gate signal have an activation period in the activation period of the bias gate signal.
In an embodiment, the initialization gate signal has an activation period in the activation period of the bias gate signal, the write gate signal has an activation period in an inactivation period of the bias gate signal, and the compensation gate signal is activated in the activation period of the bias gate signal and is inactivated in the inactivation period of the bias gate signal.
In an embodiment, the initialization gate signal and the compensation gate signal are activated in an inactivation period of the bias gate signal, are inactivated in the activation period of the bias gate signal, and the write gate signal has an activation period in the activation period of the bias gate signal.
Therefore, according to embodiments of the present inventive concept, the display device may initialize an anode of a light emitting element for a longer period by including the light emitting element, a write transistor configured to write a data voltage in response to a write gate signal, a driving transistor configured to generate a driving current based on the data voltage and to apply the driving current to the light emitting element, a compensation transistor configured to diode-connect the driving transistor in response to a compensation gate signal, a first initialization transistor configured to apply a first initialization voltage to a control electrode of the driving transistor in response to an initialization gate signal, and a second initialization transistor configured to apply a second initialization voltage to an anode electrode of the light emitting element in response to a bias gate signal having an activation period longer than at least one of the compensation gate signal and the initialization gate signal.
In addition, according to embodiments of the present inventive concept, the display device may reduce an afterimage by including a pixel circuit that initializes an anode of a light emitting element for a longer period.
It is to be understood that the effects of embodiments of the present inventive concept are not limited to the above-described effects, and may be variously expanded without departing from the spirit and scope of the present inventive concept.
The above and other features of the inventive concept will become more apparent by describing in detail embodiments thereof with reference to the accompanying drawings.
Embodiments of the present inventive concept will be described more fully hereinafter with reference to the accompanying drawings. Like reference numerals may refer to like elements throughout the accompanying drawings.
Herein, when two or more elements or values are described as being substantially the same as or about equal to each other, it is to be understood that the elements or values are identical to each other, the elements or values are equal to each other within a measurement error, or if measurably unequal, are close enough in value to be functionally equal to each other as would be understood by a person having ordinary skill in the art. For example, the term “about” as used herein is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, considering the measurement in question and the error associated with measurement of the particular quantity (e.g., the limitations of the measurement system). For example, “about” may mean within one or more standard deviations as understood by one of the ordinary skill in the art. Further, it is to be understood that while parameters may be described herein as having “about” a certain value, according to exemplary embodiments, the parameter may be exactly the certain value or approximately the certain value within a measurement error as would be understood by a person having ordinary skill in the art.
It will be understood that the terms “first,” “second,” “third,” etc. are used herein to distinguish one element from another, and the elements are not limited by these terms. Thus, a “first” element in an embodiment may be described as a “second” element in another embodiment.
It should be understood that descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments, unless the context clearly indicates otherwise.
The terms of a singular form may include plural forms unless the context clearly indicates otherwise.
Referring to
The display panel 100 has a display region AA in which an image is displayed and a peripheral region PA adjacent to the display region AA. In an embodiment, the gate driver 300 and the emission driver 500 may be mounted in the peripheral region PA of the display panel 100.
The display panel 100 may include a plurality of gate lines GL, a plurality of data lines DL, a plurality of emission lines EL, and a plurality of pixel circuits P electrically connected to the data lines DL, the gate lines GL, and the emission lines EL. The gate lines GL and the emission lines EL may extend in a first direction D1 and the data lines DL may extend in a second direction D2 crossing the first direction D1.
The timing controller 200 may receive input image data IMG and an input control signal CONT from a host processor (e.g., a graphic processing unit GPU). For example, the input image data IMG may include red image data, green image data and blue image data. In an embodiment, the input image data IMG may further include white image data. In an embodiment, the input image data IMG may include magenta image data, yellow image data, and cyan image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may further include a vertical synchronization signal and a horizontal synchronization signal.
The timing controller 200 may generate a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, and data signal DATA based on the input image data IMG and the input control signal CONT.
The timing controller 200 may generate the first control signal CONT1 for controlling operation of the gate driver 300 based on the input control signal CONT, and output the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.
The timing controller 200 may generate the second control signal CONT2 for controlling operation of the data driver 400 based on the input control signal CONT, and output the second control signal CONT2 to the data driver 400. The second control signal CONT2 may include a horizontal start signal and a load signal.
The timing controller 200 may generate the third control signal CONT3 for controlling operation of the emission driver 500 based on the input control signal CONT, and output the third control signal CONT3 to the emission driver 500. The third control signal CONT3 may include a vertical start signal and a emission clock signal.
The timing controller 200 may receive the input image data IMG and the input control signal CONT, and generate the data signal DATA. The timing controller 200 may output the data signal DATA to the data driver 400.
The gate driver 300 may generate gate signals for driving the gate lines GL in response to the first control signal CONT1 input from the timing controller 200. The gate driver 300 may output the gate signals to the gate lines GL. For example, the gate driver 300 may sequentially output the gate signals to the gate lines GL.
The data driver 400 may receive the second control signal CONT2 and the data signal DATA from the timing controller 200. The data driver 400 may convert the data signal DATA into data voltages having an analog type. The data driver 400 may output the data voltages to the data lines DL.
The emission driver 500 may generate gate signals for driving the emission lines EL in response to the third control signal CONT3 input from the timing controller 200. The emission driver 500 may output the emission signals to the emission lines EL. For example, the emission driver 500 may sequentially output the emission signals to the emission lines EL.
Referring to
Referring to
In an embodiment, the driving transistor T1 may further include a lower electrode. For example, the lower electrode of the driving transistor T1 may be connected to the first electrode of the driving transistor T1.
The first, second, fifth, and sixth transistors T1, T2, T5, and T6 may be implemented as p-channel metal oxide semiconductor (PMOS) transistors. In this case, a low voltage level may be an activation level, and a high voltage level may be an inactivation level. For example, when a signal applied to a control electrode of the PMOS transistor has the low voltage level, the PMOS transistor may be turned on. For example, when a signal applied to the control electrode of the PMOS transistor has the high voltage level, the PMOS transistor may be turned off.
The third, fourth, and seventh transistors T3, T4, and T7 may be implemented as n-channel metal oxide semiconductor (NMOS) transistors. In this case, the low voltage level may be a inactivation level, and the high voltage level may be an activation level. For example, when a signal applied to a control electrode of the NMOS transistor has the low voltage level, the NMOS transistor may be turned off. For example, when a signal applied to the control electrode of the NMOS transistor has the high voltage level, the NMOS transistor may be turned on.
However, embodiments of the present inventive concept are not limited thereto. For example, the first, second, fifth, and sixth transistors T1, T2, T5, and T6 may be NMOS transistors according to embodiments. For example, the third, fourth, seventh transistors T3, T4, and T7 may be PMOS transistors according to embodiments.
Referring to
In an embodiment, the bias gate signal GB may have the activation period after about 2 s or more passes from when the emission signal EM is inactivated. Accordingly, after the second emission transistor T6 is turned off, the second initialization voltage VAINT may be applied to the anode electrode of the light emitting element EE.
In an embodiment, the activation period of the bias gate signal GB may be longer than or equal to about 480 s. For example, the activation period of the bias gate signal GB may be longer than or equal to about 187 horizontal time 187H.
For example, the time that an afterimage remains may be calculated from The following equation:
Y=−0.0098*X+14.692
where, Y is a time (e.g., in units of sec) for which the afterimage remains, and X may be a time (e.g., in units of μs) for which the second initialization voltage VAINT is applied to the anode electrode. Accordingly, since the activation period of the bias gate signal GB is longer than or equal to about 480 s, the remaining time of the afterimage may be less than about 10 sec.
Referring to
Referring to
Referring to
Referring to
In this way, the display device may reduce the time that the afterimage remains by making an anode initialization time during which the anode initialization operation is performed longer.
Referring to
The emission driver 500 may receive the emission clock signal ECLK from the timing controller 200 and generate the emission signal EM based on the emission clock signal ECLK.
For example, as shown in
The bias gate signal GB may have the activation period in the inactivation period of the emission signal EM. The activation period of the bias gate signal GB may be shorter than the N clock time of the emission clock signal ECLK.
For example, the activation period of the bias gate signal GB may be shorter than about 1290 μs. In addition, the activation period of the bias gate signal GB may have a difference of about 2 μs or more from the inactivation period of the emission signal EM.
Accordingly, since the activation period of the bias gate signal GB is shorter than the inactivation period of the emission signal EM, the bias gate signal GB may have the activation period in the inactivation period of the emission signal EM.
The display device according to an embodiment of the present inventive concept is substantially the same as the display device of
Referring to
For example, the second time point t2 and the fourth time point t4 of the display device of
For example, at a first time point t1, the bias gate signal GB may have the inactive level, and the seventh transistor T7 may be turned off. Accordingly, in embodiments, the second initialization voltage VAINT is not applied to the first electrode (e.g., the anode electrode) of the light emitting element EE.
Referring to
The display device according to an embodiment is substantially the same as the display device of
Referring to
For example, the third time point t3 and the fourth time point t4 of the display device of
For example, at the first time point t1, the bias gate signal GB may have the inactivation level, and the seventh transistor T7 may be turned off. Accordingly, in embodiments, the second initialization voltage VAINT is not applied to the first electrode (e.g., the anode electrode) of the light emitting element EE.
Referring to
Referring to
The processor 1010 may perform various computing functions. The processor 1010 may be, for example, a microprocessor, a central processing unit (CPU), an application processor (AP), etc. The processor 1010 may be coupled to other components via, for example, an address bus, a control bus, a data bus, etc. Further, the processor 1010 may be coupled to an extended bus such as, for example, a peripheral component interconnection (PCI) bus.
The memory device 1020 may store data for operations of the electronic device 1000. For example, the memory device 1020 may include at least one non-volatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistance random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc and/or at least one volatile memory device such as, for example, a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile DRAM device, etc.
The storage device 1030 may include, for example, a solid state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, etc.
The I/O device 1040 may include an input device such as, for example, a keyboard, a keypad, a mouse device, a touch pad, a touch screen, etc., and an output device such as, for example, a printer, a speaker, etc. In some embodiments, the I/O device 1040 may include the display device 1060.
The power supply 1050 may provide power for operations of the electronic device 1000. For example, the power supply 1050 may be a power management integrated circuit (PMIC).
The display device 1060 may display an image corresponding to visual information of the electronic device 1000. For example, the display device 1060 may be an organic light emitting display device or a quantum dot light emitting display device, but is not limited thereto. The display device 1060 may be coupled to other components via the buses or other communication links. The display device 1060 may initialize the anode of the light emitting element for a longer period. Accordingly, the display device 1060 may reduce the afterimage. Embodiments of the present inventive concept may be applied to any electronic device including the display device. For example, embodiments of the inventive concept may be applied to a television (TV), a digital TV, a 3D TV, a mobile phone, a smartphone, a tablet computer, a virtual reality (VR) device, a wearable electronic device, a personal computer (PC), a home appliance, a laptop computer, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, a navigation device, etc.
While the present inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the present inventive concept as defined by the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2022-0099299 | Aug 2022 | KR | national |
