Patent Application
20240038141
This application claims the priority of Chinese Patent Application No. 202111356204.5, filed on Nov. 16, 2021, in the China National Intellectual Property Administration, entitled “PIXEL CIRCUIT AND DISPLAY DEVICE”, the entire content of which is incorporated herein by reference.
The present application relates to a display technology field, in particular to a pixel circuit and a display device.
Low-frequency driving display is an important direction of display technology development. Most of the transistors used in conventional 7T1C (consisting of seven transistors and one storage capacitor) pixel circuits are low-temperature polysilicon transistors. One obvious disadvantage of such transistors is that the leakage current is large, and the display effect is severely affected under a condition of low-frequency display. A current solution is to replace the transistor connected to the driving transistor with a metal oxide transistor, which can alleviate the leakage current between the transistor and the driving transistor to a certain extent. However, when the display is driven at a low frequency, the screen dwell time is longer, and the driving transistor is subjected to a long-time electric stress to cause a threshold voltage shift, which causes the current flowing through the driving transistor to change, which further leads to a change in the luminance of the display panel to cause a flicker problem.
There is a technical problem in the current pixel circuit that the current flowing through the driving transistor changes during low-frequency display.
The present application provides a pixel circuit and a display device for alleviating a technical problem existing in the current pixel circuit that the current flowing through a driving transistor changes during a low-frequency display.
The present application provides a pixel circuit comprising:
In the pixel circuit of the present application, the pixel circuit further comprises a second reset unit, a first end of the second reset unit is electrically connected to the light emitting unit, a second end of the second reset unit is electrically connected to a second constant voltage signal input end, and a control end of the second reset unit is electrically connected to a second reset signal input end.
In the pixel circuit of the present application, the pixel circuit further comprises a third reset unit, a first end of the third reset unit is electrically connected to the light emitting unit, a second end of the third reset unit is electrically connected to the second constant voltage signal input end, and a control end of the third reset unit is electrically connected to a first scan signal input end.
In the pixel circuit of the present application, the light emitting control unit comprises a first light emitting control unit and a second light emitting control unit, the first light emitting control unit is electrically connected between the first power supply input end and the driving unit, and the second light emitting control unit is electrically connected between the driving unit and the light emitting unit.
In the pixel circuit of the present application, the first end of the first reset unit is electrically connected between the first light emitting control unit and the driving unit.
In the pixel circuit of the present application, the first end of the first reset unit is electrically connected between the driving unit and the second light emitting control unit.
In the pixel circuit of the present application, both the first end of the second reset unit and the first end of the third reset unit are electrically connected between the second light emitting control unit and the light emitting unit.
In the pixel circuit of the present application, the pixel circuit further comprises an input unit, a first end of the input unit is electrically connected between the first light emitting control unit and the driving unit, a second end of the input unit is electrically connected to a data signal input end, and a control end of the input unit is electrically connected to the first scan signal input end.
In the pixel circuit of the present application, the pixel circuit further comprises a compensation unit, a first end of the compensation unit is electrically connected to a control end of the driving unit, a second end of the compensation unit is electrically connected between the driving unit and the second light emitting control unit, and a control end of the compensation unit is electrically connected to a second scan signal input end.
In the pixel circuit of the present application, the pixel circuit further comprises an initializing unit, a first end of the initializing unit is electrically connected to the control end of the driving unit, a second end of the initializing unit is electrically connected to a third constant voltage signal input end, and a control end of the initializing unit is electrically connected to the second scan signal input end.
In the pixel circuit of the present application, the driving unit comprises a first transistor, the first light emitting control unit comprises a second transistor, and the second light emitting control unit comprises a third transistor.
In the pixel circuit of the present application, a gate, a source, and a drain of the second transistor are electrically connected to a first control signal input end, the first power supply input end, and a source of the first transistor, respectively, and a gate, a source, and a drain of the third transistor are electrically connected to a second control signal input end, a drain of the first transistor, and the light emitting unit, respectively.
In the pixel circuit of the present application, the first reset unit comprises a fourth transistor.
In the pixel circuit of the present application, a gate, a source, and a drain of the fourth transistor are electrically connected to the first reset signal input end, the first constant voltage signal input end, and a source or a drain of the first transistor, respectively.
In the pixel circuit of the present application, the second reset unit comprises a fifth transistor.
In the pixel circuit of the present application, a gate, a source, and a drain of the fifth transistor are electrically connected to the second reset signal input end, the second constant voltage signal input end, and the light emitting unit, respectively.
In the pixel circuit of the present application, the third reset unit comprises a sixth transistor.
In the pixel circuit of the present application, a gate, a source, and a drain of the sixth transistor are electrically connected to the first scan signal input end, the second constant voltage signal input end, and the light emitting unit, respectively.
In the pixel circuit of the present application, the compensation unit comprises a seventh transistor, the input unit comprises an eighth transistor, and the initializing unit comprises a ninth transistor;
The present application further provides a display device comprising a pixel circuit, the pixel circuit comprises:
A pixel circuit and a display device are provide by the present application, the pixel circuit includes a driving unit, a light emitting control unit electrically connected to the driving unit, and a first reset unit electrically connected to the driving unit, a first end of the first reset unit is electrically connected to the driving unit, a second end of the first reset unit is electrically connected to a first constant voltage signal input end, and a control end of the first reset unit is electrically connected to a first reset signal input end. In the present application, a first reset unit electrically connected to the driving unit is provided, and the voltage of the driving unit is adjusted by the first reset unit, thereby relieving the unidirectional electric stress applied to the driving unit during low-frequency display, stabilizing the current flowing through the driving unit, and further improving the display effect of the display device during low-frequency display.
In order to more clearly explain the technical solutions in the embodiments or prior art, the following will briefly introduce the drawings required in the description of the embodiments or prior art. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, without paying any creative work, other drawings can be obtained based on these drawings.
The description of the following embodiments refers to the attached drawings to illustrate specific embodiments in which the present disclosure can be implemented. The directional terms mentioned in the present disclosure, such as [up], [down], [front], [back], [left], [right], [inner], [outer], [side], etc., are only the direction of the attached drawings. Therefore, the directional terms used are used to describe and understand the present disclosure, rather than to limit the present disclosure. In the drawings, units with similar structures are indicated by the same reference numerals.
Embodiments of the present application provide a pixel circuit and a display device, the pixel circuit includes a driving unit, a light emitting control unit electrically connected to the driving unit, and a first reset unit electrically connected to the driving unit, a first end of the first reset unit is electrically connected to the driving unit, a second end of the first reset unit is electrically connected to a first constant voltage signal input end, and a control end of the first reset unit is electrically connected to a first reset signal input end. In the present application, a first reset unit electrically connected to the driving unit is provided, and the voltage of the driving unit is adjusted by the first reset unit, thereby relieving the unidirectional electric stress applied to the driving unit during low-frequency display, stabilizing the current flowing through the driving unit, and further improving the display effect of the display device during low-frequency display.
The structure and function of a pixel circuit provided by an embodiment of the present application will be described below with reference to the accompanying drawings.
In an embodiment, referring to
Specifically, the first light emitting control unit 21 is electrically connected between the first power supply input end VDD and the driving unit 10, and a control end of the first light emitting control unit 21 is electrically connected to a first control signal input end EM1; the second light emitting control unit 22 is electrically connected between the driving unit 10 and the light emitting unit L, and a control end of the second light emitting control unit 22 is electrically connected to a second control signal input end EM2; another end of the light emitting unit L is electrically connected to a second power supply input end VSS. A first end of the first reset unit 30 is electrically connected between the first light emitting control unit 21 and the driving unit 10, a second end of the first reset unit 30 is electrically connected to a first constant voltage signal input end V1, and a control end of the first reset unit is electrically connected to a first reset signal input end F1.
It may be understood that the first power supply input end VDD and the second power supply input end VSS provide voltage signals, respectively, and that the voltage provided by the first power supply input end VDD is greater than the voltage provided by the second power supply input end VSS; the first constant voltage signal input end V1 is configured to provide a specific constant voltage which can be set according to the demand of the driving unit 10; the first reset signal input end F1 is configured to provide a specific square wave signal, so as to control the first reset unit to periodically input a constant voltage inputted by the first constant voltage signal input end V1 to the driving unit 10, thereby alleviating a change in current of the driving unit 10 caused by a unidirectional electrical stress. In addition, with respect to the low-frequency display driving, the embodiment of the present application can control the resetting of the operating state of the driving unit 10 through the signal inputted from the first reset signal input end F1 under the premise of ensuring that the scan signal maintains the low-frequency scanning, so that the current flowing through the driving unit 10 is prevented from changing, and therefore the frequency of part of the scan signal does not need to be increased under the low-frequency driving. Therefore, the embodiment of the present application is further conducive to reducing the overall energy consumption of the pixel circuit.
Alternatively, the first control signal input end EM1 and the second control signal input end EM2 may input the same control signal or may input different control signals as necessary.
Further, the pixel circuit further includes a third reset unit 50, a compensation unit 60, an input unit 70, and an initializing unit 80. The third reset unit is configured to reset a voltage of an input end of the light emitting unit L; the compensation unit 60 is configured to compensate a voltage of a control end of the driving unit 10; the input unit 70 is configured to input a data signal and drive the light emitting unit L to emit light through the driving unit 10; the initializing unit 80 is configured to perform an initialization operation on a voltage of a control end of the driving unit 10.
A first end of the third reset unit 50 is electrically connected to the light emitting unit, a second end of the third reset unit 50 is electrically connected to a second constant voltage signal input end V2, and a control end of the third reset unit is electrically connected to a first scan signal input end S1. Wherein the first end and the second end of the third reset unit 50 respectively refer to an output end and an input end of the third reset unit 50; the second constant voltage signal input end V2 is configured to provide a specific voltage that can be set according to the demand of the light emitting unit L; the first scan signal input end S1 is configured to provide a periodic scan signal to control the third reset unit 50 to input the light emitting unit L with a specific voltage periodically input by the second constant voltage signal input end V2, thereby completing a reset operation of the light emitting unit L.
A first end of the compensation unit 60 is electrically connected to the control end of the driving unit 10, a second end of the compensation unit 60 is electrically connected between the driving unit 10 and the second light emitting control unit 22, and a control end of the compensation unit 60 is electrically connected to a second scan signal input end S2. Wherein the first and second ends of the compensation unit 60 refer to the output and input ends of the compensation unit 60, respectively; the second scan signal input end S2 is configured to provide a periodic scan signal to control the compensation unit 60 to select whether the control end of the driving unit 10 is electrically connected between the driving unit 10 and the second light emitting control unit 22.
A first end of the input unit 70 is electrically connected between the first light emitting control unit 21 and the driving unit 10, a second end of the input unit 70 is electrically connected to a data signal input end Da, and a control end of the input unit 70 is electrically connected to the first scan signal input end S1. Wherein the first and second ends of the input unit 70 refer to the output and input ends of the input unit 70, respectively; the data signal input end Da is configured to input a data signal; the scan signal inputted from the first scan signal input end S1 controls the input unit 70 to transmit the data signal to the driving unit 10, and the light emitting unit L is driven to emit light through the driving unit 10.
A first end of the initializing unit 80 is electrically connected to the control end of the driving unit 10, a second end of the initializing unit 80 is electrically connected to a third constant voltage signal input end V3, and a control end of the initializing unit 80 is electrically connected to the second scan signal input end S2. Wherein a first end and a second end of the initializing unit 80 refer to an output end and an input end of the initializing unit 80, respectively; the third constant voltage signal input end V3 is configured to provide an initial voltage; the scan signal inputted from the second scan signal input end S2 controls the initializing unit 80 to transmit the initial voltage supplied from the third constant voltage signal input end V3 to the control end of the driving unit 10, so as to implement an initialization operation on the control end of the driving unit 10.
Further, the driving unit 10 includes a first transistor T1, the first light emitting control unit 21 includes a second transistor T2, the second light emitting control unit 22 includes a third transistor T3, the first reset unit 30 includes a fourth transistor T4, the third reset unit 50 includes a sixth transistor T6, the compensation unit 60 includes a seventh transistor T7, the input unit 70 includes an eighth transistor T8, and the initializing unit 80 includes a ninth transistor T9.
Wherein a gate, a source and a drain of the second transistor T2 are electrically connected to the first control signal input end EM1, the first power supply input end VDD and a source of the first transistor T1, respectively, a gate, a source and a drain of the third transistor T3 are electrically connected to the second control signal input end EM2, a drain of the first transistor T1 and the light emitting unit L, respectively, a gate, a source and a drain of the fourth transistor T4 are electrically connected to the first reset signal input end F1, the first constant voltage signal input end V1 and the source or the drain of the first transistor T1, respectively, a gate, a source and a drain of the sixth transistor T6 are electrically connected to the first scan signal input end S1, the second constant voltage signal input end V2 and the light emitting unit L, respectively, a gate, a source and a drain of the seventh transistor T7 are electrically connected to the second scan signal input end S2, the gate of the first transistor T1 and the drain of the first transistor T1, respectively, a gate, a source and a drain of the eighth transistor T8 are electrically connected to the first scan signal input end S1, the data signal input end Da and the source of the first transistor T1, respectively, and a gate, a source and a drain of the ninth transistor T9 are electrically connected to the second scan signal input end S2, the third constant voltage signal input end V3 and the gate of the first transistor T1, respectively.
The pixel circuit further includes a first capacitor C1 and a second capacitor C2, opposite ends of the first capacitor C1 are electrically connected to the first power supply input end VDD and the gate of the first transistor T1, respectively, and opposite ends of the second capacitor C2 are electrically connected to the first scan signal input end S1 and the gate of the first transistor T1, respectively.
In another embodiment, referring to
The pixel circuit includes a driving unit 10, a light emitting control unit, a first reset unit 30, a third reset unit 50, a compensation unit 60, an input unit and an initializing unit 80. The light emitting control unit may include a first light emitting control unit 21 and a second light emitting control unit 22. The first reset unit is electrically connected between the driving unit 10 and the second light emitting control unit 22 for adjusting the current flowing through the driving unit 10.
The first light emitting control unit 21 is electrically connected between a first power supply input end VDD and the driving unit 10, and a control end of the first light emitting control unit 21 is electrically connected to the first control signal input end EM1; the second light emitting control unit 22 is electrically connected between the driving unit 10 and the light emitting unit L, and a control end of the second light emitting control unit 22 is electrically connected to a second control signal input end EM2; another end of the light emitting unit L is electrically connected to a second power supply input end VSS. A first end of the first reset unit is electrically connected between the driving unit 10 and the second light emitting control unit 22, a second end of the first reset unit 30 is electrically connected to a first constant voltage signal input end V1, and a control end of the first reset unit 30 is electrically connected to a first reset signal input end F1.
A first end of the third reset unit 50 is electrically connected to the light emitting unit L, a second end of the third reset unit 50 is electrically connected to a second constant voltage signal input end V2, and a control end of the third reset unit is electrically connected to a first scan signal input end S1. A first end of the compensation unit 60 is electrically connected to the control end of the driving unit a second end of the compensation unit 60 is electrically connected between the driving unit 10 and the second light emitting control unit 22, and a control end of the compensation unit 60 is electrically connected to a second scan signal input end S2. A first end of the input unit 70 is electrically connected between the first light emitting control unit 21 and the driving unit 10, a second end of the input unit 70 is electrically connected to a data signal input end Da, and a control end of the input unit 70 is electrically connected to the first scan signal input end S1. A first end of the initializing unit 80 is electrically connected to the control end of the driving unit 10, a second end of the initializing unit 80 is electrically connected to a third constant voltage signal input end V3, and a control end of the initializing unit 80 is electrically connected to the second scan signal input end S2.
Further, the driving unit 10 includes a first transistor T1, the first light emitting control unit 21 includes a second transistor T2, the second light emitting control unit 22 includes a third transistor T3, the first reset unit 30 includes a fourth transistor T4, the third reset unit 50 includes a sixth transistor T6, the compensation unit 60 includes a seventh transistor T7, the input unit 70 includes an eighth transistor T8, and the initializing unit 80 includes a ninth transistor T9.
Wherein a gate, a source and a drain of the second transistor T2 are electrically connected to the first control signal input end EM1, the first power supply input end VDD and a source of the first transistor T1, respectively, a gate, a source and a drain of the third transistor T3 are electrically connected to the second control signal input end EM2, a drain of the first transistor T1 and the light emitting unit L, respectively, a gate, a source and a drain of the fourth transistor T4 are electrically connected to the first reset signal input end F1, the first constant voltage signal input end V1 and the source or the drain of the first transistor T1, respectively, a gate, a source and a drain of the sixth transistor T6 are electrically connected to the first scan signal input end S1, the second constant voltage signal input end V2 and the light emitting unit L, respectively, a gate, a source and a drain of the seventh transistor T7 are electrically connected to the second scan signal input end S2, the gate of the first transistor T1 and the drain of the first transistor T1, respectively, a gate, a source and a drain of the eighth transistor T8 are electrically connected to the first scan signal input end S1, the data signal input end Da and the source of the first transistor T1, respectively, and a gate, a source and a drain of the ninth transistor T9 are electrically connected to the second scan signal input end S2, the third constant voltage signal input end V3 and the gate of the first transistor T1, respectively.
The pixel circuit further includes a first capacitor C1 and a second capacitor C2, opposite ends of the first capacitor C1 are electrically connected to the first power supply input end VDD and the gate of the first transistor T1, respectively, and opposite ends of the second capacitor C2 are electrically connected to the first scan signal input end S1 and the gate of the first transistor T1, respectively.
In another embodiment, referring to
The pixel circuit includes a driving unit 10, a light emitting control unit, a first reset unit 30, a second reset unit 40, a third reset unit 50, a compensation unit 60, an input unit 70, and an initializing unit 80. The light emitting control unit may include a first light emitting control unit 21 and a second light emitting control unit 22. The first reset unit 30 is electrically connected between the first light emitting control unit 21 and the driving unit 10 for adjusting a current flowing through the driving unit 10; the second reset unit 40 is electrically connected between the second light emitting control unit 22 and the light emitting unit L to reset the light emitting unit L.
The first light emitting control unit 21 is electrically connected between a first power supply input end VDD and the driving unit 10, and a control end of the first light emitting control unit 21 is electrically connected to the first control signal input end EM1; the second light emitting control unit 22 is electrically connected between the driving unit 10 and the light emitting unit L, and a control end of the second light emitting control unit 22 is electrically connected to a second control signal input end EM2; another end of the light emitting unit L is electrically connected to a second power supply input end VSS. A first end of the first reset unit 30 is electrically connected between the first light emitting control unit 21 and the driving unit 10, a second end of the first reset unit 30 is electrically connected to a first constant voltage signal input end V1, and a control end of the first reset unit 30 is electrically connected to a first reset signal input end F1.
A first end of the second reset unit 40 is electrically connected to the light emitting unit L, a second end of the second reset unit 40 is electrically connected to a second constant voltage signal input end V2, and a control end of the second reset unit 40 is electrically connected to a second reset signal input end F2. The second reset signal input end F2 is configured to provide a specific square wave signal to control the second reset unit 40 to periodically transmit the constant voltage inputted by the second constant voltage signal input end V2 to the light emitting unit L, thereby realizing a reset operation on the light emitting unit L.
Alternatively, the signal inputted from the second reset signal input end F2 and the signal inputted from the first reset signal input end F1 may be the same signal to implement simultaneous operation of the first reset unit 30 and the second reset unit 40. It may be understood that for the same frame screen driven by the low frequency display, the current flowing through the driving unit 10 is stabilized under the action of the first reset unit 30, and the current flowing to the light emitting unit L is stabilized under the action of the second reset unit 40, so that the light emitting unit L is ensured to emit light stably, and the flicker problem is prevented.
A first end of the third reset unit 50 is electrically connected to the light emitting unit L, a second end of the third reset unit 50 is electrically connected to a second constant voltage signal input end V2, and a control end of the third reset unit is electrically connected to a first scan signal input end S1. A first end of the compensation unit 60 is electrically connected to the control end of the driving unit a second end of the compensation unit 60 is electrically connected between the driving unit 10 and the second light emitting control unit 22, and a control end of the compensation unit 60 is electrically connected to a second scan signal input end S2. A first end of the input unit 70 is electrically connected between the first light emitting control unit 21 and the driving unit 10, a second end of the input unit 70 is electrically connected to a data signal input end Da, and a control end of the input unit 70 is electrically connected to the first scan signal input end S1. A first end of the initializing unit 80 is electrically connected to the control end of the driving unit 10, a second end of the initializing unit 80 is electrically connected to a third constant voltage signal input end V3, and a control end of the initializing unit 80 is electrically connected to the second scan signal input end S2.
Further, the driving unit 10 includes a first transistor T1, the first light emitting control unit 21 includes a second transistor T2, the second light emitting control unit 22 includes a third transistor T3, the first reset unit 30 includes a fourth transistor T4, the third reset unit 50 includes a sixth transistor T6, the compensation unit 60 includes a seventh transistor T7, the input unit 70 includes an eighth transistor T8, and the initializing unit 80 includes a ninth transistor T9.
Wherein a gate, a source and a drain of the second transistor T2 are electrically connected to the first control signal input end EVIL the first power supply input end VDD and a source of the first transistor T1, respectively, a gate, a source and a drain of the third transistor T3 are electrically connected to the second control signal input end EM2, a drain of the first transistor T1 and the light emitting unit L, respectively, a gate, a source and a drain of the fourth transistor T4 are electrically connected to the first reset signal input end F1, the first constant voltage signal input end V1 and the source or the drain of the first transistor T1, respectively, a gate, a source and a drain of the sixth transistor T6 are electrically connected to the first scan signal input end S1, the second constant voltage signal input end V2 and the light emitting unit L, respectively, a gate, a source and a drain of the seventh transistor T7 are electrically connected to the second scan signal input end S2, the gate of the first transistor T1 and the drain of the first transistor T1, respectively, a gate, a source and a drain of the eighth transistor T8 are electrically connected to the first scan signal input end S1, the data signal input end Da and the source of the first transistor T1, respectively, and a gate, a source and a drain of the ninth transistor T9 are electrically connected to the second scan signal input end S2, the third constant voltage signal input end V3 and the gate of the first transistor T1, respectively.
The pixel circuit further includes a first capacitor C1 and a second capacitor C2, opposite ends of the first capacitor C1 are electrically connected to the first power supply input end VDD and the gate of the first transistor T1, respectively, and opposite ends of the second capacitor C2 are electrically connected to the first scan signal input end S1 and the gate of the first transistor T1, respectively.
In another embodiment, referring to
The pixel circuit includes a driving unit 10, a light emitting control unit, a first reset unit 30, a second reset unit 40, a third reset unit 50, a compensation unit 60, an input unit 70, and an initializing unit 80. The light emitting control unit may include a first light emitting control unit 21 and a second light emitting control unit 22. The first reset unit 30 is electrically connected between the driving unit 10 and the second light emitting control unit 22 for adjusting a current flowing through the driving unit 10; the second reset unit 40 is electrically connected between the second light emitting control unit 22 and the light emitting unit L to reset the light emitting unit L.
The first light emitting control unit 21 is electrically connected between a first power supply input end VDD and the driving unit 10, and a control end of the first light emitting control unit 21 is electrically connected to the first control signal input end EM1; the second light emitting control unit 22 is electrically connected between the driving unit 10 and the light emitting unit L, and a control end of the second light emitting control unit 22 is electrically connected to a second control signal input end EM2; another end of the light emitting unit L is electrically connected to a second power supply input end VS S.
A first end of the first reset unit 30 is electrically connected between the driving unit 10 and the second light emitting control unit 22, a second end of the first reset unit 30 is electrically connected to a first constant voltage signal input end V1, and a control end of the first reset unit 30 is electrically connected to a first reset signal input end F1. A first end of the second reset unit 40 is electrically connected to the light emitting unit L, a second end of the second reset unit 40 is electrically connected to a second constant voltage signal input end V2, and a control end of the second reset unit 40 is electrically connected to a second reset signal input end F2.
A first end of the third reset unit 50 is electrically connected to the light emitting unit L, a second end of the third reset unit 50 is electrically connected to a second constant voltage signal input end V2, and a control end of the third reset unit is electrically connected to a first scan signal input end S1. A first end of the compensation unit 60 is electrically connected to the control end of the driving unit a second end of the compensation unit 60 is electrically connected between the driving unit 10 and the second light emitting control unit 22, and a control end of the compensation unit 60 is electrically connected to a second scan signal input end S2. A first end of the input unit 70 is electrically connected between the first light emitting control unit 21 and the driving unit 10, a second end of the input unit 70 is electrically connected to a data signal input end Da, and a control end of the input unit 70 is electrically connected to the first scan signal input end S1. A first end of the initializing unit 80 is electrically connected to the control end of the driving unit 10, a second end of the initializing unit 80 is electrically connected to a third constant voltage signal input end V3, and a control end of the initializing unit 80 is electrically connected to the second scan signal input end S2.
Further, the driving unit 10 includes a first transistor T1, the first light emitting control unit 21 includes a second transistor T2, the second light emitting control unit 22 includes a third transistor T3, the first reset unit 30 includes a fourth transistor T4, the third reset unit 50 includes a sixth transistor T6, the compensation unit 60 includes a seventh transistor T7, the input unit 70 includes an eighth transistor T8, and the initializing unit 80 includes a ninth transistor T9.
Wherein a gate, a source and a drain of the second transistor T2 are electrically connected to the first control signal input end EM1, the first power supply input end VDD and a source of the first transistor T1, respectively, a gate, a source and a drain of the third transistor T3 are electrically connected to the second control signal input end EM2, a drain of the first transistor T1 and the light emitting unit L, respectively, a gate, a source and a drain of the fourth transistor T4 are electrically connected to the first reset signal input end F1, the first constant voltage signal input end V1 and the source or the drain of the first transistor T1, respectively, a gate, a source and a drain of the sixth transistor T6 are electrically connected to the first scan signal input end S1, the second constant voltage signal input end V2 and the light emitting unit L, respectively, a gate, a source and a drain of the seventh transistor T7 are electrically connected to the second scan signal input end S2, the gate of the first transistor T1 and the drain of the first transistor T1, respectively, a gate, a source and a drain of the eighth transistor T8 are electrically connected to the first scan signal input end S1, the data signal input end Da and the source of the first transistor T1, respectively, and a gate, a source and a drain of the ninth transistor T9 are electrically connected to the second scan signal input end S2, the third constant voltage signal input end V3 and the gate of the first transistor T1, respectively.
The pixel circuit further includes a first capacitor C1 and a second capacitor C2, opposite ends of the first capacitor C1 are electrically connected to the first power supply input end VDD and the gate of the first transistor T1, respectively, and opposite ends of the second capacitor C2 are electrically connected to the first scan signal input end S1 and the gate of the first transistor T1, respectively.
The operation of the pixel circuit shown in
With respect to
As the driving frequency decreases, for example, 60 Hz, 30 Hz, 24 Hz, 15 Hz, and a random frequency less than 120 Hz, stages in which the pixel circuit drives the display device includes also includes a reset duration stage RF, in this case, the time interval between the two adjacent display stages DS increases, during this period, the current flowing through the driving unit 10 has a tendency to change, so that the reset duration stage RF is added; during the reset duration stage RF, the first reset unit 30 is operated to adjust the electrical stress applied to the driving unit 10, so as to stabilize the current flowing through the driving unit 10, thereby preventing flicker.
As shown in
In the display stage DS, the pixel circuit drives the display device to perform display under the action of the signals NS(n−1), NS(n), PS(n−1), PS(n) and EM, and in a short time before the arrival of the reset duration stage RF, the reset signal RT turns on the first reset unit 30 to perform a reset operation on the driving unit 10. During the reset duration stage RF, several scan signals, such as NS(n−1), NS(n), PS(n−1), and PS(n), are maintained at a constant voltage, and during this period, the reset signal RT may turn on the first reset unit 30 again or multiple times as necessary to reset the driving unit 10 again or multiple times, so as to maintain the stability of the current flowing through the driving unit 10.
An embodiment of the present application further provides a display device including the pixel circuit of any one of the above embodiments. The display device may be an organic light emitting diode display device, a micro light emitting diode display device, or a display, a notebook computer, a tablet computer, a television set, a mobile phone, or the like, which include the display device.
It should be noted that, although the present application discloses the foregoing embodiments, the foregoing embodiments are not intended to limit the present application. A person of ordinary skill in the art may make various changes and finishes without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application is subject to the scope defined by the claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202111356204.5 | Nov 2021 | CN | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2021/140585 | 12/22/2021 | WO |
