Patent Application
20240087520
The present disclosure relates to a current-driven display device having a display element driven by current such as an organic EL (Electro Luminescence) element, and more particularly to a pixel circuit used in the display device.
In recent years, an organic EL display device having a pixel circuit including an organic EL element (also called an organic light-emitting diode (OLED)) has been put to practical use. A pixel circuit in an organic EL display device includes a drive transistor, a write control transistor, a holding capacitor, etc., in addition to the organic EL element. A thin film transistor is used as the drive transistor and the write control transistor, and a holding capacitor is connected to a gate terminal serving as a control terminal of the drive transistor. A voltage corresponding to a video signal representing an image to be displayed (more specifically, a voltage representing a gradation value of a pixel to be formed by the pixel circuit) is applied as a data voltage. An organic EL element is a self-luminous display element that emits light with luminance corresponding to a current flowing through the organic EL element. The drive transistor is provided in series with the organic EL element and controls the current flowing through the organic EL element in accordance with a voltage held in the holding capacitor.
Variations and shifts occur in the characteristics of organic EL elements and drive transistors. Therefore, it is necessary to compensate for the variations and shifts in the characteristics of these elements in order to display high quality images in an organic EL display device. For organic EL displays, there are two known methods of compensating for the characteristics of the elements: one is to compensate for the characteristics of the elements inside the pixel circuit and the other is to compensate for the characteristics outside the pixel circuit. As a pixel circuit corresponding to the former method, a pixel circuit is known in which the voltage at the gate terminal of the drive transistor, i.e., the voltage held in the holding capacitor, is initialized and then the holding capacitor is charged with the data voltage via the drive transistor in diode connection state. In such a pixel circuit, variations and shifts in the threshold voltage of the drive transistor are compensated for internally (such compensation of variations and shifts in the threshold voltage is hereinafter referred to as “threshold compensation,” and the method in which threshold compensation is performed within the pixel circuit is called the “internal compensation method”).
A pixel circuit using a P-channel thin film transistor whose channel layer is formed of low temperature polysilicon (LTPS) is known as a pixel circuit of an organic EL display device that employs an internal compensation method. Since low-temperature polysilicon has high mobility, using a thin-film transistor whose channel layer is formed of low-temperature polysilicon (hereinafter referred to as “LTPS-TFT”) as a drive transistor improves the drive capability for the organic EL element in the pixel circuit, and when used as a switching element, the on-resistance is low.
In recent years, a thin film transistor (hereinafter referred to as “oxide TFT”) whose channel layer is formed of oxide semiconductor has attracted attention. Since the oxide TFT has a small off-leak current, it is suitable as a switching element in a pixel circuit or the like. Note that as the oxide TFT, a thin film transistor (hereinafter referred to as “IGZO-TFT”) containing indium gallium zinc oxide (InGaZnO) is typically used.
Furthermore, in order to implement a pixel circuit that combines the features of the LTPS-TFT, which can increase the drive capability of the drive transistor and reduce the on-resistance of the switching element, and the features of the oxide TFT, which can reduce the off-leakage current of the switching element, a pixel circuit in which P-channel type (hereinafter also referred to as “P-type”) LTPS-TFTs and N-channel type (hereinafter also referred to as “N-type”) oxide TFTs are mixed is also known (see, for example, Japanese Unexamined Patent Application Publication No. 2018-5237).
The present inventors have confirmed that the following problem may occur: when black is to be displayed in a pixel circuit in which P-type transistors and N-type transistors are mixed (hereinafter referred to as “hybrid-type pixel circuit”) such as the pixel circuit in which LTPS-TFTs and oxide TFTs are mixed as described above, the luminance of the pixel circuit cannot be reduced to a sufficiently low value (the problem is hereinafter referred to as “black display defect”).
Therefore, it is desired to prevent the above-described black display defects from occurring in display devices that use hybrid-type pixel circuits with a mixture of P-type and N-type transistors.
Several embodiments of the present invention provide a pixel circuit provided in a display device with a display portion including a plurality of data signal lines, a plurality of first scanning signal lines, and a plurality of second scanning signal lines, the pixel circuit corresponding to one of the data signal lines, one of the first scanning signal lines, and one of the second scanning signal lines, the pixel circuit including:
Several other embodiments of the present invention provide a display device with a display portion including a plurality of data signal lines, a plurality of first scanning signal lines, and a plurality of second scanning signal lines, the display device including:
According to the above several embodiments of the present invention, in the display device with a display portion including a plurality of data signal lines, a plurality of first scanning signal lines, and a plurality of second scanning signal lines, there is provided a pixel circuit so as to correspond to one of the data signal lines, one of the first scanning signal lines, and one of the second scanning signal lines. In the pixel circuit, when the corresponding first scanning signal line and the corresponding second scanning signal line are in the selected state, the voltage of the corresponding data signal lines is written to the holding capacitor via the writing control transistor in ON state and the drive transistor brought into a diode-connected state by the threshold compensation transistor in ON state. After the end of the data voltage write operation, when the corresponding second scanning signal line is deselected and thereby the threshold compensating transistor changes from ON state to OFF state, a change in the voltage of the corresponding second scanning signal line affects the control voltage, which is the voltage of the control terminal of the drive transistor (which corresponds to the voltage written to the holding capacitor) through the parasitic capacitance of the threshold compensation transistor, causing the control voltage to change. Further, when the corresponding first scanning signal line is deselected and thereby the write control transistor changes from ON state to OFF state, a change in the voltage of the corresponding first scanning signal line affects the voltage (control voltage) of the control terminal of the drive transistor via the capacitance between the corresponding first scanning signal line and the control terminal of the drive transistor, causing the control voltage to change. Since the conductivity type of the write control transistor and the conductivity type of the threshold compensation transistor are different from each other, the voltage of the corresponding first scanning signal line at this time changes in the direction opposite to the voltage change of the corresponding second scanning signal line. Therefore, the control voltage change caused by the voltage change of the corresponding second scanning signal line can be compensated for (cancelled or reduced) by the control voltage change caused by the voltage change of the corresponding first scanning signal line based on the above capacitance. As a result, it is possible to prevent the problem that the luminance of the display element cannot be suppressed to a sufficiently low value when black is to be displayed in a hybrid pixel circuit in which P-type and N-type transistors are mixed, that is, black display defects can be prevented.
Embodiments will be described below with reference to the accompanying drawings. In each transistor referred to below, a gate terminal corresponds to a control terminal, one of a drain terminal and a source terminal corresponds to a first conduction terminal, and the other corresponds to a second conduction terminal. Further, although the transistors in the following embodiments are, for example, thin film transistors, the present invention is not limited to this. Furthermore, unless otherwise specified, the term “connection” herein refers to “electrical connection”, the meaning of which encompasses not only direct connection but also indirect connection through another or other elements, without departing from the gist of the present invention.
As shown in
The display portion 11 has provided therein m (where m is an integer of 2 or more) data signal lines D1, D2, . . . , Dm, n first scanning signal lines PS1, PS2, . . . , PSn, and n+2 (where n is an integer of 2 or more) second scanning signal lines NS−1, NS0, NS1, . . . , NSn, and the first and second scanning signal lines intersect the data signal lines. Moreover, there are n emission control lines (emission lines) EM1 to EMn respectively provided along the n first scanning signal lines PS1 to PSn. Further, the display portion 11 is provided with m×n pixel circuits 15 arranged in a matrix along the m data signal lines D1 to Dm and the n first scanning signal lines PS1 to PSn. Each pixel circuit 15 corresponds to one of the m data signal lines D1 to Dm and one of the n first scanning signal lines PS1 to PSn (to distinguish the pixel circuits 15, the pixel circuit that corresponds to the ith first scanning signal line PSi and the jth data signal line Dj will also be referred to below as the “ith-row, jth-column pixel circuit” and denoted by the symbol “Pix(i,j)”). Moreover, each pixel circuit 15 also corresponds to one of the n second scanning signal lines NS1 to NSn and one of the n emission control lines EM1 to EMn.
In the display portion 11, a power supply line (not shown) common to each of the pixel circuits 15 is arranged. That is, a first power supply line for supplying a high-level power supply voltage ELVDD for driving an organic EL element to be described later (hereinafter referred to as a “high-level power supply line” and indicated by the symbol “ELVDD” like the high-level power supply voltage), and a second power supply line for supplying a low-level power supply voltage ELVSS for driving the organic EL element (hereinafter referred to as a “low-level power supply line” and indicated by the symbol “ELVSS” like the low-level power supply voltage) are arranged. More specifically, the low-level power supply line ELVSS is a common cathode for the multiple pixel circuits 15. Further, the display portion 11 is also provided with an initialization voltage line (not shown) for supplying an initialization voltage Vini used for initialization of each pixel circuit 15 (indicated by the symbol “Vini” as well as the initialization voltage). The high-level power supply voltage ELVDD, the low-level power supply voltage ELVSS, and the initialization voltage Vini are supplied from the power supply circuit 50.
The display control circuit 20 receives an input signal Sin including image information representing an image to be displayed and timing control information for image display from the outside of the display device 10, generates a data-side control signal Scd and a scanning-side control signal Scs based on the input signal Sin, and outputs the data-side control signal Scd and the scanning-side control signal Scs to the data-side drive circuit 30 and the scanning-side drive circuit 40, respectively.
The data-side drive circuit 30 drives the data signal lines D1 to Dm based on the data-side control signal Scd from the display control circuit 20. That is, the data-side drive circuit 30 generates m data signals D(1) to D(m) representing images to be displayed based on the data-side control signal Scd, and applies them to the data signal lines D1 to Dm, respectively.
Based on the scanning-side control signal Scs from the display control circuit 20, the scanning-side drive circuit 40 functions as a signal line drive circuit configured to drive the n first scanning signal lines PS1 to PSn and the n+2 second scanning signal lines NS−1 to NSn, and also functions as an emission control circuit configured to drive the n emission control lines EM1 to EMn.
More specifically, during each frame period, the scanning-side drive circuit 40 sequentially selects the n first scanning signal lines PS1 to PSn each for a predetermined period corresponding to one horizontal period and sequentially selects the n+2 second scanning signal lines NS−1 to NSn each for a predetermined period corresponding to one horizontal period, based on the scanning-side control signal Scs, applies an active signal to the selected first scanning signal line PSk (k is an integer of 1≤k≤n), applies an active signal to the selected the second scanning signal line NSs (s is an integer of −1≤s≤n), applies an inactive signal to the
to the unselected first scanning signal lines, and an inactive signal to the unselected second scanning signal lines. Thus, m pixel circuits Pix(k, l) to Pix(k, m) corresponding to the selected first scanning signal line Gk (1≤k≤n) are selected collectively. As a result, the voltages of the m data signals D(1) to D(m) (hereinafter, these voltages may be simply referred to as “data voltages” without distinction) applied from the data-side drive circuit 30 to the data signal lines D1 to Dm in a selection period for the first scanning signal line PSk (hereinafter referred to as “kth scanning selection period”) are written as pixel data to the pixel circuits Pix(k, l) to Pix(k, m), respectively. As shown in
Furthermore, during each frame period, the scanning-side drive circuit 40 drives the emission control lines EM1 to EMn such that the emission control lines EM1 to EMn are selectively deactivated in conjunction with the driving of the first and second scanning signal lines PS1 to PSn and NS−1 to NSn. More specifically, the scanning-side drive circuit 40 functions as the emission control circuit in accordance with the scanning-side control signal Scs to apply an emission control signal that specifies non-emission (a high-level voltage) to the ith emission control line EMi (where i=1 to n) during a predetermined period of time including the ith horizontal period and an emission control signal that specifies emission (a low-level voltage) during other periods (details will be described later). While the voltage of the emission control line EMi is at low level (active), the organic EL elements in the pixel circuits Pix(i,l) to Pix(i,m) corresponding to the ith first scanning signal line PSi (referred to below as the “ith-row pixel circuits”) emit light with respective luminances that correspond to the data voltages written in the ith-row pixel circuits Pix(i,l) to Pix(i,m).
In the present embodiment, the first scanning signal lines PS1 to PSn, the second scanning signal lines NS−1 to NSn, the emission control lines EM1 to EMn, and the data signal lines D1 to Dm are driven as described above, in accordance with the signals shown in
As will be described later, in the present embodiment, in each frame period, data write operation is performed for each pixel circuit Pix(i, j) when the corresponding first and second scanning signal lines PSi, NSi are in the selected state. When the second scanning signal line NSi−2 two lines prior to the second scanning signal line NSi is in the selected state, an initialization operation of a holding capacitor Cst (this corresponds to an initialization operation of voltage of a gate terminal of a drive transistor T4 and is hereinafter also referred to as “control voltage initialization operation”) is performed. When the second scanning signal line NSi−1 immediately preceding the second scanning signal line NSi is in the selected state, an initialization operation of voltage of an anode electrode in the organic EL element OL (hereinafter also referred to as an “anode voltage initializing operation”) is performed. The emission control line EMi is driven such that each pixel circuit Pix (i, j) is in a non-emission state when the data write operation, the control voltage initialization operation, and the anode voltage initialization operation are performed therein (i=1 to n) (see
The operation outline of the display device 10 according to the present embodiment is as described above. Alternatively, the display device 10 may be configured to have two operating modes: a normal drive mode and a pause drive mode. In this case, in the normal drive mode, the image data (data voltage in each pixel circuit) of the display portion 11 is rewritten in each frame period as above. In the pause drive mode, a drive period, which consists only of a refresh frame period for rewriting the image data, alternates with a pause period, which consists of a plurality of non-refresh frame periods for stopping the rewriting of the image data in the display portion 11.
In the following, first, the configuration and operation of a pixel circuit (hereinafter also referred to as “comparative pixel circuit”) in a display device as a comparative example of the present embodiment will be described, and then, the configuration and operation of the pixel circuit 15 in the present embodiment will be described in comparison with the configuration and operation of the pixel circuit in the comparative example. Note that since the configuration of the display device as the comparative example is the same as that of the display device according to the present embodiment except for the pixel circuit, the same or corresponding parts are denoted by the same reference numerals and the description thereof is omitted.
As described above, the inventors of the present application have confirmed that in the hybrid pixel circuit, in which a P-type transistor and an N-type transistor are mixed, a problem (black display defect) may occur in which the luminance cannot be suppressed to a sufficiently low value when black is to be displayed. The following describes the configuration and operation of the pixel circuit in the comparative example with reference to the mechanism causing the black display defect.
The pixel circuit Pix(i,j) is connected to the first scanning signal line PSi that corresponds to the pixel circuit Pix(i,j) (also referred to below as the “corresponding first scanning signal line” in the description focusing on the pixel circuit), the second scanning signal line NSi that corresponds to the pixel circuit Pix(i,j) (also referred to below as the “corresponding second scanning signal line” in the description focusing on the pixel circuit), the second scanning signal line that is two lines prior to the corresponding second scanning signal line NSi (the scanning signal line preceding by two lines in the order of scanning the second scanning signal lines NS−1 to NSn), i.e., the (i−2)th second scanning signal line NSi−2 (also referred to below as the “preceding second scanning signal line” in the description focusing on the pixel circuit), the second scanning signal line immediately preceding the corresponding second scanning signal line NSi, i.e., the (i−1)th second scanning signal line NSi−1 (also referred to below as the “immediately preceding second scanning signal line” in the description focusing on the pixel circuit), the emission control line EMi that corresponds to the pixel circuit Pix(i,j) (also referred to below as the “corresponding emission control line” in the description focusing on the pixel circuit), the data signal line Dj that corresponds to the pixel circuit Pix(i,j) (also referred to below as the “corresponding data signal line” in the description focusing on the pixel circuit), the initialization voltage line Vini, the high-level power supply line ELVDD, and the low-level power supply line ELVSS.
The first initialization transistor T1 has a gate terminal connected to the preceding second scanning signal line NSi−2, and a drain terminal connected to the first electrode of the holding capacitor Cst, a gate terminal of the drive transistor T4, and a source terminal of the threshold compensation transistor T2. The second initialization transistor T7 has a gate terminal connected to the immediately preceding second scanning signal line NSi−1, a source terminal connected to the initialization voltage line Vini, and a drain terminal connected to the anode electrode of the organic EL element OL.
The threshold compensation transistor T2 has a gate terminal connected to the corresponding second scanning signal line NSi, a drain terminal connected to a drain terminal of the drive transistor T4 and a source terminal of the second emission control transistor T6, and a source terminal connected to the gate terminal of the drive transistor T4.
The write control transistor T3 has a gate terminal connected to the corresponding first scanning signal line PSi, a source terminal connected to the corresponding data signal line Dj, and a drain terminal connected to a source terminal of the drive transistor T4 and the first emission control transistor T5.
The drive transistor T4 has the gate terminal connected to the first electrode of the holding capacitor Cst, the source terminal connected to the drain terminal of the write control transistor T3 and a drain terminal of the first emission control transistor, and the drain terminal connected to the source terminal of the second emission control transistor T6.
The first emission control transistor T5 has a gate terminal connected to the corresponding emission control line EMi, a source terminal connected to the high-level power supply line ELVDD, and the drain terminal connected to the source terminal of the drive transistor T4. The second emission control transistor T6 has a gate terminal connected to the corresponding emission control line EMi, the source terminal connected to the drain terminal of the drive transistor 14, and a drain terminal connected to the anode electrode of the organic EL element OL.
The holding capacitor Cst has the first electrode connected to the gate terminal of the drive transistor T4 and a second electrode connected to the high-level power supply line ELVDD. The organic EL element OL has the anode electrode connected to the drain terminal of the second emission control transistor T6, and a cathode electrode connected to the low-level power supply line ELVSS.
Next, the operation of the pixel circuit 14 shown in
A emission control signal (hereinafter referred to as a “corresponding emission control signal”) EM(i) supplied to the pixel circuit Pix(i,j) of
During the period when the pixel circuit Pix(i, j) is in the non-emission state, i.e., the non-emission period t1 to t8, the second scanning signal (hereinafter also referred to as “preceding second scanning signal”) NS(i−2) supplied to the pixel circuit Pix (i, j) via the preceding second scanning signal line NSi−2 changes from L level to H level, thereby causing the N-type first initialization transistor T1 to change from OFF state to ON state and to maintain ON state while the second scanning signal NS(i−2) is at H level. During the period when the first initialization transistor T1 is in ON state (hereinafter referred to as the “initialization period”) from t2 to t4, the holding capacitor Cst is initialized and the voltage of node N1 including the gate terminal of drive transistor T4 and the first electrode of holding capacitor Cst becomes the initialization voltage Vini. In other words, the voltage of the gate terminal of drive transistor T4 (hereinafter referred to as “gate voltage”) Vg becomes the initialization voltage Vini.
At time t3 within the non-emission period t1 to t8 of the pixel circuit Pix(i,j) in
During the period t4 to t7 when the threshold compensation transistor T2 is in ON state, the first scanning signal PS(i) (hereinafter also referred to as the “corresponding first scanning signal”) is supplied to the pixel circuit Pix(i,j) through the corresponding first scanning signal line PSi changes from H level to L level at time t5. As a result, the P-type write control transistor T3 changes from OFF state to ON state, and maintains ON state while the corresponding first scanning signal PS(i) is at L level. During the period t5 to t6 when the write control transistor T3 is in ON state (hereinafter referred to as a “data write period”), a data signal D(j) supplied to the pixel circuit Pix(i,j) via the corresponding data signal line Dj is provided as the data voltage Vdata to the holding capacitor Cst through the diode-connected drive transistor 14. As a result, the threshold-compensated data voltage is written and held in the holding capacitor Cst, and the gate voltage Vg of the drive transistor T4 is maintained at the voltage of the first electrode of the holding capacitor Cst. At this time, the gate voltage Vg has a value given by the following equation, where Vth (<0) is a threshold value of the drive transistor T4.
Vg=Vdata+Vth (1)
In this way, during the data write period t5 to t6, the data voltage is written while performing the internal compensation.
At time t7 after the data write period t5 to t6, the corresponding second scanning signal NS(i) changes from H level to L level, and the threshold compensation transistor T2 is turned off. The voltage change (change from H to L) of the corresponding second scanning signal NS(i) affects the voltage of the node N1, i.e., the gate voltage Vg via the parasitic capacitance Cgs between the gate and source of the threshold compensation transistor T2, the gate voltage Vg decreases by ΔVf from the value represented by the above equation (1). This voltage drop ΔVf (>0) is a pull-in voltage caused by the change of the N-type threshold compensation transistor T2 from ON state to OFF state.
After that, at time t8, the corresponding emission control signal EM(i) changes from H level to L level, thereby turning on the first and second emission control transistors T5 and T6, and the emission period starts. During the emission period, a current I1 corresponding to the voltage held in the holding capacitor Cst, i.e., the voltage (absolute value) |Vgs| between the gate and source of the drive transistor T4, flows from the high-level power supply line ELVDD to the low-level power supply line ELVSS by way of the first emission control transistor T5, the drive transistor T4, the second emission control transistor T6, and the organic EL element OL. As a result, the organic EL element OL emits light with luminance corresponding to the current I1.
As described above, the voltage of the node N1, i.e., the gate voltage Vg, drops by the pull-in voltage ΔVf when the threshold compensation transistor T2 changes from ON state to OFF state at time t7. Here, a specific voltage setting example for the pixel circuit is shown. The H level voltage is 8 V, the L level voltage is −8 V, the voltage range of the data signal line Di is 1 to 6 V, the white voltage is 1 V, and the black voltage is 6 V (in this case, for example, the high-level power supply voltage ELVDD is 5V, the low-level power supply voltage ELVSS is −5V, and the initialization voltage Vini is −5V). In such a voltage setting example, when the threshold compensation transistor T2 is turned off, its gate voltage Vg, i.e., the voltage of the corresponding second scanning signal NS(i) changes from 8V to −8V, and the pull-in voltage ΔVf caused by this voltage change is non-negligible compared to the voltage range of the data signal line Di (1 to 6V).
Since such a pull-in voltage ΔVf is generated when the threshold compensation transistor T2 turns off, the voltage |Vgs| between the gate and source of drive transistor 14 becomes larger by the pull-in voltage ΔVf than the voltage written to the holding capacitor Cst during the data write period t5 to t6 (“write voltage”). Thus, the above current I1 flowing through the drive transistor T4 and the organic EL element increases, and as a result the organic EL element emits light with luminance higher than that corresponding to the write voltage to the holding capacitor Cst. In other words, the organic EL element OL emits light with luminance higher than that corresponding to the data signal D(j) due to the decrease in the gate voltage Vg caused by the voltage change in the corresponding second scanning signal NS(i). Therefore, in order to make the luminance of the organic EL element OL be a lower value corresponding to black display when black is to be displayed, the voltage of the data signal D(j) indicating black may be increased. However, if the voltage of the data signal D(j) (black voltage) is made higher, the margin for the voltage range that can be output from the data-side drive circuit 30 to the data signal line Dj becomes smaller. This may cause a defect that the luminance of the organic EL element OL cannot be suppressed to a sufficiently low value when black is to be displayed, that is, a black display defect may occur.
In addition to the corresponding second scanning signal NS(i), any signal that changes from H level to L level after the data write period t5 to t6 may cause a black display defect. For example, the emission control signal EM(i), which changes from H level to L level at time t8, may also be a cause of “black display defect”. However, even in the case that such a signal is used, if the capacitive coupling between the signal line transmitting the such a signal and the node N1 is negligible (the parasitic capacitance between the signal line and the node N1 is negligible), the such a signal is not a cause of black display defect. When a layout pattern as described below is adopted for the pixel circuit (see
The pixel circuit Pix(i, j) in
The basic connection configuration of the pixel circuit Pix(i, j) in the present embodiment, that is, the connection relationship among the components T1 to T7, Cst, and OL in the pixel circuit Pix(i, j), and the connection relationship with the components T1 to T7, Cst, OL regarding the signal lines NSi, NSi−1, NSi−2, PSi, EMi, Dj, the power supply lines ELVDD, ELVSS, and the initialization voltage line Vini which are connected to the pixel circuits Pix(i, j), are as shown in
Next, the operation of the pixel circuit 15 shown in
As can be seen by comparing
However, as described above, in the pixel circuit 15 in the present embodiment, the compensation capacitor Cscg is provided between the node N1 including the gate terminal of the drive transistor T4 and the corresponding first scanning signal line PSi. The change in the gate voltage Vg of the transistor T4 is different from the change in the gate voltage Vg in the pixel circuit 14 in the comparative example. The operation of the pixel circuit 15 will be described below, focusing on this difference. Note that a detailed description will be omitted for the parts of this operation that are the same as the operation of the pixel circuit 14 in the comparative example.
Also in the present embodiment, the gate voltage Vg of the drive transistor T4 becomes the initialization voltage Vini at time t2 through the initialization operation by the first initialization transistor T1 during the period t2 to t4, and is maintained at the initialization voltage Vini until time t5. Thereafter, the gate voltage Vg becomes the data voltage Vdata+Vth with threshold compensation through the data write operation by the write control transistor T3 during the period t5 to t6 (with compensation operation by the threshold compensation transistor T2) (see equation (1) already described). However, unlike the comparative example, in the present embodiment, when the write control transistor T3 turns off at time t6 by the corresponding first scanning signal PS(i) changing from L level to H level, the voltage change of the corresponding first scanning signal PS(i) affects the voltage of the node N1, i.e., the gate voltage Vg, via compensation capacitance Cscg, with the result that the gate voltage Vg is increased from Vdata+Vth. This increase in gate voltage Vg (hereinafter referred to as “compensation voltage”) ΔVc (>0) is determined by the voltage change of the corresponding first scanning signal PS(i) and the capacitance values of the holding capacitor Cst and the compensation capacitance Cscg, etc., and can be adjusted with the compensation capacitance Cscg.
At time t7 after the data write period t5 to t6, as in the comparative example, when the corresponding second scanning signal NS(i) changes from H level to L level and the threshold compensation transistor T2 turns off in the present embodiment, this voltage change in the corresponding second scanning signal NS(i) affects the gate voltage Vg of the drive transistor T4 via the parasitic capacitance of the threshold compensation transistor T2 Cgs, so that the gate voltage Vg decreases by the pull-in voltage ΔVf. However, as described above, the gate voltage rises by ΔVc at time t6 through the compensation capacitance Cscg. Therefore, after time t7, the gate voltage Vg becomes as follows:
Vg=Vdata+Vth+ΔVc−ΔVf (2)
Therefore, during the emission period after time t8, the current I1 corresponding to the voltage (absolute value) |Vgs| between the gate and source of drive transistor T4 based on the gate voltage Vg represented by the above equation (2) flows through the drive transistor T4 and the organic EL element OL, and the organic EL element OL emits light with luminance corresponding to the current I1.
As can be seen from the above equation (2), the voltage drop (pull-in voltage) ΔVf, which occurs when the corresponding second scanning signal NS(i) changes from H level to L level, can be compensated by the voltage increase ΔVc through the compensation capacitance Cscg for the gate voltage Vg of drive transistor T4.
The layout pattern for implementing the pixel circuit 15 (
In
As shown in
Next, the features of the layout pattern of the pixel circuit 15 in the present embodiment will be described with reference to
As already mentioned, in the layout pattern of the pixel circuit 15 shown in
In contrast, in the layout pattern as the comparative example, as shown in
In the layout pattern shown in
In the layout patterns of
According to the present embodiment as described above, in the hybrid pixel circuit 15 in which P-type transistors and N-type transistors are mixed by including both LIPS-TFTs and IGZO-TFTs as oxide TFTs, the compensation capacitor Cscg is formed between the node N1 including the gate terminal of the drive transistor 14 and the corresponding first scanning signal line PSi (
Furthermore, by adopting the layout pattern shown in
Next, an organic EL display device according to a second embodiment will be described with reference to
As can be seen by comparing
Next, the operation of the pixel circuit 16 shown in
As can be seen by comparing
After that, as in the first embodiment above (see
As described above, also in the present embodiment, as in the first embodiment, when the corresponding first scanning signal PS(i) changes from the L level to the H level to turn off the write control transistor T3, the gate voltage Vg of the drive transistor 14 increases by the voltage ΔVc corresponding to the capacitance value of the compensation capacitor Cscg. This voltage increase ΔVc can compensate for the pull-in voltage ΔVf generated when the corresponding second scanning signal NS(i) changes from H level to L level after the data write period t5 to t6. Therefore, in the present embodiment, as in the first embodiment, it is possible to prevent the defect of not reducing the luminance of the organic EL element OL to a sufficiently low value when black is to be displayed, i.e., a black display defect.
When implementing the pixel circuit 16 (
The present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the present invention.
For example, in each of the above embodiments, among the transistors in the pixel circuit 15 or 16, the P-type transistors are LTPS-TFTs and the N-type transistors are IGZO-TFTs, but the present invention is not limited to these. The present invention can be applied to any internal compensation type display device using a hybrid pixel circuit in which a P-type transistor and an N-type transistor are mixed. For example, an N-type LIPS-TFT may be used in the pixel circuit. However, in such a hybrid pixel circuit, in order to compensate for a decrease in the gate voltage Vg of the drive transistor due to the change in the control signal of the threshold compensation transistor T2 (corresponding second scanning signal NS(i) in the above pixel circuits 15, 16) for the purpose of preventing black display defects, it is a prerequisite that the conductivity types of the write control transistor T3 and the threshold compensation transistor T2 are different from each other in the pixel circuit.
As described above, in each of the above-described embodiments, the corresponding second scanning signal NS(i) is supplied to the gate terminal of the threshold compensation transistor T2, the corresponding first scanning signal PS(i) is supplied to the gate terminal of the write control transistor T3, and there is formed a compensation capacitance Cscg between the node N1 including the gate terminal of drive transistor T4 and the corresponding first scanning signal line PSi so that the decrease (pull-in voltage) ΔVf in the gate voltage Vg of the drive transistor 14 accompanying the change from H level to L level in the corresponding second scanning signal NS(i) is compensated for by the increase (compensation voltage) ΔVc in the gate voltage Vg accompanying the change from L level to H level in the corresponding first scanning signal PS(i). On the other hand, if there is used a signal other than the corresponding second scanning signal NS(i) that changes from H level to L level after the data writing period t5 to t6, that signal may cause a black display defect. Thus, if there is used a signal other than the corresponding second scanning signal NS(i) that may cause a black display defect, the above compensation capacitance Cscg should be formed so that the decrease in gate voltage Vg due to the change from H level to L level in that signal is also compensated for.
In the pixel circuit Pix(i,j) in the first embodiment, i.e., the pixel circuit 15, the preceding second scanning signal NSi−2 is connected to the gate terminal of the first initialization transistor T1 (see
While the embodiments have been described above taking as an example the organic EL display device, the present invention is not limited to the organic EL display device and can be applied to any internal compensation type display device using a hybrid pixel circuit as described above in which a current-driven display element is used. Examples of the display elements that can be used are organic EL elements, such as organic light-emitting diodes (OLEDs), inorganic light-emitting diodes, and quantum-dot light-emitting diodes (QLEDs).
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2021/003545 | 2/1/2021 | WO |
