Patent Application
20220328005
The present invention relates to a pixel circuit having an organic electroluminescence (EL) element or other electro-optic element with a luminance controlled by a current value and an image display device comprised of such pixel circuits arrayed in a matrix, in particular a so-called active matrix type image display device controlled in value of current flowing through the electro-optic elements by insulating gate type field effect transistors (FETs) provided inside the pixel circuits.
In an image display device, for example, a liquid crystal display, a large number of pixels are arranged in a matrix and the light intensity is controlled for every pixel in accordance with the image information to be displayed so as to display an image. This same is true for an organic EL display etc. An organic EL display is a so-called self light emitting type display having a light emitting element in each pixel circuit and has the advantages that the viewability of the image is higher in comparison with a liquid crystal display, a backlight is unnecessary, the response speed is high, etc. Further, it greatly differs from a liquid crystal display etc. in the point that the gradations of the color generation are obtained by controlling the luminance of each light emitting element by the value of the current flowing through it, that is, each light emitting element is a current controlled type.
An organic EL display, in the same way as a liquid crystal display, may be driven by a simple matrix and an active matrix system, but while the former has a simple structure, it has the problem that realization of a large sized and high definition display is difficult. For this reason, much effort is being devoted to development of the active matrix system of controlling the current flowing through the light emitting element inside each pixel circuit by an active element provided inside the pixel circuit, generally, a thin film transistor (TFT).
The pixel circuit 2a of
When the scanning line WSL is made a selected state (low level here) and a write potential Vdata is supplied to the data line DTL, the TFT 12 becomes conductive, the capacitor C11 is charged or discharged, and the gate potential of the TFT 11 becomes Vdata.
Step ST2
When the scanning line WSL is made a non-selected state (high level here), the data line DTL and the TFT 11 are electrically separated, but the gate potential of the TFT 11 is held stably by the capacitor C11.
The current flowing through the TFT 11 and the light emitting element 13 becomes a value in accordance with a gate-source voltage Vgs of the TFT 11, while the light emitting element 13 is continuously emitting light with a luminance in accordance with the current value. As in the above step ST1, the operation of selecting the scanning line WSL and transmitting the luminance information given to the data line to the inside of a pixel will be referred to as “writing” below. As explained above, in the pixel circuit 2a of
As explained above, in the pixel circuit 2a, by changing a gate application voltage of the drive transistor constituted by the TFT 11, the value of the current flowing through the EL light emitting element 13 is controlled. At this time, the source of the p-channel drive transistor is connected to the power supply potential Vcc, so this TFT 11 is always operating in a saturated region. Accordingly, it becomes a constant current source having a value shown in the following equation 1.
Ids=1/2·μ(W/L)Cox(Vgs−|Vth|)2 (1)
Here, μ indicates the mobility of a carrier, Cox indicates a gate capacitance per unit area, W indicates a gate width, L indicates a gate length, Vgs indicates the gate-source voltage of the TFT 11, and Vth indicates the threshold value of the TFT 11.
In a simple matrix type image display device, each light emitting element emits light only at a selected instant, while in an active matrix, as explained above, each light emitting element continues emitting light even after the end of the write operation. Therefore, it becomes advantageous in especially a large sized and high definition display in the point that the peak luminance and peak current of each light emitting element can be lowered in comparison with a simple matrix.
In general, the I-V characteristic of an organic EL emitting element ends up deteriorating along with time as shown in
The pixel circuit 2a of
Next, consider a pixel device replacing the transistors with n-channel TFTs.
The pixel circuit 2b of
In the pixel circuit 2b, the drain side of the TFT 21 serving as the drive transistor is connected to the power source potential Vcc, and the source is connected to the anode of the organic EL emitting element 23, whereby a source-follower circuit is formed.
As shown in
Summarizing the problems to be solved by the invention, here too, the I-V characteristic of the organic EL emitting element ends up deteriorating along with time. As shown in
Further, as shown in
With this system, in the same way as when driven by the p-channel TFT of
With this system, however, the drive transistor has to be connected to the cathode side of the organic EL diode. This cathodic connection requires development of new anode-cathode electrodes. This is considered extremely difficult with the current level of technology.
Therefore, as shown in
EL emitting element while using current anode-cathode electrodes. Further, it is possible to configure transistors of a pixel circuit by only n-channel transistors and possible to use the a-Si process in the fabrication of the TFTs. Due to this, there is the advantage that a reduction of the cost of TFT substrates becomes possible.
In the display device shown in
As shown by the pixel circuit of
However, this method of the related art had problems. Each Vss line had (number of pixels in the X-direction×RGB) number of pixels connected to it. Therefore, when the TFT 43 of
A first object of the present invention is to provide a pixel circuit able to prevent a spread of the terminal voltages of drive transistors inside a panel and in turn able to reliably prevent deterioration of uniformity and a display device for the same.
A second object of the present invention is to provide a pixel circuit able to reliably prevent deterioration of the uniformity, enabling source-follower output with no deterioration of luminance even with a change of the current-voltage characteristic of the light emitting element along with time, enabling a source-follower circuit of n-channel transistors, and able to use an n-channel transistor as an EL drive transistor while using current anode-cathode electrodes and a display device for the same.
To attain the above object, according to a first aspect of the present invention, there is provided a pixel circuit for driving an electro-optic element with a luminance changing according to a flowing current, comprising a drive transistor forming a current supply line between a first terminal and a second terminal and controlling a current flowing through the current supply line in accordance with the potential of a control terminal; a first node; a power source voltage source; a reference power source interconnect; and a first circuit for connecting the first node to the reference power source interconnect for making a potential of the first node change to a fixed potential while the electro-optic element is not emitting light; the current supply line of the drive transistor, the first node, and the electro-optic element being connected in series between the power source voltage source and reference potential; the power source voltage source interconnect and the reference power source interconnect being laid out in the same direction so as not to have intersecting parts.
Preferably, the circuit further comprises a data line through which a data signal in accordance with luminance information is supplied; a second node; a first control line; a pixel capacitance element connected between the first node and the second node; and a first switch between the data line and the second node and controlled in conduction by the first control line.
More preferably, the circuit further comprises a second control line; the drive transistor is a field effect transistor with a source connected to the first node, a drain connected to the power source voltage source interconnect or reference potential, and a gate connected to the second node;
and the first circuit includes a second switch connected between the first node and fixed potential and controlled in conduction by the second control line.
Still more preferably, when the electro-optic element is driven, as a first stage, the first switch is held in a non-conductive state by the first control line and, in that state, the second switch is held in a conductive state and the first node is connected to a fixed potential by the second control line; as a second stage, the first switch is held in a conductive state by the first control line, data to be propagated over the data line is written in the pixel capacitance element, then the first switch is held in a non-conductive state; and as a third stage, the second switch is held in a non-conductive state by the second control line.
Alternatively, preferably, the circuit further comprises a second and third control line; the drive transistor is a field effect transistor with a drain connected to the power source voltage source or reference potential and a gate connected to the second node; and the first circuit includes a second switch connected between a source of the field effect transistor and the electro-optic element and controlled in conduction by the second control line and a third switch connected between the first node and the reference power source interconnect and controlled in conduction by the third control line.
More preferably, when the electro-optic element is driven, as a first stage, the first switch is held in a non-conductive state by the first control line, the second switch is held in a non-conductive state by the second control line, and the third switch is held in a non-conductive state by the third control line; as a second stage, the first switch is held in a conductive state by the first control line, the third switch is held in a conductive state by the third control line, the first node is held at a predetermined potential, and, in that state, data to be propagated over the data line is written in the pixel capacitance element, then the first switch is held in a non-conductive state by the first control line; and as a third stage, the third switch is held in a non-conductive state by the third control line and the second switch is held in a conductive state by the second control line.
According to a second aspect of the invention, there is provided a display device comprising a plurality of pixel circuits arranged in a matrix; power source voltage source interconnects arranged for the matrix array of pixel circuits; reference power source interconnects arranged for the matrix array of pixel circuits; and a reference potential; each pixel circuit including an electro-optic element with a luminance changing according to a flowing current, a drive transistor forming a current supply line between a first terminal and a second terminal and controlling a current flowing through the current supply line in accordance with the potential of a control terminal, a first node, and a first circuit for connecting the first node to the corresponding reference power source interconnect for making a potential of the first node change to a fixed potential while the electro-optic element is not emitting light, the current supply line of the drive transistor, the first node, and the electro-optic element being connected in series between the power source voltage source and reference potential, and the power source voltage source interconnect and the reference power source interconnect being laid out in the same direction so as not to have intersecting parts.
Preferably, the display device further comprises a data line arranged for each column of the matrix array of pixel circuits and through which a data signal in accordance with luminance information is supplied and a first control line arranged for each row of the matrix array of pixel circuits; each pixel circuit further having a second node, a pixel capacitance element connected between the first node and the second node and a first switch connected between the corresponding data line and the second node and controlled in conduction by the corresponding first control line.
More preferably, the device further comprises second control lines; each drive transistor is a field effect transistor with a source connected to the first node, a drain connected to the corresponding power source voltage source interconnect or reference potential, and a gate connected to the second node; and the first circuit includes a second switch connected between the first node and fixed potential and controlled in conduction by the corresponding second control line.
Still more preferably, when an electro-optic element is driven, as a first stage, the first switch is held in a non-conductive state by the corresponding first control line and, in that state, the second switch is held in a conductive state and the first node is connected to a fixed potential by the corresponding second control line; as a second stage, the first switch is held in a conductive state by the corresponding first control line, data to be propagated over the data line is written in the pixel capacitance element, then the first switch is held in a non-conductive state; and as a third stage, the second switch is held in a non-conductive state by the corresponding second control line.
Alternatively, preferably the device further comprises second and third control lines; each drive transistor is a field effect transistor with a drain connected to the power source voltage source interconnect or reference potential and a gate connected to the second node; and the first circuit includes a second switch connected between a source of the field effect transistor and the electro-optic element and controlled in conduction by the corresponding second control line and a third switch connected between the first node and the reference power source interconnect and controlled in conduction by the corresponding third control line.
More preferably, when an electro-optic element is driven, as a first stage, the first switch is held in a non-conductive state by the corresponding first control line, the second switch is held in a non-conductive state by the corresponding second control line, and the third switch is held in a non-conductive state by the corresponding third control line; as a second stage, the first switch is held in a conductive state by the corresponding first control line, the third switch is held in a conductive state by the corresponding third control line, the first node is held at a predetermined potential, and, in that state, data to be propagated over the data line is written in the pixel capacitance element, then the first switch is held in a non-conductive state by the corresponding first control line; and as a third stage, the third switch is held in a non-conductive state by the corresponding third control line and the second switch is held in a conductive state by the corresponding second control line.
According to the present invention, since the power source voltage source interconnects and the reference power source interconnects are laid out in the same direction so as not to have any intersecting parts, it is possible to prevent overlap between the power source voltage source interconnects and the reference power source interconnects. Accordingly, it is possible to lay out the reference power source interconnects (Vss interconnects) by a lower resistance than the past. Further, the number of pixels connected to a single interconnect is smaller in the vertical direction (y-direction) than the horizontal direction (x-direction) at a general angle of view, so with the same line width, it is possible to lay out the reference power source interconnects by a lower resistance than the past.
According to the present invention, further, since the source electrode of a drive transistor is connected to a fixed potential through a switch and there is a pixel capacity between the gate and source of the drive transistor, the change in luminance due to the change in the I-V characteristic of a light emitting element along with time is corrected. When the drive transistor is an n-channel transistor, by making the fixed potential a ground potential, the potential applied to the light emitting element is made the ground potential so as to create a non-emitting period of the light emitting element. Further, by adjusting the off period of the second switch connecting the source electrode and ground potential, the emitting and non-emitting periods of the light emitting element are adjusted for duty driving. Further, by making the fixed potential close to the ground potential or a potential lower than that or by raising the gate voltage, deterioration of the image quality due to fluctuation in the threshold voltage Vth of the switch transistor connected to the fixed potential is suppressed. Further, when the drive transistor is a p-channel transistor, by making the fixed potential the potential of the power source connected to the cathode electrode of the light emitting element, the potential applied to the light emitting element is made the power source potential so as to create a non-emitting period of the organic EL element. Further, by making the characteristic of the drive transistor an n-channel type, a source-follower circuit becomes and anodic connection becomes possible. Further, making all of the drive transistors n-channel transistors becomes possible, introduction of a general amorphous silicon process becomes possible, and reduction of the cost becomes possible.
Further, since the second switch is laid out between the light emitting element and the drive transistor, current is not supplied to the drive transistor in the non-emitting period and therefore power consumption of the panel is suppressed. Further, by using a potential of the cathode side of the light emitting element as the ground potential, for example, the second reference potential, there is no need to provide a GND interconnect at the TFT side inside the panel. Further, by being able to delete the GND interconnects of the TFT substrates in the panel, layout in the pixels and layout of the peripheral circuits become easy. Further, by being able to delete the GND interconnects of the TFT substrates in the panel, there is no overlap between the power source potential (first reference potential) and ground potential (second reference potential) of the peripheral circuits, the Vcc lines can be laid out with a lower resistance, and a high uniformity can be achieved.
Further, by turning the third switch at the power source interconnect side on when writing in a signal line so as to lower the impedance, the coupling effect on pixel writing is corrected in a short time and an image of a high uniformity is obtained.
These and other objects and features of the present invention will become clearer from the following description of the preferred embodiments given with reference to the accompanying drawings, in which:
Below, preferred embodiments of the present invention will be described with reference to the accompanying drawings.
Note that while the pixel circuits 101 are arranged in an m×n matrix in the pixel array portion 102,
The pixel circuit 101 according to the first embodiment has, as shown in
In the pixel circuit 101, a light emitting element (OLED) 114 is connected between the source of the TFT 111 and the reference potential (in this present embodiment, the ground potential GND). Specifically, the anode of the light emitting diode 114 is connected to the source of the TFT 111, while the cathode side is connected to the ground potential GND. The connection point of the anode of the light emitting element 114 and the source of the TFT 111 constitutes a node ND111. The source of the TFT 111 is connected to the drain of the TFT 113 and a first electrode of the capacitor C111, while the gate of the TFT 111 is connected to a node ND112. The source of the TFT 113 is connected to a fixed potential (in the present embodiment, a reference power source interconnect Vss line VSL101 set to the ground potential GND), while the gate of the TFT 113 is connected to the drive line DSL101. Further, a second electrode of the capacitor C111 is connected to the node ND112. The data line DTL101 and node ND112 are connected to a source and drain of the TFT 112 serving as the first switch. Further, the gate of the TFT 112 is connected to the scanning line WSL101.
In this way, the pixel circuit 101 according to the present embodiment is configured with a capacitor C111 connected between the gate and source of the TFT 111 serving as the drive transistor and with a source potential of the TFT 111 connected to a fixed potential through the TFT 113 serving as the switch transistor.
In the present embodiment, as shown in
Next, the operation of the above configuration will be explained focusing on the operation of a pixel circuit with reference to
First, at the time of the emitting state of an ordinary EL light emitting element 114, as shown in
Next, in the non-emitting period of the EL light emitting element 114, as shown in
Next, in the non-emitting period of the EL light emitting element 114, as shown in
After this, in the non-emitting period of the EL light emitting element 114, as shown in
After this, as shown in
The source potential Vs of the TFT 111 fluctuates, but despite this, since there is a capacity between the gate and source of the TFT 111, as shown in
Here, consider the problems in the source-follower system of the related art in the circuit of the present invention. In this circuit as well, the EL light emitting element deteriorates in its I-V characteristic along with the increase in the emitting period. Therefore, even if the drive transistor sends the same current, the potential applied to the EL light emitting diode changes and the potential of the node ND111 falls. However, in this circuit, the potential of the node ND111 falls while the gate-source potential of the drive transistor is held constant, so the current flowing through the drive transistor (TFT 111) does not change. Accordingly, the current flowing through the EL light emitting element also does not change. Even if the I-V characteristic of the EL light emitting element deteriorates, a current corresponding to the input voltage Vin constantly flows. Therefore, the problem of the related art can be solved.
As explained above, according to the present embodiment, the source of each TFT 111 serving as a drive transistor is connected to the anode of the light emitting element 114, the drain is connected to the power source potential Vcc, a capacitor C111 is connected between the gate and source of the TFT 111, and the source potential of the TFT 111 is connected to a fixed potential through the TFT 113 serving as the switch transistor and, further, the pixel circuit Vss lines VSL101 to VSL10n are connected by the Vss line VSLU and Vss line VSLB and arranged in parallel to the pixel circuit power source voltage Vcc lines VCL101 to VCL10n, so the following effects can be obtained.
Since the Vss interconnects are laid out in the y-direction (vertical direction), the TFTs 113 of the pixel circuits connected to the Vss lines VSL101 to VSL10n turn on at a single timing for 1H. Therefore, the fluctuation entering the interconnects becomes smaller and the uniformity is improved.
In addition, as explained above, the Vcc interconnects of the pixel array portion 102 are generally laid out in parallel in the y-direction with respect to the panel. Accordingly, in this embodiment, in the interconnects at the valid pixel portion, it is possible to lay out the Vss interconnects and the Vcc interconnects in parallel and possible to prevent overlap of the Vss interconnects and Vcc interconnects. Therefore, it is possible to lay out the Vss interconnects with less resistance than the past. In addition, the number of pixels connected to a single interconnect is smaller in the vertical direction (y-direction) than the horizontal direction (x-direction) in a general angle of view, so with the same line width, it is possible to lay out the Vss interconnects by a lower resistance than the past. Further, source-follower output with no deterioration in luminance even with a change in the I-V characteristic of an EL light emitting element along with time becomes possible. Further, a source-follower circuit of n-channel transistors becomes possible, so it is possible to use an n-channel transistor as a drive element of an EL light emitting element while using current anode-cathode electrodes. Further, it is possible to configure transistors of a pixel circuit by only n-channel transistors and possible to use the a-Si process in the fabrication of the TFTs. Due to this, there is the advantage that a reduction of the cost of TFT substrates becomes possible.
The display device 200, as shown in
Note that while the pixel circuits 201 are arranged in an m×n matrix in the pixel array portion 202,
In the second embodiment as well, like in the first embodiment, as shown in
Each pixel circuit 201 according to the second embodiment has, as shown in
In each pixel circuit 201, the source and drain of the TFT 213 are connected between the source of the TFT 211 and the anode of the light emitting element 215, the drain of the TFT 211 is connected to the power source potential Vcc, and the cathode of the light emitting element 215 is connected to the ground potential GND. That is, the TFT 211 serving as the drive transistor, the TFT 213 serving as the switch transistor, and the light emitting element 215 are connected in series between the power source potential Vcc and the ground potential GND. Further, the connection point of the source of the TFT 213 and the anode of the light emitting element 215 constitutes a node ND211. The gate of the TFT 211 is connected to the node ND212. Further, a capacitor C211 serving as the pixel capacity Cs is connected between the nodes ND211 and ND212, that is, between the gate and source of the TFT 211. The first electrode of the capacitor C211 is connected to the node ND211, while the second electrode is connected to the node ND212. The gate of the TFT 213 is connected to the drive line DSL201. Further, the source and drain of the TFT 212 serving as the first switch are connected to the data line DTL201 and the node ND212. Further, the gate of the TFT 212 is connected to the scanning line WSL201. Further, the source and drain of the TFT 214 are connected between the source (node ND211) of the TFT 213 and the Vss line VSL201, while the gate of the TFT 214 is connected to the scanning line WSL211.
In this way, the pixel circuit 201 according to the present embodiment is configured with the source of the TFT 211 serving as the drive transistor and the anode of the light emitting element 215 connected by the TFT 213 serving as the switching transistor, with a capacitor C211 connected between the gate and source of the TFT 211, and with a source potential of the TFT 213 connected to the reference power source interconnect constituted by the Vss line VSL201 (fixed voltage line) through the TFT 214.
Next, the operation of the above configuration will be explained focusing on the operation of a pixel circuit with reference to
First, at the ordinary emitting state of an EL light emitting element 215, as shown in
Next, in the non-emitting period of an EL light emitting element 215, as shown in
Next, in the non-emitting period of an EL light emitting element 215, as shown in
After this, in the non-emitting period of the EL light emitting element 215, as shown in
After this, as shown in
At this time, the TFT 211 serving as the drive transistor drives in the saturated region, so the current Ids flowing through the TFT 211 becomes the value shown in the above equation 1. This is the gate-source voltage Vgs of the drive transistor and is (Vin-Vo). That is, the current flowing through the TFT 211 can be said to be determined by the Vin.
In this way, by turning the TFT 214 on during a signal write period to make the source of the TFT 211 low in impedance, it is possible to make the source side of the TFT 211 of the pixel capacitor a fixed potential (Vss) at all times, there is no need to consider deterioration of image quality due to coupling at the time of a signal line write operation, and it is possible to write the signal line voltage in a short time. Further, it is possible to increase the pixel capacity to take measures against a leak characteristic.
Due to the above, even if the EL light emitting element 215 changes in its I-V characteristic along with the increase in the emitting period, in the pixel circuit 201 of the second embodiment, the potential of the node ND211 falls while the potential between the gate and source of the TFT 211 serving as the drive transistor is held constant, so the current flowing through the TFT 211 does not change. Accordingly, the current flowing through the EL light emitting element 215 also does not change. Even if the I-V characteristic of the EL light emitting element 215 deteriorates, the current corresponding to the input voltage Vin constantly flows. Source-follower output with no deterioration of the luminance becomes possible even if the I-V characteristic of the EL light emitting element changes along with time. In addition, since there is no transistor other than the pixel capacitor Cs between the gate and source of the TFT 211, the gate-source voltage Vgs of the TFT 211 serving as the drive transistor will not change due to fluctuations in the threshold voltage Vth like in the conventional system.
Further, in
The transistors of the pixel circuits need not be re-channel transistors. p-channel TFTs may also be used to form each pixel circuit. In this case, the power source is connected to the anode side of the EL light emitting element, while the TFT 211 serving as the drive transistor is connected to the cathode side.
Further, the TFT 212, TFT 213, and TFT 214 serving as the switching transistors may also be transistors of different polarities from the TFT 211 serving as the drive transistor.
According to the second embodiment, since the Vss interconnects are laid out in the y-direction, the TFTs 213 of the pixel circuits connected to the Vss lines VSL201 to VSL20n turn on at a single timing with respect to 1H. Accordingly, there is little fluctuation entering the interconnects and the uniformity can be improved. In addition, as explained above, the Vcc interconnects of the pixel array portion 202 are in general laid out in parallel to the y-direction with respect to the panel. Therefore, according to the present embodiment, in the interconnects at the valid pixel parts, the Vss interconnects and Vcc interconnects can be laid out in parallel and overlap between the Vss interconnects and Vcc interconnects can be prevented. For this reason, the Vss interconnects can be laid out with a lower resistance than the past. Further, the number of pixels connected to a single interconnect is smaller in the vertical direction (y-direction) than the horizontal direction (x-direction) in a general angle of view, so if the line width is the same, it is possible to lay out Vss interconnects with a lower resistance than the past. Further, source-follower output with no deterioration in luminance even with a change in the I-V characteristic of the organic EL emitting element along with time becomes possible. A source-follower circuit of n-channel transistors becomes possible, so it is possible to use an re-channel transistor as a drive element of an organic EL emitting element while using current anode-cathode electrodes. Further, it is possible to configure transistors of a pixel circuit by only n-channel transistors and possible to use the a-Si process in the fabrication of the TFTs. Due to this, there is the advantage that a reduction of the cost of TFT substrates becomes possible. In addition, according to the second embodiment, it is possible to write a signal line voltage in a short time even for example with a black signal and therefore possible to obtain an image quality of a high uniformity. Simultaneously, it is possible to increase the signal line capacity and suppress a leak characteristic.
Summarizing the effects of the invention, as explained above, according to the present invention, the pixel circuits connected to the reference power source interconnects turn on at a single timing during the signal sampling period. Therefore, there is little fluctuation entering the interconnects and the uniformity can be improved. In addition, it is possible to prevent overlap between the reference power source interconnects and the power source voltage source interconnects. Therefore, it is possible to lay out the reference power source interconnects by a lower resistance than the past. In addition, the number of pixels connected to a single interconnect is smaller in the vertical direction (y-direction) than the horizontal direction (x-direction) in a general angle of view, so with the same line width, it is possible to lay out the reference power source interconnects by a lower resistance than the past.
Further, according to the present invention, source-follower output with no deterioration in luminance even with a change in the I-V characteristic of the organic EL emitting element along with time becomes possible. Further, a source-follower circuit of n-channel transistors becomes possible, so it is possible to use an n-channel transistor as a drive element of an organic EL emitting element while using current anode-cathode electrodes. Further, it is possible to configure transistors of a pixel circuit by only n-channel transistors and possible to use the a-Si process in the fabrication of the TFTs. Due to this, there is the advantage that a reduction of the cost of TFT substrates becomes possible.
While the invention has been described with reference to specific embodiments chosen for purpose of illustration, it should be apparent that numerous modifications could be made thereto by those skilled in the art without departing from the basic concept and scope of the invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2003-158423 | Jun 2003 | JP | national |
This application is a continuation of and claims the benefit of priority from U.S. patent application Ser. No. 16/233,942, filed on Dec. 27, 2018, which is a continuation of U.S. patent application Ser. No. 15/888,530, filed Feb. 5, 2018 (now U.S. Pat. No. 10,170,041, issued Jan. 1, 2019), which is continuation of U.S. patent application Ser. No. 15/391,248, filed Dec. 27, 2016 (now U.S. Pat. No. 9,911,383, issued Mar. 6, 2018); which is a continuation of U.S. patent application Ser. No. 14/789,611, filed Jul. 1, 2015 (now U.S. Pat. No. 9,570,007, issued Feb. 14, 2017); which is a continuation of U.S. patent Ser. No. 14/571,966, filed on December 16, 2014 (now U.S. Pat. No. 9,147,358, issued Sep. 29, 2015); which is a continuation of U.S. patent application Ser. No. 14/446,103, filed on Jul. 29, 2014 (now U.S. Pat. No. 9,076,384, issued Jul. 7, 2015); which is a continuation of U.S. patent application Ser. No. 13/412,655, filed on Mar. 6, 2012 (now U.S. Pat. No. 8,836,678, issued Sep. 16, 2014); which is a divisional of U.S. patent application Ser. No. 11/777,781, filed on Jul. 13, 2007 (now U.S. Pat. No. 8,159,479, issued Apr. 17, 2012); which is a divisional of U.S. patent application Ser. No. 10/857,857, filed on Jun. 2, 2004 (now U.S. Pat. No. 7,382,342, issued Jun. 3, 2008). This application is also based upon and claims the benefit of priority under 35 U.S.C. § 119 from Japanese Patent Application No. 2003-158423 filed Jun. 3, 2003. The entire contents of each of these applications are incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 11777781 | Jul 2007 | US |
| Child | 13412655 | US | |
| Parent | 10857857 | Jun 2004 | US |
| Child | 11777781 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 16233942 | Dec 2018 | US |
| Child | 17852941 | US | |
| Parent | 15888530 | Feb 2018 | US |
| Child | 16233942 | US | |
| Parent | 15391248 | Dec 2016 | US |
| Child | 15888530 | US | |
| Parent | 14789611 | Jul 2015 | US |
| Child | 15391248 | US | |
| Parent | 14571966 | Dec 2014 | US |
| Child | 14789611 | US | |
| Parent | 14446103 | Jul 2014 | US |
| Child | 14571966 | US | |
| Parent | 13412655 | Mar 2012 | US |
| Child | 14446103 | US |
