Patent Application
20250124862
The present disclosure relates to the field of display technologies, and in particular, to a pixel circuit and a method for driving the same, a display panel, and a display device.
A display panel generally includes a substrate and a plurality of pixels disposed on the substrate. Each pixel includes a pixel circuit and a light-emitting element. The pixel circuit is coupled to the light-emitting element and configured to drive the light-emitting element to emit light.
A pixel circuit and a method for driving the same, a display panel, and a display device are provided. The technical solutions are as follows.
In an aspect, a pixel circuit is provided. The pixel circuit includes:
In some embodiments, the reset circuit includes:
In some embodiments, the first reset sub-circuit includes: a first transistor; the second reset sub-circuit includes: a second transistor; and the third reset sub-circuit includes: a third transistor; wherein
In some embodiments, the potential adjustment circuit includes:
In some embodiments, the switching sub-circuit includes: a fourth transistor; the compensation sub-circuit includes: a fifth transistor; and the adjustment sub-circuit includes: a first capacitor and a second capacitor; wherein
In some embodiments, the light emission control circuit includes:
In some embodiments, the first light emission control sub-circuit includes: a sixth transistor; and the second light emission control sub-circuit includes: a seventh transistor; wherein
In some embodiments, the pixel circuit further includes:
In some embodiments, the anti-leakage circuit includes: an eighth transistor; wherein
In some embodiments, a material of a transistor controlling the connection or disconnection between the first initial power supply terminal and the second node in the reset circuit and a material of a transistor controlling the connection or disconnection between the fourth node and the second node in the potential adjustment circuit both include: a low temperature poly-silicon material; and a material of a transistor in the anti-leakage circuit includes: an oxide material.
In some embodiments, the data writing circuit includes: a ninth transistor; and the drive circuit includes: a tenth transistor; wherein
In another aspect, a method for driving a pixel circuit is provided. The method is applicable to the pixel circuit described in the above aspect. The method includes:
In some embodiments, the pixel circuit further includes: an anti-leakage circuit; and the method further includes: controlling the second node to be connected to a fifth node by the anti-leakage circuit based on the first compensation signal in the first stage to the third stage; wherein
In still another aspect, a display panel is provided. The display panel includes a substrate, and a plurality of pixels disposed on a side of the substrate; wherein
In still another aspect, a display device is provided. The display device includes: a signal supply circuit, and the display panel described in the above aspect; wherein
For clearer descriptions of the technical solutions in the embodiments of the present disclosure, the accompanying drawings required for describing the embodiments are described below. The accompanying drawings in the following description show merely some embodiments of the present disclosure, and those of ordinary skill in the art may still derive other drawings from these accompanying drawings without creative effort.
To make the objectives, technical solutions, and advantages of the present disclosure clearer, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.
It should be noted that the transistors used in all the embodiments of the present disclosure are thin film transistors or field-effect transistors or other devices having the same characteristics. The transistors used in the embodiments of the present disclosure are mainly switching transistors according to the functions in the circuit. Since a source and a drain of the switching transistor used here are symmetrical, the source and the drain are interchangeable. In the embodiments of the present disclosure, the source is referred to as a first electrode and the drain is referred to as a second electrode. According to the form in the drawings, an intermediate terminal of the transistor is a control electrode which may also be referred to as a gate, a signal input terminal is a source, and a signal output terminal is a drain. In addition, the switching transistors used in the embodiments of the present disclosure include any one of a P-type switching transistor and an N-type switching transistor. The P-type switching transistor is turned on when the gate is at a low level and is turned off when the gate is at a high level, and the N-type switching transistor is turned on when the gate is at a high level and turned off when the gate is at a low level. In addition, a plurality of signals in the embodiments of the present disclosure each correspond to a first potential and a second potential. The first potential and the second potential only represent that the signal has potentials with two different state quantities, but do not represent that the first potential or the second potential has a specific value in the whole text.
An organic light-emitting diode (OLED) display is one of the hot spots in the field of display research currently. Compared with a liquid crystal display (LCD), the OLED display has the advantages of low power consumption, low cost, self-luminescence, wide viewing angle, fast response speed and the like. A pixel circuit is generally used in an OLED display to drive the OLED to emit light. Moreover, with the development of display technology, the application of OLED display has gradually expanded from the fields such as watches, mobile phones, and tablets with medium and small size to the fields of personal computers (PCs) and monitors with big size. Large-size displays have the feature of a high per pixel inch (PPI), i.e., resolution. In addition, due to the big difference in the scenes where the large-size displays are used, the requirement for the refresh rate varies greatly. For example, in a text reading mode or a power saving mode, the required refresh rate is generally lower than 10 Hertz (Hz); in a web browsing mode, a video watching mod or the like, the required refresh rate is generally from 48 Hz to 60 Hz; and in a game scene, the required refresh rate needs to reach 120 Hz to 144 Hz, even to 240 Hz and higher. Therefore, the displays need to have a good display effect at the refresh rates of several Hz to several hundred Hz.
At present, the common pixel circuits have a 7T1C (i.e., including 7 transistors and 1 capacitors) structure, and data writing and compensation for the threshold voltage Vth are simultaneously completed by the same device in the pixel circuit. As a result, the Vth cannot be reliably compensated in a short time (e.g., a high frame rate). In addition, the influence of the non-uniformity of the characteristics of the driving transistor in the pixel circuit on the data writing is also amplified, resulting in a significant decrease in the display quality of the displays. Therefore, it is urgent to find other compensation methods to improve the accuracy of data writing and reliably compensate the Vth within a brief period, so as to improve the display quality of the displays.
In the related art, the pixel circuit generally includes a light emission control circuit and a light emission drive circuit. The light emission control circuit includes a plurality of control transistors, and the light emission drive circuit includes a driving transistor. The plurality of control transistors are coupled to a plurality of signal terminals (e.g., a gate signal terminal and a data terminal) respectively, and are further coupled to the gate of the driving transistor for controlling the potential of the gate of the driving transistor. A first electrode of the driving transistor is configured to receive a driving power supply signal, and a second electrode of the driving transistor is coupled to the light-emitting element to transmit a driving signal to the light-emitting element based on the potential of the gate and the driving power supply signal, so as to drive the light-emitting element to emit light.
However, due to factors such as processes and materials, the uniformity and stability of the semiconductor characteristics such as the threshold voltage or mobility of the driving transistor are poor. As a result, the driving signal for driving the light-emitting element to emit light cannot be generated reliably, and the display effect of the display panel is poor.
The embodiments of the present disclosure provide a new pixel circuit. The pixel circuit can drive the light-emitting element to emit light by means of data writing and Vth compensation which are separate from each other, and thus the compensation for Vth is no longer limited by the data writing time, and a better compensation effect can be achieved in a short time (e.g., a high resolution and high frame rate). In addition, in the pixel circuit provided in the embodiments of the present disclosure, the potential of the gate of the driving transistor can also be flexibly adjusted, and the driving transistor can be reset in an off state at a low frame rate, thereby ensuring a good display stability at the low frame rate.
The data writing circuit 01 is coupled to a gate signal terminal Sn, a data terminal Vdt, and a first node N1. The data writing circuit 01 is configured to control the connection or disconnection between the data terminal Vdt and the first node N1 based on a gate driving signal provided by the gate signal terminal Sn.
For example, when the potential of the gate driving signal provided by the gate signal terminal Sn is the first potential, the data writing circuit 01 controls the data terminal Vdt to be connected to the first node N1, so that the data signal provided by the data terminal Vdt is transmitted to the first node N1 to charge the first node N1. When the potential of the gate driving signal provided by the gate signal terminal Sn is the second potential, the data writing circuit 01 controls the data terminal Vdt to be disconnected from the first node N1.
Optionally, in the embodiments of the present disclosure, the first potential is an effective potential, the second potential is an ineffective potential, and the first potential is a low potential relative to the second potential. Certainly, in some other embodiments, the first potential is a high potential relative to the second potential.
The reset circuit 02 is coupled to a reset signal terminal Re, a scanning signal terminal Scan, a first reference power supply terminal Vref1, a first initial power supply terminal Vinit1, a second initial power supply terminal Vinit2, the first node N1, a second node N2, and a light-emitting element L1. The reset circuit 02 is configured to control the connection or disconnection between the first initial power supply terminal Vinit1 and the second node N2 based on a reset signal provided by the reset signal terminal Re, and control, based on a scanning signal provided by the scanning signal terminal Scan, the connection or disconnection between the first reference power supply terminal Vref1 and the first node N1 and the connection or disconnection between the second initial power supply terminal Vinit2 and the light-emitting element L1.
For example, when the potential of the reset signal provided by the reset signal terminal Re is the first potential, the reset circuit 02 controls the first initial power supply terminal Vinit1 to be connected to the second node N2, so that the first initial power supply signal provided by the first initial power supply terminal Vinit1 is transmitted to the second node N2 to reset the second node N2. When the potential of the reset signal provided by the reset signal terminal Re is the second potential, the reset circuit 02 controls the first initial power supply terminal Vinit1 to be disconnected from the second node N2.
Similarly, when the potential of the scanning signal provided by the scanning signal terminal Scan is the first potential, the reset circuit 02 controls the first reference power supply terminal Vref1 to be connected to the first node N1, so that the first reference power supply signal provided by the first reference power supply terminal Vref1 is transmitted to the first node N1 to reset the first node N1; and the reset circuit 02 controls the second initial power supply terminal Vinit2 to be connected to the light-emitting element L1, so that the second initial power supply signal provided by the second initial power supply terminal Vinit2 is transmitted to the light-emitting element L1 to reset the light-emitting element L1. When the potential of the scanning signal provided by the scanning signal terminal Scan is the second potential, the reset circuit 02 controls the first reference power supply terminal Vref1 to be disconnected from the first node N1 and controls the second initial power supply terminal Vinit2 to be disconnected from the light-emitting element L1.
The potential adjustment circuit 03 is coupled to a first compensation terminal AZ1, a second compensation terminal AZ2, a driving power supply terminal VDD, the first node N1, the second node N2, a third node N3, and a fourth node N4. The potential adjustment circuit 03 is configured to control the connection or disconnection between the driving power supply terminal VDD and the third node N3 based on a first compensation signal provided by the first compensation terminal AZ1, control the connection or disconnection between the second node N2 and the fourth node N4 based on a second compensation signal provided by the second compensation terminal AZ2, and adjust the potential of the first node N1, the potential of the second node N2, and the potential of the third node N3 through a coupling effect.
For example, when the potential of the first compensation signal provided by the first compensation terminal AZ1 is the first potential, the potential adjustment circuit 03 controls the driving power supply terminal VDD to be connected to the third node N3, so that the driving power supply signal provided by the driving power supply terminal VDD is transmitted to the third node N3 to charge the third node N3. When the potential of the first compensation signal provided by the first compensation terminal AZ1 is the second potential, the potential adjustment circuit 03 controls the driving power supply terminal VDD to be disconnected from the third node N3.
Similarly, when the potential of the second compensation signal provided by the second compensation terminal AZ2 is the first potential, the potential adjustment circuit 03 controls the second node N2 to be connected to the fourth node N4, so that the potential of the second node N2 and the potential of the fourth node N4 interact with each other, that is, the potential of one of the second node N2 and the fourth node N4 is adjusted based on the potential of the other one of the second node N2 and the fourth node N4. When the potential of the second compensation signal provided by the second compensation terminal AZ2 is the second potential, the potential adjustment circuit 03 controls the second node N2 to be disconnected from the fourth node N4.
The light emission control circuit 04 is coupled to a light emission control terminal EM, a second reference power supply terminal Vref2, the first node N1, the fourth node N4, and the light-emitting element L1. The light emission control circuit 04 is configured to control, based on a light emission control signal provided by the light emission control terminal EM, the connection or disconnection between the second reference power supply terminal Vref2 and the first node N1 and the connection or disconnection between the fourth node N4 and the light-emitting element L1.
For example, when the potential of the light emission control signal provided by the light emission control terminal EM is the first potential, the light emission control circuit 04 controls the second reference power supply terminal Vref2 to be connected to the first node N1, so that the potential of the second reference power supply signal provided by the second reference power supply terminal Vref2 is transmitted to the first node N1 to reset the first node N1; and the light emission control circuit 04 controls the fourth node N4 to be connected to the light-emitting element L1, so that the potential of the fourth node N4 is transmitted to the light-emitting element L1 to drive the light-emitting element L1 to emit light reliably. When the potential of the light emission control signal provided by the light emission control terminal EM is the second potential, the light emission control circuit 04 controls the second reference power supply terminal Vref2 to be disconnected from the first node N1 and controls the fourth node N4 to be disconnected from the light-emitting element L1.
The drive circuit 05 is coupled to the second node N2, the driving power supply terminal VDD, and the fourth node N4. The drive circuit 05 is configured to transmit a driving signal (e.g., a driving current) to the fourth node N4 based on the potential of the second node N2 and the driving power supply signal. When the light emission control circuit 04 controls the fourth node N4 to be connected to the light-emitting element L1, the driving signal transmitted to the fourth node N4 is further transmitted to the light-emitting element L1, thereby driving the light-emitting element L1 to emit light.
In some embodiments, as shown in
It can be known from the working principle of each circuit described above that, in the embodiments of the present disclosure, the data writing circuit 01 writes the data signal to the first node N1 based on the gate driving signal, the potential adjustment circuit 03 writes the driving power supply signal to the third node N3 based on the compensation signal to control the connection or disconnection between the second node N2 and the fourth node N4, and the potentials of the first node N1, the second node N2 and the third node N3 are adjusted through the coupling effect. In this way, the threshold voltage Vth of the driving transistor in the drive circuit 05 is reliably written to the second node N2, and thus the driving signal subsequently generated by the drive circuit 05 is irrelevant to the threshold voltage Vth, thereby compensating the threshold voltage Vth. It can be seen from
In addition, in the embodiments of the present disclosure, the potential of the second reference power supply signal provided by the second reference power supply terminal Vref2 is lower than the potential of the first reference power supply signal provided by the first reference power supply terminal Vref1.
For example, the potential Vref10 of the first reference power supply signal is about 5 volts (V) to 7V; and the potential Vref20 of the second reference power supply signal is about 2V to 4V.
It should be noted that during the display process, the light-emitting element L1 and the driving transistor included in the drive circuit 05 need to be reset at a higher frequency, so as to compensate for the luminance difference caused by aging of the device during the light-emitting process of the light-emitting element L1. The reset action also needs to be performed at the low frame rate. Correspondingly, the refresh of one frame of picture is generally divided into a refresh frame stage and a hold frame stage that are sequentially executed. In the refresh frame stage, the data signal is written, and compensation for the threshold voltage Vth, driving the light-emitting element L1 to emit light, and the like may also be performed; and in the hold frame stage, only the light-emitting element L1 and the driving transistor are reset.
In this way, on the basis of setting the potential Vref10 of the first reference power supply signal provided by the first reference power supply terminal Vref1 higher than the potential Vref20 of the second reference power supply signal provided by the second reference power supply terminal Vref2, in the hold frame stage, the potential of the light emission control signal provided by the light emission control terminal EM is set high (i.e., the potential of the light emission control signal is controlled to be the ineffective potential) and the potential of the scanning signal provided by the scanning signal terminal Scan is set low (i.e., the potential of the scanning signal is controlled to be the effective potential), such that the light emission control circuit 04 controls the fourth node N4 to be disconnected from the light-emitting element L1 and controls the second reference power supply terminal Vref2 to be disconnected from the first node N1, and the reset circuit 02 controls the first reference power supply terminal Vref1 to be connected to the first node N1 and controls the second initial power supply terminal Vinit2 to be connected to the light-emitting element L1. Thus, in the first reference power supply terminal Vref1 and the second reference power supply terminal Vref2, the first reference power supply terminal Vref1 providing a sufficiently high potential can transmit the first reference power supply signal Vref10 to the first node N1, and then the potential of the second node N2 is pulled up under the regulating effect of the potential adjustment circuit 03, thereby ensuring that the driving transistor can be reliably turned off, and the driving transistor is reset in an off state. In addition, the second initial power supply terminal Vinit2 can transmit the second initial power supply signal to the light-emitting element L1, to reliably reset the light-emitting element L1. This control method can ensure a good display stability of the light-emitting element at the low frame rate.
Then, when the light-emitting element L1 needs to emit light normally, the potential of the light emission control signal provided by the light emission control terminal EM is set low (i.e., the potential of the light emission control signal is controlled to be the effective potential) and the potential of the scanning signal provided by the scanning signal terminal Scan is set high (i.e., the potential of the scanning signal is controlled to be the ineffective potential), such that the light emission control circuit 04 controls the second reference power supply terminal Vref2 to be connected to the first node N1 and controls the fourth node N4 to be connected to the light-emitting element L1, and the reset circuit 02 controls the first reference power supply terminal Vref1 to be disconnected from the first node N1 and controls the second initial power supply terminal Vinit2 to be disconnected from the light-emitting element L1. Thus, in the first reference power supply terminal Vref1 and the second reference power supply terminal Vref2, the second reference power supply terminal Vref2 providing a lower potential can transmit the second reference power supply signal to the first node N1, that is, the potential of the first node N1 returns to the potential Vref20 of the second reference power supply signal. In addition, since only the potential of the first node N1 changes, according to the law of conservation of charge, the potential of the second node N2 can quickly return to the potential which enables normal light emission of the light-emitting element L1 under the control of the potential adjustment circuit 03, thereby ensuring that the drive circuit 05 reliably drives the light-emitting element L1 to emit light based on the potential of the second node N2.
In summary, the embodiments of the present disclosure provide a pixel circuit. In the pixel circuit, the data writing circuit controls the connection or disconnection between the data terminal and the first node based on the gate driving signal; the reset circuit controls, based on the reset signal and the scanning signal, the connection or disconnection between the initial power supply terminal and the second node and between the initial power supply terminal and the light-emitting element, and the connection or disconnection between the reference power supply terminal and the first node; the potential adjustment circuit controls, based on the compensation signal, the connection or disconnection between the driving power supply terminal and the third node and the connection or disconnection between the second node and the fourth node, and adjusts the potential of the first node, the potential of the second node and the potential of the third node through the coupling effect; the light emission control circuit controls, based on the light emission control signal, the connection or disconnection between the reference power supply terminal and the first node and the connection or disconnection between the fourth node and the light-emitting element; and the drive circuit transmits, based on the potential of the second node and the driving power supply signal, the driving signal to the fourth node to drive the light-emitting element to emit light. In this way, the signal provided by each signal terminal can be flexibly set to achieve a reliable compensation for the threshold voltage of the driving transistor in the drive circuit, thereby ensuring a good display effect.
Additionally, since data is directly written into the second node under the coupling effect of the potential adjustment circuit instead of being written into the second node through the drive circuit, data writing and compensation for the threshold voltage can be achieved through different paths by different circuits, and thus data writing and compensation for the threshold voltage can be separated from each other without affecting each other, which ensures the effective compensation for the threshold voltage, and further ensures a better display effect. Moreover, on the basis of flexibly setting the reference power supply signals provided by the first reference power supply terminal and the second reference power supply terminal, the reference power supply signal at a higher potential can be written into the gate of the driving transistor in the drive circuit in the hold frame, thereby ensuring that the driving transistor is reset reliably in an off state, and ensuring a good display stability, especially at the low frame rate.
The first reset sub-circuit 021 is coupled to the reset signal terminal Re, the first initial power supply terminal Vinit1, and the second node N2. The first reset sub-circuit 021 is configured to control the connection or disconnection between the first initial power supply terminal Vinit1 and the second node N2 based on the reset signal.
For example, the first reset sub-circuit 021 controls the first initial power supply terminal Vinit1 to be connected to the second node N2 when the potential of the reset signal is the first potential, and controls the first initial power supply terminal Vinit1 to be disconnected from the second node N2 when the potential of the reset signal is the second potential.
The second reset sub-circuit 022 is coupled to the scanning signal terminal Scan, the first reference power supply terminal Vref1, and the first node N1. The second reset sub-circuit 022 is configured to control the connection or disconnection between the first reference power supply terminal Vref1 and the first node N1 based on the scanning signal.
For example, the second reset sub-circuit 022 controls the first reference power supply terminal Vref1 to be connected to the first node N1 when the potential of the scanning signal is the first potential, and controls the first reference power supply terminal Vref1 to be disconnected from the first node N1 when the potential of the scanning signal is the second potential.
The third reset sub-circuit 023 is coupled to the scanning signal terminal Scan, the second initial power supply terminal Vinit2, and the light-emitting element L1. The third reset sub-circuit 023 is configured to control the connection or disconnection between the second initial power supply terminal Vinit2 and the light-emitting element L1 based on the scanning signal. Optionally, as described in the foregoing embodiments, the third reset sub-circuit 023 is coupled to the anode of the light-emitting element L1, and controls the connection or disconnection between the second initial power supply terminal Vinit2 and the anode of the light-emitting element L1.
For example, the third reset sub-circuit 023 controls the second initial power supply terminal Vinit2 to be connected to the light-emitting element L1 when the potential of the scanning signal is the first potential, and controls the second initial power supply terminal Vinit2 to be disconnected from the light-emitting element L1 when the potential of the scanning signal is the second potential.
The switching sub-circuit 031 is coupled to the first compensation terminal AZ1, the driving power supply terminal VDD, and the third node N3. The switching sub-circuit 031 is configured to control the connection or disconnection between the driving power supply terminal VDD and the third node N3 based on the first compensation signal.
For example, the switching sub-circuit 031 controls the driving power supply terminal VDD to be connected to the third node N3 when the potential of the first compensation signal is the first potential, and controls the driving power supply terminal VDD to be disconnected from the third node N3 when the potential of the first compensation signal is the second potential.
The compensation sub-circuit 032 is coupled to the second compensation terminal AZ2, the second node N2, and the fourth node N4. The compensation sub-circuit 032 is configured to control the connection or disconnection between the second node N2 and the fourth node N4 based on the second compensation signal.
For example, the compensation sub-circuit 032 controls the second node N2 to be connected to the fourth node N4 when the potential of the second compensation signal is the first potential, and controls the second node N2 to be disconnected from the fourth node N4 when the potential of the second compensation signal is the second potential.
The adjustment sub-circuit 033 is coupled to the first node N1, the second node N2, and the third node N3. The adjustment sub-circuit 033 is configured to adjust the potential of the first node N1, the potential of the second node N2, and the potential of the third node N3 through the coupling effect.
The first light emission control sub-circuit 041 is coupled to the light emission control terminal EM, the second reference power supply terminal Vref2, and the first node N1. The first light emission control sub-circuit 041 is configured to control the connection or disconnection between the second reference power supply terminal Vref2 and the first node N1 based on the light emission control signal.
For example, the first light emission control sub-circuit 041 controls the second reference power supply terminal Vref2 to be connected to the first node N1 when the potential of the light emission control signal is the first potential, and controls the second reference power supply terminal Vref2 to be disconnected from the first node N1 when the potential of the light emission control signal is the second potential.
The second light emission control sub-circuit 042 is coupled to the light emission control terminal EM, the fourth node N4, and the light-emitting element L1. The second light emission control sub-circuit 042 is configured to control the connection or disconnection between the fourth node N4 and the light-emitting element L1 based on the light emission control signal. Optionally, as described in the foregoing embodiments, the second light emission control sub-circuit 042 is coupled to the anode of the light-emitting element L1, and controls the connection or disconnection between the fourth node N4 and the anode of the light-emitting element L1.
For example, the second light emission control sub-circuit 042 controls the fourth node N4 to be connected to the light-emitting element L1 when the potential of the light emission control signal is the first potential, and controls the fourth node N4 to be disconnected from the light-emitting element L1 when the potential of the light emission control signal is the second potential.
The anti-leakage circuit 06 is coupled to the first compensation terminal AZ1, the second node N2, and a fifth node N5. The anti-leakage circuit 06 is configured to control the connection or disconnection between the second node N2 and the fifth node N5 based on the first compensation signal.
For example, the anti-leakage circuit 06 controls the second node N2 to be connected to the fifth node N5 when the potential of the first compensation signal is the first potential, and controls the second node N2 to be disconnected from the fifth node N5 when the potential of the first compensation signal is the second potential.
On this basis, with continued reference to
Additionally, the potential adjustment circuit 03 controls the fourth node N4 to be connected to the second node N2 when the potential of the second compensation signal is the first potential, and on this basis, when the anti-leakage circuit 06 controls the second node N2 to be connected to the fifth node N5, the fourth node N4 is indirectly connected to the fifth node N5. Similarly, when the anti-leakage circuit 06 controls the second node N2 to be connected to the fifth node N5, the first initial power supply terminal Vinit1 is indirectly connected to the fifth node N5. The potential adjustment circuit 03 controls the fourth node N4 to be disconnected from the fifth node N5 when the potential of the second compensation signal is the second potential. The potential adjustment circuit 03 adjusts the potential of the first node N1, the potential of the third node N3, and the potential of the fifth node N5.
Based on the above embodiments, it can be known that by providing the anti-leakage circuit 06, the drive circuit 05 is indirectly coupled with the second node N2, and the first initial power supply terminal Vinit1 and the fourth node N4 are indirectly connected to or disconnected from the fifth node N5 through the second node N2. In this way, the potential of the fifth node N5 (e.g., the gate of the driving transistor) is prevented from leakage, that is, the potential stability of the fifth node N5 is improved.
Taking the structure shown in
As can be seen from
A gate of the first transistor T1 is coupled to the reset signal terminal Re, a first electrode of the first transistor T1 is coupled to the first initial power supply terminal Vinit1, and a second electrode of the first transistor T1 is coupled to the second node N2.
Agate of the second transistor T2 is coupled to the scanning signal terminal Scan, a first electrode of the second transistor T2 is coupled to the first reference power supply terminal Vref1, and a second electrode of the second transistor T2 is coupled to the first node N1.
A gate of the third transistor T3 is coupled to the scanning signal terminal Scan, a first electrode of the third transistor T3 is coupled to the second initial power supply terminal Vinit2, and a second electrode of the third transistor T3 is coupled to the light-emitting element L1. Optionally, as described in the foregoing embodiments, the second electrode of the third transistor T3 is coupled to the anode of the light-emitting element L1.
In some embodiments, with continued reference to
A gate of the fourth transistor T4 is coupled to the first compensation terminal AZ1, a first electrode of the fourth transistor T4 is coupled to the driving power supply terminal VDD, and a second electrode of the fourth transistor T4 is coupled to the third node N3.
A gate of the fifth transistor T5 is coupled to the second compensation terminal AZ2, a first electrode of the fifth transistor T5 is coupled to the fourth node N4, and a second electrode of the fifth transistor T5 is coupled to the second node N2.
The first capacitor C1 is connected in series between the first node N1 and the third node N3. The first capacitor C1 is also referred to as a node potential storage capacitor Cst.
The second capacitor C2 is connected in series between the third node N3 and the second node N2. The second capacitor C2 is also referred to as a threshold voltage storage capacitor Cvth.
When the first reference power supply terminal Vref1 transmits the first reference power supply signal at a relatively high potential to the first node N1 through the second transistor T2, the potential of the third node N3 can be pulled up synchronously through the node potential storage capacitor Cst, and the potential of the gate of the driving transistor (i.e., a tenth transistor T10) can be pulled up through the threshold voltage storage capacitor Cvth, thereby ensuring that the driving transistor is reliably reset in an off state, and improving the display stability of the display panel at the low frame rate.
In some embodiments, with continued reference to
A gate of the sixth transistor T6 is coupled to the light emission control terminal EM, a first electrode of the sixth transistor T6 is coupled to the second reference power supply terminal Vref2, and a second electrode of the sixth transistor T6 is coupled to the first node N1.
A gate of the seventh transistor T7 is coupled to the light emission control terminal EM, a first electrode of the seventh transistor T7 is coupled to the fourth node N4, and a second electrode of the seventh transistor T7 is coupled to the light-emitting element L1. Optionally, as described in the foregoing embodiments, the second electrode of the seventh transistor T7 is coupled to the anode of the light-emitting element L1.
In some embodiments, with continued reference to
A gate of the ninth transistor T9 is coupled to the gate signal terminal Sn, a first electrode of the ninth transistor T9 is coupled to the data terminal Vdt, and a second electrode of the ninth transistor T9 is coupled to the first node N1.
A gate of the tenth transistor T10 is coupled to the second node N2, a first electrode of the tenth transistor T10 is coupled to the driving power supply terminal VDD, and a second electrode of the tenth transistor T10 is coupled to the fourth node N4.
In some embodiments, with continued reference to
A gate of the eighth transistor T8 is coupled to the first compensation terminal AZ1, a first electrode of the eighth transistor T8 is coupled to the fifth node N5, and a second electrode of the eighth transistor T8 is coupled to the second node N2.
As can be seen from a comparison of
Optionally, in the embodiments of the present disclosure, on the basis of providing the anti-leakage circuit 06, the material of the transistor (i.e., the first transistor T1) controlling the connection or disconnection between the first initial power supply terminal Vinit1 and the second node N2 in the reset circuit 02 and the material of the transistor controlling the connection or disconnection between the fourth node N4 and the second node N2 in the potential adjustment circuit 03 both include a low temperature poly-silicon (LTPS) material. The material of the transistor (i.e., the eighth transistor T8) in the anti-leakage circuit 06 includes an oxide material. In addition, similar to the eighth transistor T8, the material of the fourth transistor T4 coupled to the first compensation terminal AZ1 also includes an oxide material. It should be noted that the material of the transistor herein refers to the material of the active layer included in the transistor. It should be noted that a pixel circuit is considered as a circuit of the LTPO structure in the case that the pixel circuit includes both a transistor including the LTPS material and a transistor including the oxide material; and a pixel circuit is considered as a circuit of the LTPS structure in the case that the pixel circuit only includes the transistor including the LTPS material.
In some embodiments, with continued reference to
The N-type transistors made from the oxide material have better anti-leakage capability than the P-type transistors made from the LTPS material. Therefore, in combination with
In summary, the embodiments of the present disclosure provide a pixel circuit. In the pixel circuit, the data writing circuit controls the connection or disconnection between the data terminal and the first node based on the gate driving signal; the reset circuit controls, based on the reset signal and the scanning signal, the connection or disconnection between the initial power supply terminal and the second node and between the initial power supply terminal and the light-emitting element, and the connection or disconnection between the reference power supply terminal and the first node; the potential adjustment circuit controls, based on the compensation signal, the connection or disconnection between the driving power supply terminal and the third node and the connection or disconnection between the second node and the fourth node, and adjusts the potential of the first node, the potential of the second node and the potential of the third node through the coupling effect; the light emission control circuit controls, based on the light emission control signal, the connection or disconnection between the reference power supply terminal and the first node and the connection or disconnection between the fourth node and the light-emitting element; and the drive circuit transmits, based on the potential of the second node and the driving power supply signal, the driving signal to the fourth node to drive the light-emitting element to emit light. In this way, the signal provided by each signal terminal can be flexibly set to achieve a reliable compensation for the threshold voltage of the driving transistor in the drive circuit, thereby ensuring a good display effect.
Additionally, since data is directly written into the second node under the coupling effect of the potential adjustment circuit instead of being written into the second node through the drive circuit, data writing and compensation for the threshold voltage can be achieved through different paths by different circuits, and thus data writing and compensation for the threshold voltage can be separated from each other without affecting each other, which ensures the effective compensation for the threshold voltage, and further ensures a better display effect. Moreover, on the basis of flexibly setting the reference power supply signals provided by the first reference power supply terminal and the second reference power supply terminal, the reference power supply signal at a higher potential can be written into the gate of the driving transistor in the drive circuit in the hold frame, thereby ensuring that the driving transistor is reset reliably in an off state, and ensuring a good display stability, especially at the low frame rate.
In step 801, in a first stage, the reset circuit controls the first initial power supply terminal to be connected to the second node based on the reset signal provided by the reset signal terminal, controls the first reference power supply terminal to be connected to the first node and controls the second initial power supply terminal to be connected to the light-emitting element based on the scanning signal provided by the scanning signal terminal; and the potential adjustment circuit controls the driving power supply terminal to be connected to the third node based on the first compensation signal provided by the first compensation terminal.
In step 802, in a second stage, the reset circuit controls the first reference power supply terminal to be connected to the first node and controls the second initial power supply terminal to be connected to the light-emitting element based on the scanning signal; and the potential adjustment circuit controls the driving power supply terminal to be connected to the third node based on the first compensation signal and controls the second node to be connected to the fourth node based on the second compensation signal provided by the second compensation terminal.
In step 803, in a third stage, the data writing circuit controls the data terminal to be connected to the first node based on the gate driving signal provided by the gate signal terminal; and the potential adjustment circuit controls the driving power supply terminal to be connected to the third node based on the first compensation signal and controls the second node to be connected to the fourth node based on the second compensation signal.
In step 804, in a fourth stage, the light emission control circuit controls the second reference power supply terminal to be connected to the first node and controls the fourth node to be connected to the light-emitting element based on the light emission control signal provided by the light emission control terminal; and the drive circuit transmits a driving signal to the fourth node based on the potential of the second node and the driving power supply signal provided by the driving power supply terminal, to drive the light-emitting element to emit light.
In step 805, in a fifth stage, the reset circuit controls the first reference power supply terminal to be connected to the first node and controls the second initial power supply terminal to be connected to the light-emitting element based on the scanning signal.
The potential of the second reference power supply signal provided by the second reference power supply terminal is lower than the potential of the first reference power supply signal provided by the first reference power supply terminal. In addition, the first stage, the second stage, the third stage, the fourth stage and the fifth stage are sequentially executed. In each stage, the potential adjustment circuit adjusts the potential of the first node, the potential of the second node and the potential of the third node through the coupling effect.
It should be noted that the first stage to the fourth stage are the refresh frame stage described in the foregoing embodiments; and the fifth stage is the hold frame stage described in the foregoing embodiments.
In some embodiments, with continued reference to
In some embodiments, on the basis of the structure shown in
For the structures shown in
Further, in the structures shown in
For example, assuming that the potential of the first initial power supply signal is Vinit10, the potential of the second initial power supply signal is Vinit20, the potential of the first reference power supply signal is Vref10, and the potential of the driving power supply signal is Vdd, then in the first stage t1, the potential of the first node N1 is controlled to be Vref10, the potential of the second node N2 and the potential of the fifth node N5 are controlled to be Vinit10, the potential of the third node N3 is controlled to be Vdd, and the potential of the anode of the light-emitting element L1 is controlled to be Vinit20, thereby resetting the first node N1, the second node N2, the fifth node N5 and the anode of the light-emitting element L1. Thus, the tenth transistor T10 is turned on. That is, in the first stage t1, the potentials at two terminals of the first capacitor C1 are Vref10 and Vdd, and the potentials at two terminals of the second capacitor C2 are Vdd and Vinit10. The first stage t1 is also referred to as a reset stage.
For the structures shown in
Further, in the structures shown in
For example, still assuming that the potential of the first initial power supply signal is Vinit10, the potential of the second initial power supply signal is Vinit20, the potential of the first reference power supply signal is Vref10, and the potential of the driving power supply signal is Vdd, then in the second stage t2, the potential of the first node N1 is controlled to be Vref10, the potential of the second node N2 and the potential of the fifth node N5 are both controlled to be Vdd+Vth, the potential of the third node N3 is controlled to be Vdd, and the potential of the anode of the light-emitting element L1 is controlled to be Vinit20. That is, in the second stage t2, the potentials at two terminals of the first capacitor C1 are Vref10 and Vdd, and the potentials at two terminals of the second capacitor C2 are Vdd and Vdd+Vth. The second stage t2 is also referred to as a compensation stage.
For the structures shown in
Further, in the structures shown in
For example, still assuming that the potential of the first initial power supply signal is Vinit10, the potential of the second initial power supply signal is Vinit20, the potential of the first reference power supply signal is Vref10, the potential of the driving power supply signal is Vdd, and the potential of the data signal is Vdt0, then in the third stage t3, the potential of the first node N1 is Vdt0, the potential of the third node N3 is maintained as Vdd, and the potential of the second node N2 and the potential of the fifth node N5 are maintained as Vdd+Vth. That is, in the third stage t3, the potentials at two terminals of the first capacitor C1 are Vdt0 and Vdd, and the potentials at two terminals of the second capacitor C2 are Vdd and Vdd+Vth. The third stage t3 is also referred to as a data writing stage.
For the structures shown in
Further, in the structures shown in
For example, still assuming that the potential of the first initial power supply signal is Vinit10, the potential of the second initial power supply signal is Vinit20, the potential of the first reference power supply signal is Vref10, the potential of the driving power supply signal is Vdd, the potential of the data signal is Vdt0, and the potential of the second reference power supply signal is Vref20, then in the fourth stage t4, the potentials at two terminals of the first capacitor C1 are Vref20 and Vdd+Vref20−Vdt, the potential of the gate of the driving transistor is Vdd+Vref20-Vdt+Vth, a path is formed between the driving power supply terminal VDD and the pull-down power supply terminal VSS, and the tenth transistor T10 transmits a driving signal to the fourth node N4 based on the potential of the second node N2 and the driving power supply signal provided by the driving power supply terminal VDD. The driving signal continues to be transmitted to the anode of the light-emitting element L1 through the turned-on seventh transistor T7. The light-emitting element L1 emits light under the action of the voltage difference between the driving signal and the pull-down power supply signal provided by the pull-down power supply terminal VSS. The fourth stage t4 is also referred to as a light-emitting stage. With reference to the formula: I0=1/2μnCox(W/L)*(Vgs−Vth)2 based on which the driving transistor (i.e., the tenth transistor T10) generates the driving signal, it can be known that on the basis that the threshold voltage Vth of the driving transistor is written into the second node N2 in the second stage t2 such that the gate-source voltage difference Vgs of the driving transistor equals to Vg−Vs=(Vdd+Vref20−Vdt+Vth)−Vdd=Vref20−Vdt+Vth in the fourth stage t4, the driving current I0 generated by the driving transistor satisfies I0=1/2μnCox(W/L)*(Vref20−Vdt+Vth−Vth)=1/2μnCox(W/L)*(Vdt0−Vref0), which is irrelevant to the threshold voltage Vth, thereby compensating the threshold voltage Vth. Here, μn is the carrier mobility of the driving transistor, Cox is the capacitance of the gate insulating layer of the driving transistor, W/L is the width-to-length ratio of the driving transistor, all of which are constants after the manufacturing process of the display panel is determined.
Still Referring to
For the structures shown in
Further, the first reference power supply signal provided by the first reference power supply terminal Vref1 is transmitted to the first node N1 through the turned-on second transistor T2, and the signal at the first node N1 is changed from the second reference power supply signal in the previous stage (that is, the fourth stage t4) to the first reference power supply signal, that is, the potential at the first node N1 is increased from the lower potential Vref20 of the second reference power supply signal to the higher potential Vref10 of the first reference power supply signal. Under the regulating effect of the first capacitor C1 and the second capacitor C2, the potential of the gate (e.g., the second node N2 shown in
That is, in the embodiments of the present disclosure, the anode of the light-emitting element L1 and the threshold voltage Vth of the driving transistor are reset in the hold frame stage, so that the gate-source voltage difference Vgs of the driving transistor rapidly drops to approximately Vth. Since the fifth transistor T5 included in the compensation sub-circuit 032 is turned off, the potential of the gate of the driving transistor is not affected. Before the light-emitting element L1 returns to emit light, the luminance of the display panel keeps unchanged. In this way, a good low frame rate display can be achieved in a low-frequency refresh state.
Afterwards, when the light-emitting element L1 needs to emit light normally and is turned on again, the potential of the light emission control signal provided by the light emission control terminal EM is set low, and the potential of the scanning signal provided by the scanning signal terminal Scan is set high, so that the second transistor T2 and the third transistor T3 are both turned off, and the sixth transistor T6 and the seventh transistor T7 are both turned on. Further, the second reference power supply signal provided by the second reference power supply terminal Vref2 is transmitted to the first node N1 through the turned-on second transistor T2, so that the potential of the first node N1 returns from the higher potential Vref10 of the first reference power supply signal to the lower potential Vref20 of the second reference power supply signal, and the fourth node N4 is connected to the anode of the light-emitting element L1, thereby reliably driving the light-emitting element L1 to emit light again. In addition, from the hold frame to the stage in which the light-emitting element L1 emits light again, only the potential of the first node N1 jumps and the other devices and capacitors are free of charging and discharging. Therefore, according to the law of conservation of charge, it can be known that after the light-emitting element L1 emits light normally, the potential of the gate of the driving transistor can quickly return to the voltage of normal light emission, which further ensures that the light-emitting element L1 can be reliably driven to emit light.
In summary, the embodiments of the present disclosure provide a method for driving a pixel circuit. In the method, the data writing circuit controls the connection or disconnection between the data terminal and the first node based on the gate driving signal; the reset circuit controls, based on the reset signal and the scanning signal, the connection or disconnection between the initial power supply terminal and the second node and between the initial power supply terminal and the light-emitting element, and the connection or disconnection between the reference power supply terminal and the first node; the potential adjustment circuit controls, based on the compensation signal, the connection or disconnection between the driving power supply terminal and the third node and the connection or disconnection between the second node and the fourth node, and adjusts the potential of the first node, the potential of the second node and the potential of the third node through the coupling effect; the light emission control circuit controls, based on the light emission control signal, the connection or disconnection between the reference power supply terminal and the first node and the connection or disconnection between the fourth node and the light-emitting element; and the drive circuit transmits, based on the potential of the second node and the driving power supply signal, the driving signal to the fourth node to drive the light-emitting element to emit light. In this way, the signal provided by each signal terminal can be flexibly set to achieve a reliable compensation for the threshold voltage of the driving transistor in the drive circuit, thereby ensuring a good display effect.
Additionally, since data is directly written into the second node under the coupling effect of the potential adjustment circuit instead of being written into the second node through the drive circuit, data writing and compensation for the threshold voltage can be achieved through different paths by different circuits, and thus data writing and compensation for the threshold voltage can be separated from each other without affecting each other, which ensures the effective compensation for the threshold voltage, and further ensures a better display effect. Moreover, on the basis of flexibly setting the reference power supply signals provided by the first reference power supply terminal and the second reference power supply terminal, the reference power supply signal at a higher potential can be written into the gate of the driving transistor in the drive circuit in the hold frame, thereby ensuring that the driving transistor is reset reliably in an off state, and ensuring a good display stability, especially at the low frame rate.
With reference to
Optionally, the display device described in the embodiments of the present disclosure may be any product or component having a display function, such as an OLED display device, a mobile phone, a tablet computer, a flexible display device, a television, and a display.
It should be noted that the terms used in the embodiments of the present disclosure are merely used for explaining the embodiments of the present disclosure, but not intended to limit the present disclosure. Unless otherwise defined, the technical terms or scientific terms used in embodiments of the present disclosure should have the ordinary meaning understood by those of ordinary skill in the art to which the present disclosure belongs.
For example, in embodiments of the present disclosure, the terms “first” and “second” are merely used for descriptive purposes, but not construed as indicating or implying any relative importance. The term “a plurality of” refers to two or more unless specifically defined otherwise.
Similarly, “a/an”, “one” and similar words do not limit the quantity, but indicate the presence of at least one.
“comprising”, “including” and similar words mean that the element or object appearing before “comprising” and “including” encompasses the elements, objects and equivalents thereof appearing after “comprising” and “including”, without excluding other elements or objects.
“On,” “under,” “left,” and “right” are merely used to express the relative positional relationships, and when the absolute position of a described object changes, the relative positional relationship may also change accordingly.
The above descriptions are merely optional embodiments of the present disclosure, and are not intended to limit the present disclosure. Within the spirit and principles of the present disclosure, any modifications, equivalent substitutions, improvements, and the like are within the protection scope of the present disclosure.
This application is a U.S. national stage of international application No. PCT/CN2023/088842, fled on Apr. 18, 2023, the disclosure of which is herein incorporated by reference in its entirety.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2023/088842 | 4/18/2023 | WO |
