Patent Application
20190385530
The present application relates to the field of display technologies, and more particularly, to a pixel circuit and a method for driving the same, a display substrate and a method for driving the same, and a display apparatus.
Organic Light-emitting Diode (OLED) displays are one of the hotspots in the current research field. Compared with Liquid Crystal Displays (LCDs), the OLEDs have advantages such as low energy consumption, low production cost, self-illumination, wide viewing angle, and corresponding high speed etc.
Analysis shows that the OLEDs may exhibit a short-term afterimage phenomenon when displaying pictures of different grayscales.
Embodiments of the present application provide a pixel circuit and a method for driving the same, a display substrate and a method for driving the same, and a display apparatus, which can at least improve the short-term afterimage problem.
In order to achieve the above purposes, the embodiments of the present application adopt the following technical solutions.
In a first aspect, there is provided a pixel circuit, comprising: a driving resetting sub-circuit, a writing compensation sub-circuit, a light-emitting resetting sub-circuit, a light-emitting enabling sub-circuit, a driving sub-circuit and a light-emitting device, wherein the driving sub-circuit comprises a driving transistor having a source connected to the writing compensation sub-circuit; the driving resetting sub-circuit is connected to a first resetting signal terminal, a first initial voltage terminal and the driving sub-circuit respectively, and is configured to input a voltage provided at the first initial voltage terminal to a gate of the driving transistor in the driving sub-circuit so as to reset the driving sub-circuit under the control of the first resetting signal terminal; the writing compensation sub-circuit is connected to a scanning signal terminal, a data voltage terminal and the driving sub-circuit respectively, and is configured to input a data voltage output at the data voltage terminal to the driving sub-circuit and perform data compensation on the driving sub-circuit under the control of the scanning signal terminal; and configured to input a reference voltage output at the data voltage terminal to the driving sub-circuit under the control of the scanning signal terminal so that the driving transistor is in an on-bias state when the driving resetting sub-circuit inputs the voltage provided at the first initial voltage terminal to the gate of the driving transistor in the driving sub-circuit so as to reset the driving sub-circuit under the control of the first resetting signal terminal,; the light-emitting resetting sub-circuit is connected to the scanning signal terminal, the first initial voltage terminal and an anode of the light-emitting device respectively, and is configured to input the voltage provided at the first initial voltage terminal to the light-emitting device so as to reset the light-emitting device under the control of the scanning signal terminal, wherein a cathode of the light-emitting device is connected to a second power supply voltage terminal; the light-emitting enabling sub-circuit is connected to an enabling signal terminal, a first power supply voltage terminal, the driving sub-circuit and the light-emitting device respectively, and is configured to provide a voltage at the first power supply voltage terminal to the driving sub-circuit and connect the driving sub-circuit to the light-emitting device under the control of the enabling signal terminal; and the driving sub-circuit is configured to provide a driving current to the light-emitting device.
Alternatively, the driving sub-circuit is further connected to the first power supply voltage terminal; the driving sub-circuit further comprises a storage capacitor; the gate of the driving transistor is electrically connected to the driving resetting sub-circuit and the writing compensation sub-circuit, and a first electrode and a second electrode of the driving transistor are both electrically connected to the light-emitting enabling sub-circuit and the writing compensation sub-circuit; and the storage capacitor has a terminal electrically connected to the gate of the driving transistor, and another terminal electrically connected to the first power supply voltage terminal.
Alternatively, the driving resetting sub-circuit comprises a first transistor, wherein the first transistor has a gate electrically connected to the first resetting signal terminal, a first electrode electrically connected to the gate of the driving transistor, and a second electrode electrically connected to the first initial voltage terminal.
Alternatively, the writing compensation sub-circuit comprises a second transistor and a third transistor, wherein the second transistor has a gate electrically connected to the scanning signal terminal, a first electrode electrically connected to the gate of the driving transistor, and a second electrode electrically connected to a drain of the driving transistor; and the third transistor has a gate electrically connected to the scanning signal terminal, a first electrode electrically connected to the data voltage terminal, and a second electrode electrically connected to the drain of the driving transistor.
Alternatively, the light-emitting resetting sub-circuit comprises a fourth transistor, wherein the fourth transistor has a gate electrically connected to the scanning signal terminal, a first electrode electrically connected to the first initial voltage terminal, and a second electrode electrically connected to the light-emitting device.
Alternatively, the light-emitting enabling sub-circuit comprises a fifth transistor and a sixth transistor, wherein the fifth transistor has a gate electrically connected to the enabling signal terminal, a first electrode electrically connected to the first power supply voltage terminal, and a second electrode electrically connected to the source of the driving transistor; and the sixth transistor has a gate electrically connected to the enabling signal terminal, a first electrode electrically connected to the drain of the driving transistor, and a second electrode electrically connected to the light-emitting device.
Alternatively, the light-emitting device comprises a light-emitting diode, wherein the light-emitting diode has an anode electrically connected to the light-emitting enabling sub-circuit and the light-emitting resetting sub-circuit, and a cathode electrically connected to the second power supply voltage terminal.
In a second aspect, there is provided a display substrate, comprising sub-pixels disposed in an array, wherein each of the sub-pixels comprises the pixel circuit according to the first aspect.
Alternatively, the scanning signal terminals of all the pixel circuits in a row of sub-pixels are all connected to a gate line; the display substrate further comprises at least one switching sub-circuit, wherein each of the at least one switching sub-circuit is connected to a gate line, and all of the at least one switching sub-circuit is connected to a second resetting signal terminal and a second initial voltage terminal; and the switching sub-circuit is configured to input a voltage provided at the second initial voltage terminal to the gate line under the control of the second resetting signal terminal, so that the writing compensation sub-circuit inputs a data voltage output at the data voltage terminal to the driving sub-circuit in a blanking phase.
Further, each of the at least one switching sub-circuit comprises a seventh transistor, wherein the seventh transistor has a gate electrically connected to the second resetting signal terminal, a first electrode electrically connected to the gate line, and a second electrode electrically connected to the second initial voltage terminal.
In a third aspect, there is provided a display apparatus, comprising the display substrate according to the second aspect.
In a fourth aspect, there is provided a method for driving the pixel circuit according to the first aspect, comprising: in a resetting phase of an image frame, resetting, by the driving resetting sub-circuit, the driving sub-circuit through the first initial voltage terminal under the control of the first resetting signal terminal; in a writing compensation phase of the image frame, providing, by the writing compensation sub-circuit, a data voltage to the driving sub-circuit through the data voltage terminal, and performing data compensation on the driving sub-circuit under the control of the scanning signal terminal, while resetting, by the light-emitting resetting sub-circuit, the light-emitting device through the first initial voltage terminal under the control of the scanning signal terminal; in a light-emitting phase of the image frame, providing, by the light-emitting enabling sub-circuit, a voltage provided at the first power supply voltage terminal to the driving sub-circuit, and connecting the driving sub-circuit to the light-emitting device under the control of the enabling signal terminal, so that the driving sub-circuit provides a driving current to the light-emitting device; and in a blanking phase between adjacent image frames, resetting, by the driving resetting sub-circuit, the driving sub-circuit through the first initial voltage terminal under the control of the first resetting signal terminal, while providing, by the writing compensation sub-circuit, a reference voltage to the driving sub-circuit through the data voltage terminal under the control of the scanning signal terminal, so that the driving transistor in the driving sub-circuit is in an On-Bias state.
In a fifth aspect, there is provided a method for driving a display substrate, wherein the display panel comprises sub-pixels, wherein each of the sub-pixels comprises the pixel circuit according to the first aspect; the display panel further comprises at least one switching sub-circuit, wherein each of the at least one switching sub-circuit is connected to a gate line, and all of the at least one switching sub-circuit is connected to a second resetting signal terminal and a second initial voltage terminal.
The method for driving a display panel comprises: in a resetting phase of an image frame, resetting by, the driving resetting sub-circuit, the driving sub-circuit through the first initial voltage terminal under the control of the first resetting signal terminal; in a writing compensation phase of the image frame, providing, by the writing compensation sub-circuit, a data voltage to the driving sub-circuit through the data voltage terminal, and performing data compensation on the driving sub-circuit under the control of the scanning signal terminal; and resetting, by the light-emitting resetting sub-circuit, the light-emitting device through the first initial voltage terminal under the control of the scanning signal terminal; in a light-emitting phase of the image frame, providing, by the light-emitting enabling sub-circuit, a voltage provided at the first power supply voltage terminal to the driving sub-circuit, and connecting the driving sub-circuit to the light-emitting device under the control of the enabling signal terminal, so that the driving sub-circuit provides a driving current to the light-emitting device; and in a blanking phase between adjacent image frames, resetting, by the driving resetting sub-circuit, the driving sub-circuit through the first initial voltage terminal under the control of the first resetting signal terminal, while inputting a voltage provided at the second initial voltage terminal to the gate line through a switch sub-circuit under the control of the second resetting signal terminal, so that the writing compensation sub-circuit provides a reference voltage to the driving sub-circuit through the data voltage terminal, to cause the driving transistor in the driving sub-circuit to be in an On-Bias state.
In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related art, the accompanying drawings to be used in the description of the embodiments or the related art will be briefly described below. Obviously, the accompanying drawings in the following description are only some embodiments of the present application, and other accompanying drawings may further be obtained by those of ordinary skill in the art according to these accompanying drawings without any creative effort.
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. It is obvious that the embodiments described are only a part of the embodiments of the present application, instead of all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without any creative effort shall fall within the protection scope of the present application.
The short-term afterimage phenomenon is related to a hysteresis effect of a driving transistor in an OLED display. A process of the hysteresis effect is as shown in
When a picture of the maximum grayscale is switched to a picture of the intermediate grayscale, the driving current Ids in the sub-pixel when the picture of the maximum grayscale is displayed needs to be reduced. Therefore, hole detrapping will occur on an interface between a semiconductor layer and a gate insulating layer of the driving transistor in the sub-pixel, and at the time, a value of Vgs changes from V_w at point A1 to V_g at point A2. When a picture of the minimum grayscale is switched to a picture of the intermediate grayscale, the driving current Ids of the driving transistor in the sub-pixel when the picture of the minimum grayscale is displayed needs to be increased. Therefore, hole trapping will occur on the interface between the semiconductor layer and the gate insulating layer of the driving transistor in the sub-pixel, and at the time, the value of Vgs changes from V_b at point A3 to V_g at point A4. It can be seen that paths for the voltage change during the hole trapping process and the hole detrapping process are different, and therefore, the different paths along which voltage V_g at point A2 and the point A4 is reached correspond to different driving currents Ids respectively. As a result, there is a difference between brightness of the sub-pixel of the picture of the intermediate grayscale that is switched from the picture of the maximum grayscale and brightness of the sub-pixel of the picture of the intermediate grayscale that is switched from the picture of the minimum grayscale, which results in a short-term afterimage phenomenon. The different driving currents Ids change from the above points A2 and A4 to point B after a period of time, and the afterimage disappears.
The embodiments of the present application provide a pixel circuit, as shown in
Specifically, the resetting sub-circuit 10 is connected to a first resetting signal terminal RST1, a first initial voltage terminal Vint1 and the driving sub-circuit 50 respectively, and is configured to input a voltage provided at the first initial voltage terminal Vint1 to the driving sub-circuit 50 so as to reset the driving sub-circuit 50 under the control of the first resetting signal terminal RST1.
The writing compensation sub-circuit 20 is connected to a scanning signal terminal S, a data voltage terminal D and the driving sub-circuit 50 respectively, and is configured to input, under the control of the scanning signal terminal S, a reference voltage output at the data voltage terminal D to the driving sub-circuit 50 in a blanking phase, so that the driving transistor Td is in an On-Bias state in the blanking phase, and input a data voltage output at the data voltage terminal D to the driving sub-circuit 50 and perform data compensation on the driving sub-circuit 50 in a writing compensation phase.
The light-emitting resetting sub-circuit 30 is connected to the scanning signal terminal S, the first initial voltage terminal Vint1 and an anode of the light-emitting device L respectively, and is configured to input the voltage provided at the first initial voltage terminal Vint1 to the light-emitting device L so as to reset the light-emitting device L under the control of the scanning signal terminal S. A cathode of the light-emitting device L is connected to a second power supply voltage terminal ELVSS.
The light-emitting enabling sub-circuit 40 is connected to an enabling signal terminal EM, a first power supply voltage terminal ELVDD, the driving sub-circuit 50 and the light-emitting device L respectively, and is configured to provide a voltage at the first power supply voltage terminal ELVDD to the driving sub-circuit 50 and connect the driving sub-circuit 50 to the light-emitting device L under the control of the enabling signal terminal EM.
The driving sub-circuit 50 is configured to provide a driving current to the light-emitting device L.
Description will be made below by taking a P-type driving transistor Td as an example. It should be noted that the driving transistor Td has a relatively large size and has a certain driving capability. Therefore, the driving transistor Td may provide the driving current to the light-emitting device L to drive the light-emitting device L to emit light with the output voltage at the first power supply voltage terminal ELVDD which is provided by the light-emitting enabling sub-circuit 40.
It can be understood that the blanking phase is a time period between adjacent image frames, and during the time period, a residual image of a previous frame is eliminated. For any image frame, it is progressively scanned from a first row of gate line to a last row of gate line. Therefore, the blanking phase occurs after a last row of gate line of a previous image frame is scanned completely and a last row of sub-pixels of the previous image frame completes the display and before a first row of gate line of a next image frame start to be scanned.
The embodiments of the present application provide a pixel circuit, in which the writing compensation sub-circuit 20 inputs the data voltage output at the data voltage terminal D to the driving transistor Td in the driving sub-circuit 50, and performs data compensation on the driving transistor Td in the writing compensation phase, so that when the driving transistor Td drives the light-emitting device L to emit light, the current flowing through the light-emitting device L is independent of a threshold voltage of the driving transistor Td, thereby eliminating the influence of the threshold voltage on light-emitting brightness, and improving display uniformity. Further, in the blanking phase, the voltage provided at the first initial voltage terminal Vint1 is input to the gate of the driving transistor Td, and at the same time, the reference voltage (denoted as VD) output at the data voltage terminal D is input to the source of the driving transistor. In this way, Vgs of all the driving transistors Td of the display panel can be reset at the same time (to Vint1-VD), and thereby the driving transistors Td are in an On-Bias state, that is, all the driving transistors Td are in the same hole trapping state. Therefore, writing and compensation of the data voltage are performed on the driving transistors Td in the same state regardless of a data voltage of a previous frame, thereby improving the short-term afterimage problem caused by the hysteresis effect.
For example, by taking a case it switches from a picture of a maximum grayscale and a picture of a minimum grayscale to a picture of an intermediate grayscale respectively as an example, as shown in
As shown in
Here, the driving transistor Td has a gate electrically connected to the driving resetting sub-circuit 10 and the writing compensation sub-circuit 20, and a source and a drain both electrically connected to the light-emitting enabling sub-circuit 40 and the writing compensation sub-circuit 20.
The storage capacitor Cst has a terminal electrically connected to the gate of the driving transistor Td, and another terminal electrically connected to the first power supply voltage terminal ELVDD.
It should be noted that the driving sub-circuit 50 may further comprise a plurality of driving transistors Td connected in parallel. The above description is merely an example of the driving sub-circuit 50. Other structures having the same functions as those of the driving sub-circuit 50 will not be described here again, and should fall within the protection scope of the present application.
Description will be made below by taking transistors other than the driving transistor being P-type transistors as an example, and each of the P-type transistors is turned on when a low level signal is input at a gate thereof. A first electrode of the P-type transistor is one of a source and a drain, and a second electrode of the P-type transistor is the other of the source and the drain which is different from the first electrode. Of course, the transistors other than the driving transistor may also be other types of transistors, such as N-type transistors, wherein each of the N-type transistors is turned on when a high level signal is input at a gate thereof. This is not limited in the present application.
As shown in
The first transistor T1 has a gate electrically connected to the first resetting signal terminal RST1, a first electrode electrically connected to the gate of the driving transistor Td, and a second electrode electrically connected to the first initial voltage terminal Vint1.
It should be noted that the driving resetting sub-circuit 10 may further comprise a plurality of switching transistors connected in parallel with the first transistor T1. The above description is merely an example of the driving resetting sub-circuit 10. Other structures having the same functions as those of the driving resetting sub-circuit 10 will not be described here again, and should fall within the protection scope of the present application.
As shown in
The second transistor T2 has a gate electrically connected to the scanning signal terminal S, a first electrode electrically connected to the gate of the driving transistor Td, and a second electrode electrically connected to the drain of the driving transistor Td.
The third transistor T3 has a gate electrically connected to the scanning signal terminal S, a first electrode electrically connected to the data voltage terminal D, and a second electrode electrically connected to the source of the driving transistor Td.
It should be noted that the writing compensation sub-circuit 20 may further comprise a plurality of switching transistors connected in parallel with the second transistor T2, and/or a plurality of switching transistors connected in parallel with the third transistor T3. The above description is merely an example of the writing compensation sub-circuit 20. Other structures having the same functions as those of the writing compensation sub-circuit 20 will not be described here again, and should fall within the protection scope of the present application.
As shown in
The fourth transistor T4 has a gate electrically connected to the scanning signal terminal S, a first electrode electrically connected to the first initial voltage terminal Vint1, and a second electrode electrically connected to the light-emitting device L.
Here, the light-emitting device L comprises a light-emitting diode, which may be a semiconductor light-emitting diode or an organic light-emitting diode. The second electrode of the fourth transistor T4 is electrically connected to an anode of the light-emitting diode.
It should be noted that the light-emitting resetting sub-circuit 30 may further comprise a plurality of switching transistors connected in parallel with the fourth transistor T4. The above description is merely an example of the light-emitting resetting sub-circuit 30. Other structures having the same functions as that of the light-emitting resetting sub-circuit 30 will not be described here again, and should fall within the protection scope of the present application.
As shown in
The fifth transistor T5 has a gate electrically connected to the enabling signal terminal EM, a first electrode electrically connected to the first power supply voltage terminal ELVDD, and a second electrode electrically connected to the source of the driving transistor Td.
The sixth transistor T6 has a gate electrically connected to the enabling signal terminal EM, a first electrode electrically connected to the drain of the driving transistor Td, and a second electrode electrically connected to the light-emitting device L.
That is, if the light-emitting device L is a light-emitting diode, the second electrode of the sixth transistor T6 is electrically connected to an anode of the light-emitting diode.
A cathode of the light-emitting diode is electrically connected to the second power supply voltage terminal ELVSS. Here, in the present application, the first power supply voltage terminal ELVDD outputs a constant high voltage, and the second power supply voltage terminal ELVSS outputs a constant low voltage.
It should be noted that the light-emitting enabling sub-circuit 40 may further comprise a plurality of switching transistors connected in parallel with the fifth transistor T5 and/or a plurality of switching transistors connected in parallel with the sixth transistor T6. The above description is merely an example of the light-emitting enabling sub-circuit 40. Other structures having the same functions as that of the light-emitting enabling sub-circuit 40 will not be described here again, and should fall within the protection scope of the present application.
Based on the above description of a specific circuit of each sub-circuit, in the blanking phase, when the scanning signal terminal S and the first resetting signal terminal RST1 output a low level signal, the enabling signal terminal EM outputs a high level signal, and the data voltage terminal D outputs the reference voltage at a high level (the voltage is denoted as VD), an equivalent circuit diagram of the pixel circuit shown in
The first transistor T1 and the second transistor T2 are turned on, so that the voltage at the first initial voltage terminal Vint1 is input to the gate and the drain of the driving transistor Td; and the third transistor T3 is turned on, so that the reference voltage (the voltage is denoted as VD) output at the data voltage terminal D is input to the source of the driving transistor. Thereby, Vgs of the driving transistor Td is equal to Vint1-VD, and the driving transistor Td is in an On-Bias state. In this way, in the pixel circuits of the sub-pixels of the display panel, all the driving transistors Td are in an On-Bias state, and writing of the data voltage and compensation of the threshold voltage are performed on the driving transistors Td in the same state regardless of a data voltage of a previous frame, thereby improving the short-term afterimage problem caused by the hysteresis effect. In the present application, the reference voltage VD output at the data voltage terminal D should satisfy Vint1-VD<-|Vth| (wherein Vth is the threshold voltage of the driving transistor Td), so that when VD is input to the source of the driving transistor and Vint1 is input to the gate of the driving transistor, the driving transistor Td is in an On-Bias state.
The embodiments of the present application further provide a display substrate, as shown in
For example, a plurality of pixel circuits are arranged in an array on the display substrate, wherein the scanning signal terminals S of the pixel circuits in a row of sub-pixels may be electrically connected to a scanning signal line CL. A first resetting signal terminal RST1 may be electrically connected to a scanning signal line CL of a previous row of sub-pixels. When a low level signal is input to the scanning signal line CL of the previous row of sub-pixels, a driving resetting sub-circuit 10 in a next row of pixel circuit resets a gate of a driving transistor Td.
Based thereon, in the blanking phase, the first resetting signal terminals RST1 in pixel circuits of a first row of sub-pixels output a low level signal, all the scanning signal lines CL output a low level signal, the enabling signal terminal EM outputs a high level signal and the data voltage terminal D outputs the reference voltage at a high level (the voltage is denoted as VD), so that Vgs of driving transistors in the pixel circuits of all sub-pixels may be reset at the same time (to Vint1-VD).
Optionally, as shown in
That is, the voltage provided at the second initial voltage terminal Vint2 is input to all the gate lines CL under the control of the second resetting signal terminal RST2, and the reference voltage output at the data voltage terminal D may be input to sources of all the driving transistors Td under the control of the second initial voltage terminal Vint2. In this case, when a first resetting signal terminal RST1 in a row of pixel circuit is electrically connected to a scanning signal line CL of a previous row of pixel circuit, the voltage at the first initial voltage terminal Vint1 may be input to a gate of a corresponding driving transistor Td. In this way, Vgs of the driving transistors in the pixel circuits of all the sub-pixels may be reset at the same time.
It should be noted that the voltage at the second initial voltage terminal Vint2 should be less than the voltage at the first initial voltage terminal Vint1 to ensure that the reference voltage output at the data voltage terminal D can be input to the sources of all the driving transistors Td under the control of the second initial voltage terminal Vint2.
In this way, it only needs to control the signals at the second resetting signal terminal RST2 and the second initial voltage terminal Vint2, to cause the reference voltage output at the data voltage terminal D to be input to the sources of the driving transistors Td, which makes the control process simpler.
Further, as shown in
The seventh transistor T7 has a gate electrically connected to the second resetting signal terminal RST2, a first electrode electrically connected to the gate line CL, and a second electrode electrically connected to the second initial voltage terminal Vint2.
The embodiments of the present application further provide a display apparatus comprising the display substrate described above.
The embodiments of the present application further provide a method for driving the pixel circuit described above. As shown in
In S10, in a resetting phase P1 of an image frame (as shown in
Specifically, when the first resetting signal terminal RST1 outputs a low level signal, and the scanning signal terminal S and the enabling signal terminal EM output a high level signal, the equivalent circuit diagram of a pixel circuit shown in
The turn-on of the first transistor T1 enables a voltage at the first initial voltage terminal Vint1 to be input to the gate of the driving transistor Td so as to reset the gate of the driving transistor Td, so that a voltage at the gate is equal to the voltage at the first initial voltage terminal Vint1, and the turn-on of the first transistor T1 enables the storage capacitor Cst to be charged so as to reset the storage capacitor Cst.
It should be noted that in a case where the first resetting signal terminals RST1 in the pixel circuits of a row of sub-pixels are electrically connected to a scanning signal line CL connected to a previous row of sub-pixels, when the scanning signal line CL connected to the previous row of sub-pixels outputs a low level signal, the first resetting signal terminals RST1 in the pixel circuits of the current row of sub-pixels output a low level signal.
In S11, in a writing compensation phase P2 of the image frame (as shown in
Specifically, when the scanning signal terminal S outputs a low level signal, and the first resetting signal terminal RST1 and the enabling signal terminal EM output a high level signal, the equivalent circuit diagram of a pixel circuit shown in
The turn-on of the third transistor T3 may enable the data voltage (denoted as Vdata) output at the data voltage terminal D to be input to the source of the driving transistor Td. At this time, the potential at the first electrode is Vdata, Vgs=Vint1-Vdata<-|Vth|, and the driving transistor Td is turned on. The turn-on of the second transistor T2 enables the gate of the driving transistor Td to be electrically connected to the drain of the driving transistor, to charge the storage capacitor Cst. At the same time, the storage capacitor Cst discharges the gate of the driving transistor Td until the voltage at the gate reaches Vdata-|Vth|, and the charging stops. By taking a P-type enhancement transistor that is turned on when Vgs<-|Vth| as an example, when the voltage at the gate of the driving transistor Td reaches Vdata-|Vth|, the driving transistor Td is turned off, and at the time, data writing and data compensation are completed.
Further, the turn-on of the fourth transistor T4 enables the voltage at the first initial voltage terminal Vint1 to be input to the anode of the light-emitting device L so as to reset charges remaining on the anode of the light-emitting device L, so as to protect the light-emitting device L.
It should be noted that in a case where the first resetting signal terminals RST1 in the pixel circuits of a row of sub-pixels are electrically connected to a scanning signal line CL connected to a previous row of sub-pixels, when the scanning signal line CL connected to the previous row of sub-pixels outputs a high level signal, the first resetting signal terminals RST1 of the pixel circuits in the sub-pixels connected to the scanning signal line CL output a high level signal.
In S12, in a light-emitting phase P3 of the image frame (as shown in
When the enabling signal terminal EM outputs a low level signal, and the first resetting signal terminal RST1 and the scanning signal terminal S output a high level signal, the equivalent circuit diagram of a pixel circuit shown in
The turn-on of the fifth transistor T5 enables the voltage provided at the first power supply voltage terminal ELVDD to be input to the source of the driving transistor Td, and the turn-on of the sixth transistor T6 enables the drain of the driving transistor Td to be electrically connected to the anode of the light-emitting device L. Here, since Vgs of the driving transistor Td is equal to Vdata-|Vth|-ELVDD<-|Vth|, the driving transistor Td is turned on, and the driving transistor Td provides a driving current flowing to the light-emitting device L, to cause the light-emitting device L to emit light. At this time, the current Is flowing through the light-emitting device L is:
where K=W/L×C×u, W/L is an aspect ratio of the driving transistor Td, C is capacitance of a channel insulating layer, and u is a channel carrier mobility.
It can be seen that the current flowing through the driving transistor Td is only related to the data voltage provided at the data voltage terminal D for realizing the display and the voltage provided at the first power supply voltage terminal ELVDD, and not dependent on the threshold voltage Vth of the driving transistor Td, thereby eliminating the influence of the threshold voltage Vth of the driving transistor Td on the brightness of the light-emitting device L, and improving the uniformity of the brightness of the light-emitting device L.
In S13, in a blanking phase P4 between adjacent image frames (as shown in
Specifically, when the scanning signal terminal S and the first resetting signal terminal RST1 output a low level signal, and the enabling signal terminal EM outputs a high level signal, the equivalent circuit diagram of a pixel circuit shown in
The turn-on of the first transistor T1 and the second transistor T2 enables the voltage at the first initial voltage terminal Vint1 to be input to the gate and the drain of the driving transistor Td; and the turn-on of the third transistor T3 enables the reference voltage (denoted as VD) output at the data voltage terminal D to be input to the source of the driving transistor Td. In this way, Vgs of all driving transistors Td is equal to Vint1-VD, and the driving transistors Td are turned on. In this way, writing and compensation of the data voltage are performed on the driving transistors Td in the same state, regardless of a data voltage of a previous frame, thereby improving the short-term afterimage problem caused by the hysteresis effect. In the present application, the reference voltage VD output at the data voltage terminal D and the data voltage Vdata output at the data voltage terminal D may be the same or different.
It should be noted that when the first resetting signal terminals RST1 in the pixel circuits of a row of sub-pixels are electrically connected to a scanning signal line CL of a previous row of sub-pixels, it only needs to control all the gate lines CL to output a low level signal. Of course, if the first resetting signal terminals RST1 in the pixel circuits of a first row of sub-pixels also output a low level signal, all the driving transistors Td may be caused to be turned on, and Vgs of the driving transistors Td is equal to Vint1-VD.
In addition, after the blanking phase, in a resetting phase of a next image frame, the gate of the driving transistor Td is reset, which may enable Vgs of the driving transistor Td to be kept as Vint1-VD until the data voltage is written.
It should be noted that when the pixel circuit described above is applied to a display panel, a plurality of pixel circuits are arranged in an array on the display substrate. In a process of displaying an image frame, the scanning signal lines CL are turned on row by row to complete display of the image frame. After the P1 to P3 phases are completed for the pixel circuits in all rows of sub-pixels, all the pixel circuits enter the blanking phase P4.
Further, as shown in
When the pixel circuits are disposed in sub-pixels of the display substrate, the scanning signal terminals S in the pixel circuits of each row of sub-pixels are electrically connected to a scanning signal line CL, and the first resetting signal terminals RST1 in the pixel circuits of the row of sub-pixels are electrically connected to a scanning signal line CL of a previous row of sub-pixels (as shown in
The embodiments of the present application further provide a method for driving a display substrate, wherein the display substrate comprises at least one sub-pixel, and each of the at least one sub-pixel comprises the pixel circuit described above, wherein the scanning signal terminals S of the pixel circuits in each row of sub-pixels are electrically connected to a scanning signal line CL, each switching sub-circuit 60 is electrically connected to a gate line CL, and all the switching sub-circuits 60 are electrically connected to the second resetting signal terminal RST2 and the second initial voltage terminal Vint2 (as shown in
As shown in
In S20, in a resetting phase P1 of an image frame (as shown in
For details of this step, refer to the above description at S10.
In S21, in a writing compensation phase P2 of the image frame (as shown in
For details of this step, refer to the above description at S11.
In S22, in a light-emitting phase P3 of the image frame (as shown in
For details of this step, refer to the above description at S12.
In S23, in a blanking phase between adjacent image frames (as shown in
For pixel circuits of all sub-pixels, when the voltage provided at the second initial voltage terminal Vint2 is input to a gate line CL, the scanning signal terminals S connected to the gate line CL output a low level signal under the control of the signal output at the second resetting signal terminal RST2, so that the scanning signal terminals S output a low level signal. Of course, the first resetting signal terminals RST1 connected to the gate line CL may also output a low level signal.
For details of this step, refer to the above description at S13.
It should be noted that, as shown in
The above description is merely specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Changes or substitutions which are easily obtained by any skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be determined by the protection scope of the claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201710769889.3 | Aug 2017 | CN | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2018/082503 | 4/10/2018 | WO | 00 |
