Patent Application
20250061861
The following disclosure relates to a display device, and more specifically to a display device including pixel circuits each including a display element driven by current, such as an organic EL element, and a method of driving the display device.
In recent years, an organic EL display device including pixel circuits each including an organic EL element has been put to practical use. The organic EL element is also called an organic light-emitting diode (OLED) and is a self-emissive display element that emits light at luminance determined based on a current flowing therethrough. Since the organic EL element is thus a self-emissive display element, the organic EL display device can easily achieve slimming down, a reduction in power consumption, an increase in luminance, etc., compared to a liquid crystal display device that requires a backlight, a color filter, and the like. Thus, in recent years, development of organic EL display devices has been actively implemented. For a pixel circuit of an organic EL display device, typically, a thin-film transistor (TFT) is adopted as a drive transistor for controlling supply of a current to an organic EL element. However, the thin-film transistor is likely to cause variations in its characteristics. Specifically, variations are likely to occur in threshold voltage. If variations in threshold voltage occur in drive transistors provided in a display unit, then variations in luminance occur, degrading display quality. Hence, there are proposed various processes (compensation processes) for compensating for variations in threshold voltage.
For schemes for the compensation processes, there are known an internal compensation scheme in which a compensation process is performed by providing, in a pixel circuit, a capacitor for holding information on a threshold voltage of a drive transistor, and an external compensation scheme in which a compensation process is performed by, for example, measuring, by a circuit provided external to a pixel circuit, the magnitude of a current flowing through a drive transistor under a predetermined condition, and correcting a video signal based on a result of the measurement.
In addition, for a low power consumption display device, a display device that performs pause driving is known. The pause driving is a driving method in which a driving period and a pause period are provided when the same image is continuously displayed, and a drive circuit is operated during the driving period, whereas operation of the drive circuit is stopped during the pause period. The pause driving is also called “intermittent driving” or “low-frequency driving”. The pause driving can be applied when off-leakage current in the transistor in the pixel circuit is small.
When pause driving such as that described above is performed in an organic EL display device, during the driving period, an organic EL element in a pixel circuit is temporarily brought into turn-off state upon performing writing of a data voltage, but during the pause period, since operation of a drive circuit stops, the organic EL element continues to emit light at luminance determined based on a data voltage written during an immediately preceding driving period. During the pause driving, the driving period and the pause period alternately appear. For example, as shown in
Hence, there is proposed a configuration in which luminance is reduced at an appropriate frequency during the pause period by temporarily bringing the organic EL element into turn-off state also during the pause period in order to inhibit occurrence of flicker (hereinafter, this configuration is referred to as “periodic turn-off configuration”).
However, even if the periodic turn-off configuration is adopted, since a thin-film transistor serving as a drive transistor in a pixel circuit has hysteresis characteristics, when pause driving is performed, flicker is still visually recognized, which will be described in detail below. Note that here, voltage stress applied between the gate and source of the drive transistor is referred to as “Vgs stress”. Note also that it is assumed that the drive transistor is of P-channel type.
When the magnitude of the Vgs stress changes, the IV characteristic also changes. Note, however, that since hole trapping and hole detrapping take time to occur, the IV characteristic gently changes. For example, when a state in which negative Vgs stress is provided to the drive transistor is changed to a state in which positive Vgs stress is provided to the drive transistor, as indicated by an arrow given reference character 94 in
During a light-emission period, the gate-source voltage Vgs is high (the gate potential is high) compared to that during the initialization period. Thus, for example, as indicated by an arrow given reference character 97 in
For example, it is assumed that an IV characteristic at the time of starting the light-emission period included in the driving period is represented by a curve given reference character 98 in
As described above, during the driving period, the waveform of luminance is rounded. On the other hand, during the pause period, since the gate-source voltage is maintained at a constant level, there is no change in the IV characteristic of the drive transistor. Thus, during the pause period, the waveform of luminance is not rounded. Accordingly, the waveform of luminance differs between the driving period and the pause period. As a result, flicker is visually recognized.
In view of this, US 2020/0243017 A1 describes that a thin-film transistor having a bottom gate is adopted as a drive transistor, and the potential of the bottom gate is changed before the initialization period, by which positive Vgs stress is provided to the drive transistor. In addition, US 2020/0118487 A1 describes that negative or positive Vgs stress is provided to a drive transistor during the pause period so that a luminance waveform in the driving period is similar to a luminance waveform in the pause period.
However, according to a technique disclosed in US 2020/0243017 A1, a manufacturing process requires a step for forming a bottom gate of a drive transistor. For example, there is required a step of depositing and patterning a bottom-gate metal layer, and in some cases, there is required a step of making a contact hole that connects the bottom-gate metal layer to another metal layer.
In addition, regarding the technique disclosed in US 2020/0243017 A1, there is a concern that occurrence of flicker is not sufficiently suppressed, which will be described with reference to
Furthermore, according to a technique disclosed in US 2020/0118487 A1, there is required driving operation in which a bias signal is provided to a control terminal of a drive transistor during the pause period, and thus, power consumption during the pause period increases due to the driving operation. That is, an effect of reducing power consumption by adopting pause driving is small.
An object of the following disclosure is therefore to suppress occurrence of flicker upon pause driving while suppressing an increase in power consumption in a display device that uses display elements driven by current.
A pixel circuit according to some embodiments of the present disclosure is a pixel circuit provided in a display device that can operate in a pause driving mode in which a driving period and a pause period alternately appear, the driving period including one or a plurality of refresh frame periods during which writing of a data voltage is performed, and the pause period including one or a plurality of non-refresh frame periods during which writing of a data voltage is not performed, the pixel circuit including:
A display device according to some embodiments of the present disclosure is a display device including:
A driving method according to some embodiments of the present disclosure is a method of driving a display device including a plurality of pixel circuits, wherein
According to some embodiments of the present disclosure, in a display device that can operate in a pause driving mode, in a refresh frame period, before a data voltage is provided to a drive current control node, an initialization voltage that brings a drive transistor into on state is provided to the drive current control node after an off-voltage that brings the drive transistor into off state is provided to the drive current control node by a reset circuit. By this, in the refresh frame period, before a data voltage is provided to the drive current control node, the hole-trap occupancy in a channel of the drive transistor sufficiently decreases and then increases. As a result, during a light-emission period in the refresh frame period, the hole-trap occupancy in the channel of the drive transistor is maintained at a substantially constant value. Therefore, there is almost no change in luminance in the light-emission period in the refresh frame period. That is, the waveform of luminance is not rounded. Thus, a luminance waveform in a driving period and a luminance waveform in a pause period are identical, suppressing occurrence of flicker. In addition, since a state in which the operation of the drive transistor stops is maintained during the pause period, there is no increase in power consumption. As such, it becomes possible to suppress occurrence of flicker upon pause driving while suppressing an increase in power consumption in a display device that uses display elements driven by current.
With reference to the accompanying drawings, embodiments will be described below. Note that in the following description, it is assumed that i and j are integers greater than or equal to 2, n is an integer between 1 and i, inclusive, and m is an integer between 1 and j, inclusive.
In the display unit 200 there are disposed (i+2) first scanning signal lines NS(−1) to NS(i), i second scanning signal lines PS(1) to PS(i), i light-emission control lines EM(1) to EM(i), and j data signal lines DL(1) to DL(j). Note that depiction of those lines is omitted in the display unit 200 in
Furthermore, in the display unit 200 there are disposed power lines (not shown) which are shared between the pixel circuits 20. More specifically, there are disposed a power line that supplies a high-level power supply voltage ELVDD for driving organic EL elements (hereinafter, referred to as “high-level power line”), a power line that supplies a low-level power supply voltage ELVSS for driving the organic EL elements (hereinafter, referred to as “low-level power line”), a power line that supplies an initialization voltage Vini for initializing the internal states of the pixel circuits 20 (hereinafter, referred to as “initialization power line”), and a power line that supplies a control voltage Voff for providing the aforementioned positive Vgs stress to drive transistors in the pixel circuits 20 (hereinafter, referred to as “control-voltage power line”).
Meanwhile, the organic EL display device according to the present embodiment has two operating modes (a normal driving mode and a pause driving mode). In the normal driving mode, the organic EL display device operates such that a refresh frame period which is a frame period during which writing of a data voltage is performed continuously appears. In the pause driving mode, the organic EL display device operates such that a driving period including one or a plurality of refresh frame periods and a pause period including one or a plurality of non-refresh frame periods during which writing of a data voltage is not performed alternately appear.
Operation of each component shown in
The gate driver 300 is connected to the first scanning signal lines NS(−1) to NS(i) and the second scanning signal lines PS(1) to PS(i). The gate driver 300 applies first scanning signals to the first scanning signal lines NS(−1) to NS(i) and applies second scanning signals to the second scanning signal lines PS(1) to PS(i), based on the gate control signals GCTL outputted from the display control circuit 100. That is, the gate driver 300 sequentially and selectively drives the first scanning signal lines NS(−1) to NS(i) and the second scanning signal lines PS(1) to PS(i).
The emission driver 400 is connected to the light-emission control lines EM(1) to EM(i). The emission driver 400 applies light-emission control signals to the light-emission control lines EM(1) to EM(i), based on the emission driver control signals EMCTL outputted from the display control circuit 100.
The source driver 500 includes a j-bit shift register, a sampling circuit, a latch circuit, j D/A converters, and the like, which are not shown. The shift register has j cascade-connected registers. The shift register transfers, in turn, a pulse of the source start pulse signal supplied to a register at an initial stage, from an input terminal to an output terminal based on the source clock signal. In response to the transfer of the pulse, a sampling pulse is outputted from each stage of the shift register. Based on the sampling pulse, the sampling circuit stores digital video signals DV. The latch circuit captures and holds digital video signals DV for one row that are stored in the sampling circuit, in accordance with the latch strobe signal. The D/A converters are provided so as to correspond to the respective data signal lines DL(1) to DL(j). The D/A converters convert the digital video signals DV held in the latch circuit into analog voltages. The converted analog voltages are simultaneously applied, as data signals, to all data signal lines DL(1) to DL(j).
In the above-described manner, the data signals are applied to the data signal lines DL(1) to DL(j), the first scanning signals are applied to the first scanning signal lines NS(−1) to NS(i), the second scanning signals are applied to the second scanning signal lines PS(1) to PS(i), and the light-emission control signals are applied to the light-emission control lines EM(1) to EM(i), by which an image based on the input image signal DIN is displayed on the display unit 200.
With reference to
Meanwhile, the transistors T1, T2, T7, and T8 are N-channel IGZO-TFTs (thin-film transistors having a channel layer made of an oxide semiconductor containing indium, gallium, zinc, and oxygen). The transistors T3 to T6 are P-channel LTPS-TFTs (thin-film transistors having a channel layer made of low-temperature polysilicon). For these transistors, the IGZO-TFT has a small off-leakage current and thus is desirable as a switching element in a pixel circuit, etc. In addition, the low-temperature polysilicon has high mobility, and thus, when an LTPS-TFT is used as a drive transistor, the ability to drive an organic EL element improves, and when an LTPS-TFT is used as a switching element, the on-resistance decreases. Note that in the pixel circuit 20, the transistors T1 to T3 and T5 to T8 other than the drive transistor T4 operate as switching elements.
The first initialization transistor T1 is connected at its control terminal to a light-emission control line EM(n) in the nth row, connected at its first conductive terminal to a second conductive terminal of the second light-emission control transistor T6 and an anode of the organic EL element 21, and connected at its second conductive terminal to an initialization power line. The threshold voltage compensation transistor T2 is connected at its control terminal to a first scanning signal line NS(n) in the nth row, connected at its first conductive terminal to a second conductive terminal of the drive transistor T4 and a first conductive terminal of the second light-emission control transistor T6, and connected at its second conductive terminal to a control terminal of the drive transistor T4, a first conductive terminal of the second initialization transistor T7, a second conductive terminal of the off-voltage application transistor T8, and the second electrode of the holding capacitor Cst.
The write control transistor T3 is connected at its control terminal to a second scanning signal line PS(n) in the nth row, connected at its first conductive terminal to a data signal line DL(m) in the mth column, and connected at its second conductive terminal to a first conductive terminal of the drive transistor T4 and a second conductive terminal of the first light-emission control transistor T5. The drive transistor T4 is connected at its control terminal to the second conductive terminal of the threshold voltage compensation transistor T2, the first conductive terminal of the second initialization transistor T7, the second conductive terminal of the off-voltage application transistor T8, and the second electrode of the holding capacitor Cst, connected at its first conductive terminal to the second conductive terminal of the write control transistor T3 and the second conductive terminal of the first light-emission control transistor T5, and connected at its second conductive terminal to the first conductive terminal of the threshold voltage compensation transistor T2 and the first conductive terminal of the second light-emission control transistor T6.
The first light-emission control transistor T5 is connected at its control terminal to the light-emission control line EM(n) in the nth row, connected at its first conductive terminal to a high-level power line, and connected at its second conductive terminal to the second conductive terminal of the write control transistor T3 and the first conductive terminal of the drive transistor T4. The second light-emission control transistor T6 is connected at its control terminal to the light-emission control line EM(n) in the nth row, connected at its first conductive terminal to the first conductive terminal of the threshold voltage compensation transistor T2 and the second conductive terminal of the drive transistor T4, and connected at its second conductive terminal to the first conductive terminal of the first initialization transistor T1 and the anode of the organic EL element 21.
The second initialization transistor T7 is connected at its control terminal to a first scanning signal line NS(n−1) in an (n−1)th row, connected at its first conductive terminal to the second conductive terminal of the threshold voltage compensation transistor T2, the control terminal of the drive transistor T4, the second conductive terminal of the off-voltage application transistor T8, and the second electrode of the holding capacitor Cst, and connected at its second conductive terminal to the initialization power line. The off-voltage application transistor T8 is connected at its control terminal to a first scanning signal line NS(n−2) in an (n−2)th row, connected at its first conductive terminal to a control-voltage power line, and connected at its second conductive terminal to the second conductive terminal of the threshold voltage compensation transistor T2, the control terminal of the drive transistor T4, the first conductive terminal of the second initialization transistor T7, and the second electrode of the holding capacitor Cst.
The holding capacitor Cst is connected at its first electrode to the high-level power line and connected at its second electrode to the second conductive terminal of the threshold voltage compensation transistor T2, the control terminal of the drive transistor T4, the first conductive terminal of the second initialization transistor T7, and the second conductive terminal of the off-voltage application transistor T8. The organic EL element 21 is connected at its anode to the first conductive terminal of the first initialization transistor T1 and the second conductive terminal of the second light-emission control transistor T6, and connected at its cathode to a low-level power line.
As can be grasped from
Note that a drive current control node is implemented by the first node N1, and a drive current control node initialization transistor is implemented by the second initialization transistor T7.
Here, a comparative example for comparing with the present embodiment will be described.
During a light-emission period 11, which is a period before the light-emission control signal EM(n) changes from low level to high level in a refresh frame period RF, the first light-emission control transistor T5 and the second light-emission control transistor T6 are maintained in on state, by which a drive current flows as indicated by an arrow given reference character 61 in
When the light-emission control signal EM(n) changes from low level to high level, the first light-emission control transistor T5 and the second light-emission control transistor T6 go into off state. In an initialization period 13, a first scanning signal NS(n−1) changes from low level to high level, by which the second initialization transistor T7 goes into on state. By this, as indicated by an arrow given reference character 62 in
Thereafter, in a writing period 14, a first scanning signal NS(n) changes from low level to high level, by which the threshold voltage compensation transistor T2 goes into on state, and a second scanning signal PS(n) changes from high level to low level, by which the write control transistor T3 goes into on state. By this, as indicated by an arrow given reference character 63 in
In the light-emission period 15, the light-emission control signal EM(n) changes from high level to low level, by which the first light-emission control transistor T5 and the second light-emission control transistor T6 go into on state. By this, a drive current flows as indicated by the arrow given reference character 61 in
Thereafter, when the light-emission control signal EM(n) changes from low level to high level in a non-refresh frame period NRF, the first light-emission control transistor T5 and the second light-emission control transistor T6 go into off state, and the light-emission period 15 is terminated. Since the first light-emission control transistor T5 and the second light-emission control transistor T6 are maintained in off state throughout a period (turn-off period) before a next light-emission period 16 starts, a drive current is not supplied to the organic EL element 21, and thus, the organic EL element 21 is maintained in turn-off state (see
In the light-emission period 16, the light-emission control signal EM(n) changes from high level to low level, by which the first light-emission control transistor T5 and the second light-emission control transistor T6 go into on state. By this, a drive current flows as indicated by the arrow given reference character 61 in
According to the comparative example such as that described above, as shown in
Next, with reference to
During a period from time point t10 which is the time of starting the refresh frame period RF to time point t11, the light-emission control signal EM(n) is maintained at low level, and thus, the first light-emission control transistor T5 and the second light-emission control transistor T6 are in on state. At this time, the gate-source voltage Vgs(T4) of the drive transistor T4 is at a level based on writing of a data voltage performed in the last refresh frame period RF. Thus, as indicated by an arrow given reference character 64 in
At time point t11, the light-emission control signal EM(n) changes from low level to high level. By this, the first light-emission control transistor T5 and the second light-emission control transistor T6 go into off state. As a result, supply of the current to the organic EL element 21 is interrupted, by which the organic EL element 21 goes into turn-off state. In addition, by the light-emission control signal EM(n) changing from low level to high level, the first initialization transistor T1 goes into on state. By this, the anode potential is initialized based on the initialization voltage Vini.
At time point t12, the first scanning signal NS(n−2) changes from low level to high level. By this, the off-voltage application transistor T8 goes into on state, and a control voltage Voff is provided to the first node N1 as indicated by an arrow given reference character 65 in
At time point t14, the first scanning signal NS(n−1) changes from low level to high level, by which the second initialization transistor T7 goes into on state. By this, as indicated by an arrow given reference character 66 in
At time point t16, the first scanning signal NS(n) changes from low level to high level. By this, the threshold voltage compensation transistor T2 goes into on state. At time point t17, the second scanning signal PS(n) changes from high level to low level. By this, the write control transistor T3 goes into on state. Thus, as indicated by an arrow given reference character 67 in
At time point t20, the light-emission control signal EM(n) changes from high level to low level, by which the first light-emission control transistor T5 and the second light-emission control transistor T6 go into on state. By this, a drive current flows as indicated by the arrow given reference character 64 in
Thereafter, in the non-refresh frame period NRF, at time point t22, the light-emission control signal EM(n) changes from low level to high level. By this, the first light-emission control transistor T5 and the second light-emission control transistor T6 go into off state, by which the organic EL element 21 goes into turn-off state. Note that a period from time point t20 to time point t22 in
During a period (turn-off period) from time point t22 to time point t23, the first light-emission control transistor T5 and the second light-emission control transistor T6 are maintained in off state, and thus, the organic EL element 21 is maintained in turn-off state. In addition, driving of the first scanning signal lines NS and the second scanning signal line PS also stops, and thus, the threshold voltage compensation transistor T2, the write control transistor T3, the second initialization transistor T7, and the off-voltage application transistor T8 are maintained in off state.
At time point t23, the light-emission control signal EM(n) changes from high level to low level, by which the first light-emission control transistor T5 and the second light-emission control transistor T6 go into on state. By this, a drive current flows as indicated by the arrow given reference character 64 in
In the present embodiment, a light-emission stopping step is implemented by operation performed at time point t11, an off-voltage applying step is implemented by operation performed during the period from time point t12 to time point t13, an initializing step is implemented by operation performed during the period from time point t14 to time point t15, a data voltage writing step is implemented by operation performed during the period from time point t16 to time point t19, and a light-emission resuming step is implemented by operation performed at time point t20.
According to the present embodiment, the pixel circuit 20 of the organic EL display device that can operate in the pause driving mode is provided with the off-voltage application transistor T8 for providing a control voltage Voff that brings the drive transistor T4 into off state to the control terminal of the drive transistor T4. In a refresh frame period RF when the organic EL display device operates in the pause driving mode, before a data voltage is provided to the control terminal of the drive transistor T4 through the diode-connected drive transistor T4, the control voltage Voff is provided to the control terminal of the drive transistor T4 through the off-voltage application transistor T8, and then an initialization voltage Vini that brings the drive transistor T4 into on state is provided to the control terminal of the drive transistor T4. As to this, when the control voltage Voff which is a high-level voltage is provided to the control terminal of the drive transistor T4, the energy band regarding the drive transistor T4 bends as shown in
Variants of the first embodiment will be described.
As can be grasped from
According to the present variant, the same effects as those in the first embodiment are obtained. In addition, since the second scanning signal line PS which is an existing wiring line is used as a wiring line for providing positive Vgs stress to the drive transistor T4, an increase in definition is easily achieved compared to the first embodiment.
According to the present variant, the same effects as those in the first embodiment are obtained. In addition, since the high-level power line which is an existing wiring line is used as a wiring line for providing positive Vgs stress to the drive transistor T4, an increase in definition is easily achieved compared to the first embodiment.
A second embodiment will be described. Note that description of the same points as those of the first embodiment is omitted as appropriate.
An overall configuration is substantially the same as that of the first embodiment. Note, however, that in the present embodiment, the control-voltage power line (a power line for supplying the control voltage Voff) is not disposed in the display unit 200, and i reset control signal lines Voi(1) to Voi(i) each for providing a voltage (off-voltage) that brings the drive transistor T4 into off state and a voltage (initialization voltage) that initializes the drive transistor T4 to the first node N1 are disposed in the display unit 200. In addition, the organic EL display device has a reset control signal line driver (reset control signal line drive circuit) that drives the i reset control signal lines Voi(1) to Voi(i). A high-level voltage and a low-level voltage are alternately applied as a reset control signal to each reset control signal line Voi. In the following description, when necessary, the reset control signal is also given reference character Voi.
With reference to
During a period from time point t30 which is the time of starting the refresh frame period RF to time point t31, as with the period from time point t10 to time point t11 in the first embodiment, a drive current based on writing of a data voltage performed in the last refresh frame period RF flows, by which the organic EL element 21 emits light based on the magnitude of the drive current. At time point t31, as with time point t11 in the first embodiment, the anode potential is initialized based on the initialization voltage Vini.
At time point t32, the reset control signal Voi(n) changes from low level to high level. At this time, since the first scanning signal NS(n−2) is maintained at low level, the reset transistor T9 is maintained in off state. Thus, there is no change in the potential at the first node N1 around time point t32.
At time point t33, the first scanning signal NS(n−2) changes from low level to high level. By this, the reset transistor T9 goes into on state, by which the reset control signal Voi is provided to the first node N1. At this time, the reset control signal Voi is at high level. Thus, the potential at the first node N1 increases, increasing the gate-source voltage Vgs(T4) of the drive transistor T4. In this manner, a voltage (off-voltage) that brings the drive transistor T4 into off state is provided to the control terminal of the drive transistor T4.
At time point t34, the reset control signal Voi(n) changes from high level to low level. At this time, since the first scanning signal NS(n−2) is maintained at high level, the reset transistor T9 is maintained in on state. By this, the potential at the first node N1 is initialized based on the low-level voltage. Specifically, the potential at the first node N1 sufficiently decreases, and accordingly, the gate-source voltage Vgs(T4) of the drive transistor T4 sufficiently decreases. At time point t35, the first scanning signal NS(n−2) changes from high level to low level. By this, the reset transistor T9 goes into off state.
At time point t36, the first scanning signal NS(n) changes from low level to high level. By this, the threshold voltage compensation transistor T2 goes into on state. At time point t37, the second scanning signal PS(n) changes from high level to low level. By this, the write control transistor T3 goes into on state. Thus, a data signal (data voltage) DL(m) is provided to the first node N1 through the write control transistor T3, the drive transistor T4, and the threshold voltage compensation transistor T2. By thus providing a data voltage to the control terminal of the drive transistor T4 through the diode-connected drive transistor T4, as in the comparative example and the first embodiment, when a drive current is supplied to the organic EL element 21, variations in the threshold voltage of the drive transistor T4 are compensated for. At time point t38, the second scanning signal PS(n) changes from low level to high level. By this, the write control transistor T3 goes into off state. At time point t39, the first scanning signal NS(n) changes from high level to low level. By this, the threshold voltage compensation transistor T2 goes into off state.
Operation performed after time point t40 is the same as that performed after time point t20 in the first embodiment.
In the present embodiment, a light-emission stopping step is implemented by operation performed at time point t31, an off-voltage applying step is implemented by operation performed during a period from time point t33 to time point t34, an initializing step is implemented by operation performed during a period from time point t34 to time point t35, a data voltage writing step is implemented by operation performed during a period from time point t36 to time point t39, and a light-emission resuming step is implemented by operation performed at time point t40.
According to the present embodiment, the pixel circuit 20 of the organic EL display device that can operate in the pause driving mode is provided with the reset transistor T9 having a control terminal connected to the first scanning signal line NS; a first conductive terminal connected to the control terminal of the drive transistor T4; and a second conductive terminal connected to the reset control signal line Voi to which a high-level voltage and a low-level voltage are alternately applied. In a refresh frame period RF when the organic EL display device operates in the pause driving mode, before a data voltage is provided to the control terminal of the drive transistor T4 through the diode-connected drive transistor T4, a high-level voltage is provided to the control terminal of the drive transistor T4 through the reset transistor T9, and then a low-level voltage is provided to the control terminal of the drive transistor T4. By this, as in the first embodiment, a luminance waveform in the driving period and a luminance waveform in the pause period are identical, suppressing occurrence of flicker. In addition, as in the first embodiment, since a state in which the operation of the drive transistor T4 stops is maintained during the pause period, there is no increase in power consumption. As such, according to the present embodiment, it becomes possible to suppress occurrence of flicker upon pause driving while suppressing an increase in power consumption in the organic EL display device. In addition, the number of transistors included in the pixel circuit 20 is seven, and a single wiring line is used in a shared manner as a wiring line for transmitting a voltage (off-voltage) that brings the drive transistor T4 into off state and as a wiring line for transmitting a voltage (initialization voltage) that initializes the drive transistor T4, and thus, an increase in definition is easily achieved compared to the first embodiment.
A variant of the second embodiment will be described.
With reference to
Operation performed during a period before time point t52 is the same as that performed during a period before time point t32 in the second embodiment. At time point t52, the first scanning signal NS(n−3) changes from low level to high level. At this time, since the first scanning signal NS(n−2) is maintained at low level, the reset transistor T9 is maintained in off state. Thus, there is no change in the potential at the first node N1 around time point t52.
At time point t53, the first scanning signal NS(n−2) changes from low level to high level. By this, the reset transistor T9 goes into on state, by which the first scanning signal NS(n−3) is provided to the first node N1. At this time, the first scanning signal NS(n−3) is at high level. Thus, the potential at the first node N1 increases, increasing the gate-source voltage Vgs(T4) of the drive transistor T4. In this manner, a voltage (off-voltage) that brings the drive transistor T4 into off state is provided to the control terminal of the drive transistor T4.
At time point t54, the first scanning signal NS(n−3) changes from high level to low level. At this time, since the first scanning signal NS(n−2) is maintained at high level, the reset transistor T9 is maintained in on state. By this, the potential at the first node N1 is initialized based on the low-level voltage. Specifically, the potential at the first node N1 sufficiently decreases, and accordingly, the gate-source voltage Vgs(T4) of the drive transistor T4 sufficiently decreases. Operation performed after time point t55 is the same as that performed after time point t35 in the second embodiment.
According to the present variant, the same effects as those in the second embodiment are obtained. In addition, since the first scanning signal lines NS are used instead of the reset control signal lines Voi in the second embodiment, a driver for driving the reset control signal lines Voi is unnecessary. Thus, narrowing of a picture-frame is easily achieved compared to the second embodiment.
All embodiments and all variants will be summarized. A configuration of a pixel circuit 20 in an nth row and an mth column is represented as shown in
In addition, for all embodiments and all variants, in the refresh frame period RF included in the driving period, the display control circuit 100 controls the display drive circuit (the gate driver 300, the emission driver 400, and the source driver 500) such that the initialization voltage is provided to the first node N1 by the reset circuit 22 after the off-voltage is provided to the first node N1 by the reset circuit 22, before a data voltage is provided to the first node N1 through the write control transistor T3, the drive transistor T4, and the threshold voltage compensation transistor T2.
In addition, for all embodiments and all variants, in a period, during which the first light-emission control transistor T5 and the second light-emission control transistor T6 are maintained in off state, in a refresh frame period RF included in a driving period, the gate driver 300 drives the (i+2) first scanning signal lines NS(−1) to NS(i) and the i second scanning signal lines PS(1) to PS(i) such that the threshold voltage compensation transistor T2 changes from on state to off state after a certain period has elapsed since the threshold voltage compensation transistor T2 changes from off state to on state and the write control transistor T3 is maintained in on state during at least a part of a period during which the threshold voltage compensation transistor T2 is maintained in on state.
For the first embodiment (including the variants), as shown in
In addition, for the first embodiment (including the variants), in the refresh frame period RF included in the driving period, the gate driver 300 drives the (i+2) first scanning signal lines NS(−1) to NS(i) such that the off-voltage application transistor T8 changes from off state to on state after the first light-emission control transistor T5 and the second light-emission control transistor T6 change from on state to off state; the second initialization transistor T7 changes from off state to on state after the off-voltage application transistor T8 changes from on state to off state; the threshold voltage compensation transistor T2 changes from off state to on state after the second initialization transistor T7 changes from on state to off state; and the threshold voltage compensation transistor T2 changes from on state to off state before the first light-emission control transistor T5 and the second light-emission control transistor T6 change from off state to on state.
For the first embodiment (see
For the first variant (see
In addition, for the first variant of the first embodiment, the gate driver 300 drives the (i+2) first scanning signal lines NS(−1) to NS(i) such that the off-voltage is provided to the first conductive terminal of the off-voltage application transistor T8 during a period during which the off-voltage application transistor T8 is maintained in on state.
For the second variant (see
For the second embodiment (including the variant), as shown in
For the second embodiment (excluding the variant), in the refresh frame period RF included in the driving period and the non-refresh frame period NRF included in the pause period, the emission driver 400 drives the i light-emission control lines EM(1) to EM(i) such that the first light-emission control transistor T5 and the second light-emission control transistor T6 change from off state to on state after a certain period has elapsed since the first light-emission control transistor T5 and the second light-emission control transistor T6 change from on state to off state. In addition, in the refresh frame period RF included in the driving period, the gate driver 300 drives the (i+2) first scanning signal lines NS(−1) to NS(i) such that the reset transistor T9 changes from off state to on state after the first light-emission control transistor T5 and the second light-emission control transistor T6 change from on state to off state; the threshold voltage compensation transistor T2 changes from off state to on state after the reset transistor T9 changes from on state to off state; and the threshold voltage compensation transistor T2 changes from on state to off state before the first light-emission control transistor T5 and the second light-emission control transistor T6 change from off state to on state. In addition, in the refresh frame period RF included in the driving period, the reset control signal line driver drives the i reset control signal lines Voi(1) to Voi(i) such that a voltage provided to the second conductive terminal of the reset transistor T9 changes from the first-level voltage to the second-level voltage after the first light-emission control transistor T5 and the second light-emission control transistor T6 change from on state to off state; and the voltage provided to the second conductive terminal of the reset transistor T9 changes from the second-level voltage to the first-level voltage during a period during which the reset transistor T9 is maintained in on state.
For the variant of the second embodiment, in the refresh frame period RF included in the driving period and the non-refresh frame period NRF included in the pause period, the emission driver 400 drives the i light-emission control lines EM(1) to EM(i) such that the first light-emission control transistor T5 and the second light-emission control transistor T6 change from off state to on state after a certain period has elapsed since the first light-emission control transistor T5 and the second light-emission control transistor T6 change from on state to off state. In addition, in the refresh frame period RF included in the driving period, the gate driver 300 drives the (i+2) first scanning signal lines NS(−1) to NS(i) such that the reset transistor T9 changes from off state to on state after the first light-emission control transistor T5 and the second light-emission control transistor T6 change from on state to off state; a voltage provided to the second conductive terminal of the reset transistor T9 changes from the second-level voltage to the first-level voltage during a period during which the reset transistor T9 is maintained in on state; the threshold voltage compensation transistor T2 changes from off state to on state after the reset transistor T9 changes from on state to off state; and the threshold voltage compensation transistor T2 changes from on state to off state before the first light-emission control transistor T5 and the second light-emission control transistor T6 change from off state to on state.
Although the above-described embodiments and variants make a description using an organic EL display device as an example, the display device is not limited thereto. The above-described content of disclosure can also be applied to inorganic EL display devices, QLED display devices, etc., as long as the display devices use display elements driven by current.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2022/019265 | 4/28/2022 | WO |
