Patent Grant
11798477
This application claims priority under 35 U.S.C. § 119(a) to Chinese Patent Application No. 202211049501.X, filed Aug. 30, 2022, the entire disclosure of which is incorporated herein by reference.
This disclosure relates to the field of display technology, and in particular, to a pixel circuit, a display panel including the pixel circuit, and a display apparatus including the display panel.
Due to advantages of active-matrix organic light-emitting diodes (AMOLEDs) such as wide color gamut, fast response, high contrast, good flexibility, and power saving, AMOLED-related products (such as AMOLED displays) have become more and more popular in recent years.
However, when the AMOLED display works for a long period of time, a threshold voltage may drift due to a temperature increase of thin film transistors (TFTs). In addition, the threshold voltage of the TFTs may also drift when a display panel works in an environment where the temperature varies. A threshold voltage drift caused by the above reasons will result in an uneven threshold voltage, which will lead to unstable display, uneven brightness, color shift, and the like in the display panel of the AMOLED display, thus affecting the overall image display effect.
In a first aspect, a pixel circuit is provided in the disclosure. The pixel circuit includes a light-emitting unit and a drive transistor. The light-emitting unit is electrically coupled with a second power supply voltage terminal. The drive transistor has a gate electrically coupled with a first reset sub-circuit, a switch sub-circuit, and an energy storage element, a source electrically coupled with a first power supply voltage terminal, and a drain electrically coupled with a light-emitting control sub-circuit. The drive transistor is configured to drive the light-emitting unit to emit light. The light-emitting control sub-circuit is electrically coupled with a light-emitting control signal terminal and the light-emitting unit, and is configured to control the light-emitting unit to emit light in response to a light-emitting control signal written at the light-emitting control signal terminal. The first reset sub-circuit is electrically coupled with a reference voltage terminal, a first reset signal terminal, the switch sub-circuit, and the energy storage element, and is configured to write a reference voltage written at the reference voltage terminal into the gate of the drive transistor and a first terminal of the energy storage element in respond to a first reset signal written at the first reset signal terminal. The switch sub-circuit is electrically coupled with a second reset sub-circuit and the energy storage element and configured to change a gate voltage of the drive transistor. The second reset sub-circuit is electrically coupled with the first reset signal terminal and configured to respond to the first reset signal. The energy storage element is electrically coupled with a third reset sub-circuit and a data writing sub-circuit and configured to change the gate voltage of the drive transistor. The third reset sub-circuit is electrically coupled with a second reset signal terminal and the data writing sub-circuit and configured to respond to a second reset signal written at the second reset signal terminal. The data writing sub-circuit is electrically coupled with a data voltage terminal and a scan signal terminal and configured to write a data voltage written at the data voltage terminal into a second terminal of the energy storage element in respond to a control data writing signal written at the scan signal terminal.
In a second aspect, a display panel is further provided in the disclosure. The display panel has an active area and an inactive area surrounding the active area. The display panel includes multiple pixel circuits provided in the first aspect.
In a third aspect, a display apparatus is further provided. The display apparatus includes a signal generating circuit and the display panel provided in the second aspect. The signal generating circuit is configured to provide the display panel with scan driving signals, data driving signals, and control signals.
To describe the technical solutions in the embodiments of the disclosure more clearly, the following briefly introduces the accompanying drawings required for describing the embodiments. Apparently, the accompanying drawings in the following description illustrate some embodiments of the disclosure. Those of ordinary skill in the art may also obtain other drawings based on these accompanying drawings without creative efforts.
For ease understanding of the disclosure, the disclosure is described more completely with reference to the accompanying drawings hereinafter. The accompanying drawings illustrate preferred embodiments of the disclosure. However, the disclosure can be implemented in various forms and is not limited to the embodiments described herein. Rather, these embodiments are provided for a more thorough and comprehensive understanding of the disclosure.
The following embodiments are described with reference to the accompanying drawings to exemplify particular embodiments that may be implemented by the disclosure. The serial numbers themselves, such as “first” and “second” are used herein to distinguish the objects described, and do not have any sequential or technical meaning. The terms “connection” and “coupling” in the disclosure include direct and indirect connections (couplings), unless otherwise specified. Directional terms such as “up”, “down”, “front”, “back”, “left”, “right”, “inside”, “outside”, “side”, and the like referred to herein which are only for directions with reference to the accompanying drawings. Therefore, the directional terms used herein are intended to better and more clearly illustrate and understand the disclosure, rather than explicitly or implicitly indicate that apparatus or components referred to herein must have a certain direction or be configured or operated in a certain direction and therefore cannot be understood as limitation on the disclosure.
It is noted that, in the description of the disclosure, terms “install”, “couple”, “connect”, and “interconnect” should be understood in a broad sense unless otherwise expressly specified and limited. For example, the terms “install”, “couple”, “connect”, and “interconnect” may refer to fixedly connect, detachably connect, or integrally connect, may refer to mechanically connect, and may refer to a directly connect, indirectly connect through an intermediate medium, or an intercommunicate interiors of two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the disclosure can be understood according to specific situations. It is noted that, the terms such as “first” and “second” in the specification, claims, and the accompanying drawings of the disclosure are used for distinguishing between different objects rather than describing a particular order.
In addition, terms such as “include”, “may include”, “contain”, or “may contain” used herein indicate the existence of the corresponding function, operation, element, etc. disclosed, and do not limit the other one or more further functions, operations, elements, etc. In addition, the term “include” or “contain” indicates the existence of the corresponding feature, number, step, operation, element, component, or combination thereof disclosed in the specification, without excluding the existence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, and is intended to cover non-exclusive inclusion. In addition, when describing the embodiments of the disclosure, the term “may” is used to denote “one or more embodiments of the disclosure”. Also, the term “exemplary” is intended to refer to examples or illustrations.
Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art of the disclosure. The terms used herein in the disclosure are for merely describing embodiments rather than intending to limit the disclosure.
In the embodiments of the disclosure, technical schemes of a pixel circuit, a display panel with the pixel circuit, and a display apparatus with the display panel are provided to solve uneven display brightness and unstable display of a display screen due to uneven light emission of a light-emitting element caused by a threshold voltage drift in a thin film transistor (TFT), which are elaborated in the following embodiments.
Refer to
It can be understood that the display panel 10 can be applied to an electronic device including personal digital assistant (PDA) and/or music player functions and so on, such as a mobile phone, a tablet computer, a wearable electronic device with wireless communication functions (for example, a smart watch, a smart bracelet), etc. The aforementioned electronic device may also be other electronic devices, such as a laptop computer having a touch-sensitive surface (for example, a touch panel). In some embodiments, the electronic device may have a communication function, that is, the electronic device may establish communication with a network through second generation mobile phone communication technical specifications (2G), third generation mobile phone communication technical specifications (3G), fourth generation mobile phone communication technical specifications (4G), fifth generation mobile phone communication specifications (5G), wireless local area network (W-LAN), or communication methods that may appear in the future, which is not further limited in the embodiments of the disclosure for the sake of simplicity.
In a first aspect, the pixel circuit 110 is provided. Further refer to
In an embodiment of the disclosure, the drive transistor 111 has a gate electrically coupled with the first reset sub-circuit 114, the switch sub-circuit 115, and the energy storage element 117, a source electrically coupled with a first power supply voltage terminal 101, and a drain electrically coupled with the light-emitting control sub-circuit 112, and the drive transistor 111 is configured to drive the light-emitting unit 113 to emit light. In an example, the first power supply voltage terminal 101 is configured to receive a first power supply voltage VDD.
The light-emitting control sub-circuit 112 is electrically coupled with the drain of the drive transistor 111, a light-emitting control signal terminal 102, and the light-emitting unit 113, and configured to control the light-emitting unit 113 to emit light in response to a light-emitting control signal written at the light-emitting control signal terminal 102.
The light-emitting unit 113 has a positive pole electrically coupled with the light-emitting control sub-circuit 112 and a negative pole electrically coupled with the second power supply voltage terminal 103. In an example, the second power supply voltage terminal 103 is configured to receive a second power supply voltage Vss.
The first reset sub-circuit 114 is electrically coupled with a reference voltage terminal 105, a first reset signal terminal 106, the gate of the drive transistor 111, the switch sub-circuit 115, and the energy storage element 117, and configured to write a reference voltage Vref written at the reference voltage terminal 105 into the gate of the drive transistor 111 and a first terminal of the energy storage element 117 in response to a first reset signal Scan2 written at the first reset signal terminal 106. In an example, the reference voltage Vref written at the reference voltage terminal 105 can be controlled externally, so as to change a voltage value of the reference voltage Vref. The voltage value of the reference voltage Vref can be adjusted to achieve an optimum voltage according to a situation of the display panel.
The switch sub-circuit 115 is electrically coupled with the gate of the drive transistor 111, the first reset sub-circuit 114, and the second reset sub-circuit 116, and the energy storage element 117 and configured to change a gate voltage of the drive transistor 111. In an example, the switch sub-circuit 115 and the drive transistor 111 are mirrored in the pixel circuit 110 and disposed adjacent to each other.
The second reset sub-circuit 116 is electrically coupled with the first reset signal terminal 106 and the switch sub-circuit 115, and configured to respond to the first reset signal Scan 2 written at the first reset signal terminal 106.
The energy storage element 117 is electrically coupled with the gate of the drive transistor 111, the first reset sub-circuit 114, a switch sub-circuit 115, a third reset sub-circuit 118, and a data writing sub-circuit 119, and configured to change the gate voltage of the drive transistor 111.
The third reset sub-circuit 118 is electrically coupled with a second reset signal terminal 107, the energy storage element 117, and the data writing sub-circuit 119, and configured to respond to a second reset signal Scan3 written at the second reset signal terminal 107.
The data writing sub-circuit 119 is electrically coupled with a data voltage terminal 108, a scan signal terminal 109, the third reset sub-circuit 118, and the energy storage element 117, and configured to write a data voltage Vdata written at the data voltage terminal 108 into a second terminal of the energy storage element 117 in response to a control data writing signal Scan1 written at the scan signal terminal 109.
The disclosure aims at providing the pixel circuit 110, which solves a problem of uneven display brightness and unstable display of a display screen due to uneven light emission of a light-emitting element caused by a threshold voltage drift in a thin film transistor (TFT).
Refer to
The first reset sub-circuit 114 includes a first reset transistor T4. The first reset transistor T4 has a control terminal configured to receive the first reset signal Scan2, a first terminal electrically coupled with the gate of the drive transistor 111, the switch sub-circuit 115, and the energy storage element 117, and a second terminal electrically coupled with the reference voltage terminal 105, and the first reset transistor T4 is configured to receive the reference voltage Vref written at the reference voltage terminal 105. In an embodiment of the disclosure, when the first reset signal Scan2 is a low-level signal, the first reset transistor T4 is switched on in response to the first reset signal Scan2, and the reference voltage Vref is written into the gate of the drive transistor 111 and the first terminal of the energy storage element 117 through the first reset transistor T4.
The switch sub-circuit 115 includes a first switch transistor T6. The first switch transistor T6 has a gate electrically coupled with the gate of the drive transistor 111 and a first terminal of the first reset transistor T4, a source electrically coupled with the gate of the drive transistor 111 and the energy storage element 117, and a drain electrically coupled with the second reset sub-circuit 116. In an embodiment of the disclosure, the first switch transistor T6 and the drive transistor 111 are manufactured through the same process, and thus a threshold voltage of the first switch transistor T6 is equal to that of the drive transistor 111.
The second reset sub-circuit 116 includes a second reset transistor T3. The second reset transistor T3 has a control terminal configured to receive the first reset signal Scan2, a second terminal which is grounded, and a first terminal electrically coupled with the drain of the first switch transistor T6. In an embodiment of the disclosure, when the first reset signal Scan2 is a low-level signal, the second reset transistor T3 is switched on in response to the first reset signal Scan2.
The energy storage element 117 includes a storage capacitor C1. The storage capacitor C1 has a first terminal electrically coupled with the gate of the drive transistor 111, the first terminal of the first reset transistor T4, and the source of the first switch transistor T6, and a second terminal electrically coupled with the third reset sub-circuit 118 and the data writing sub-circuit 119, and the storage capacitor is configured to change the gate voltage of the drive transistor 111.
The third reset sub-circuit 118 includes a third reset transistor T5. The third reset transistor T5 has a control terminal configured to receive the second reset signal Scan3, a second terminal which is grounded, and a first terminal electrically coupled with the second terminal of the storage capacitor C1 and the data writing sub-circuit 119. In an embodiment of the disclosure, when the second reset signal Scan3 is a low-level signal, the third reset transistor T5 is switched on in response to the second reset signal Scan3, and the second terminal of the energy storage element 117 is grounded through the third reset transistor T5.
The data writing sub-circuit 119 includes a second switch transistor T1. The second switch transistor T1 has a control terminal configured to receive the control data writing signal Scan1, a second terminal configured to receive the data voltage Vdata, and a first terminal electrically coupled with the second terminal of the storage capacitor C1 and the first terminal of the third reset transistor T5. In an embodiment of the disclosure, when the control data writing signal Scan1 is a low-level signal, the second switch transistor T1 is switched on in response to the control data writing signal Scan1, and the data voltage Vdata is written into the second terminal of the storage capacitor C1 through the second switch transistor T1.
The transistors illustrated in the embodiment in
The timing diagram corresponding to the pixel circuit 110 illustrated in
Specifically, “1” represents a high potential, and “0” represents a low potential. It is noted that “1” and “0” represent logic potentials, which are only to better explain specific operating processes of the embodiments of the disclosure, rather than potentials applied to gates of the transistors during specific implementing processes. In this embodiment, since all transistors are P-type transistors, the first terminal of the second switch transistor, the first terminal of the second reset transistor, the first terminal of the first reset transistor, the first terminal of the third reset transistor, and the first terminal of the light-emitting control transistor are all drains, the second terminal of the second switch transistor, the second terminal of the second reset transistor, the second terminal of the first reset transistor, the second terminal of the third reset transistor, and the second terminal of the light-emitting control transistor are all sources, the control terminal of the second switch transistor, the control terminal of the second reset transistor, the control terminal of the first reset transistor, the control terminal of the third reset transistor, and the control terminal of the light-emitting control transistor are gates, thus an effective signal is a low-level signal.
In period t1, the control data writing signal Scan1=1, the first reset signal Scan2=0, the second reset signal Scan3=0, and the light-emitting control signal Emit=1.
Specifically, when the first reset signal Scan2 and the second reset signal Scan3 are low-level signals and the control data writing signal Scan1 and the light-emitting control signal Emit are high-level signals, the second switch transistor T1 and the light-emitting control transistor T8 are switched off, and the second reset transistor T3, the first reset transistor T4, the third reset transistor T5, and the first switch transistor T6 are all switched on. The first reset transistor T4 is switched on, thus the reference voltage Vref written at the reference voltage terminal 105 is transmitted to the gate of the drive transistor 111 and the first terminal of the storage capacitor C1 through the first reset transistor T4, and thus a voltage value of the gate of the drive transistor 111 (i.e., point G illustrated in
In period t2, the control data writing signal Scan1=0, the first reset signal Scan2=1, the second reset signal Scan3=1, and the light-emitting control signal Emit=1.
Specifically, when the control data writing signal Scan1 is a low-level signal and the first reset signal Scan2, the second reset signal Scan3, and the light-emitting control signal Emit are all high-level signals, the second switch transistor T1 is switched on, and the second reset transistor T3, the first reset transistor T4, the third reset transistor T5, the first switch transistor T6, and the light-emitting control transistor T8 are all switched off. Thus, the second switch transistor T1 is switched on, and the data voltage Vdata written at the data voltage terminal 108 is transmitted to the second terminal of the storage capacitor C1 through the second switch transistor T1, thus the voltage value of the second terminal of the storage capacitor C1 (i.e., point A illustrated in
In period t3, the control data writing signal Scan1=1, the first reset signal Scan2=1, the second reset signal Scan3=0, and the light-emitting control signal Emit=1.
Specifically, when the second reset signal is a low-level signal, and the control data writing signal Scan1, the first reset signal Scan2, and the light-emitting control signal Emit are all high-level signals, the third reset transistor T5 is switched on and the drive transistor 111 is switched on. When the third reset transistor T5 is switched on, the second terminal of the storage capacitor C1 is grounded through the third reset transistor T5, thus the voltage value of the second terminal of the storage capacitor C1 (i.e., point A illustrated in
IL=k(Vgs−Vth)2=k(VGs+|Vth|)2=k(VDD−Vdata−|Vth2|+|Vthr|)2=k(VDD−Vdata)2 Expression (1)
Therefore, the drive current flowing through the light-emitting unit 113 is irrelevant to the threshold voltage Vth2 of the drive transistor 111, the threshold voltage Vth2 of the drive transistor 111 has no effect on the drive current of the light-emitting unit 113, and the drive current is in a stable state and is capable of driving the light-emitting unit 113 to emit light.
In period t4, the control data writing signal Scan1=1, the first reset signal Scan2=1, the second reset signal Scan3=1, and the light-emitting control signal Emit=0.
Specifically, when the light-emitting control signal Emit is a low-level signal and the control data writing signal Scan1, the first reset signal Scan2, and the second reset signal Scan3 are all high-level signals, the light-emitting control transistor T8 is switched on, and the second switch transistor T1, the second reset transistor T3, the first reset transistor T4, the third reset transistor T5, and the first switch transistor T6 are all switched off. Thus, the light-emitting control transistor T8 is switched on, and current is transmitted to the light-emitting unit 113 through the light-emitting control transistor T8, so that the light-emitting unit 113 emits light.
In conclusion, in the pixel circuit 110 provided in the embodiments of the disclosure, when the light-emitting unit 113 is driven to emit light by the drive transistor 111, a corresponding drive current flows through the light-emitting unit 113. A value of the corresponding drive current is related to the first power supply voltage VDD written at the first power supply voltage terminal 101 and the data voltage Vdata written at the data voltage terminal 108, but irrelevant to the threshold voltage of the drive transistor 111, as such, the drive current is prevented from being affected by the threshold voltage, a problem of uneven display brightness and unstable display caused by the threshold voltage in the pixel circuit is solved, thereby effectively improving overall brightness uniformity and stability of the display apparatus. At the same time, when the light-emitting unit 113 does not emit light, the light-emitting control transistor T8 can be controlled by the light-emitting control signal to achieve a full-black display. Moreover, the light-emitting unit 113 will be reset before emitting light and the reference voltage Vref will be written into the first reset sub-circuit 114, thus avoiding residual images of the light-emitting unit 113 due to different operating time.
The timing diagram corresponding to the pixel circuit 110 illustrated in
Specifically, “1” represents a high potential, and “0” represents a low potential. It is noted that “1” and “0” are logic potentials, which are only to better explain specific operating processes of the embodiments of the disclosure, rather than potentials applied to gates of the transistors during specific implementing processes. In this embodiment, since the drive transistor 111 and the first switch transistor T6 are both P-type transistors, the effective signal is a low-level signal. The second switch transistor T1, the second reset transistor T3, the first reset transistor T4, the third reset transistor T5, and the light-emitting control transistor T8 are all N-type transistors. In an example, the first terminal of the second switch transistor, the first terminal of the second reset transistor, the first terminal of the first reset transistor, the first terminal of the third reset transistor, and the first terminal of the light-emitting control transistor are all sources, the second terminal of the second switch transistor, the second terminal of the second reset transistor, the second terminal of the first reset transistor, the second terminal of the third reset transistor, and the second terminal of the light-emitting control transistor are all drains, the control terminal of the second switch transistor, the control terminal of the second reset transistor, the control terminal of the first reset transistor, the control terminal of the third reset transistor, and the control terminal of the light-emitting control transistor are gates, thus an effective signal is a high-level signal.
In period t1, the control data writing signal Scan1=0, the first reset signal Scan2=1, the second reset signal Scan3=1, and the light-emitting control signal Emit=0.
Specifically, when the control data writing signal Scan1 and the light-emitting control signal Emit are low-level signals and the first reset signal Scan2 and the second reset signal Scan3 are high-level signals, the second switch transistor T1 and the light-emitting control transistor T8 are switched off, and the second reset transistor T3, the first reset transistor T4, the third reset transistor T5, and the first switch transistor T6 are all switched on. As a result, the first reset transistor T4 is switched on, and the reference voltage Vref written at the reference voltage terminal 105 is transmitted to the gate of the drive transistor 111 and the first terminal of the storage capacitor C1 through the first reset transistor T4, and thus the gate of the drive transistor 111 (i.e., point G illustrated in
In period t2, the control data writing signal Scan1=1, the first reset signal Scan2=0, the second reset signal Scan3=0, and the light-emitting control signal Emit=0.
Specifically, when the first reset signal Scan2, the second reset signal Scan3 and the light-emitting control signal Emit are all low-level signals, and the control data writing signal Scan1 is a high-level signal, the second switch transistor T1 is switched on, and the second reset transistor T3, the first reset transistor T4, the third reset transistor T5, the first switch transistor T6, and the light-emitting control transistor T8 are all switched off. Thus, the second switch transistor T1 is switched on, and the data voltage Vdata written at the data voltage terminal 108 is transmitted to the second terminal of the storage capacitor C1 through the second switch transistor T1, thus the voltage value of the second terminal of the storage capacitor C1 (i.e., point A illustrated in
In period t3, the control data writing signal Scan1=0, the first reset signal Scan2=0, the second reset signal Scan3=1, and the light-emitting control signal Emit=0.
Specifically, when the control data writing signal Scan1, the first reset signal Scan2, and the light-emitting control signal Emit are all low-level signals and the second reset signal is a high-level signal, the third reset transistor T5 is switched on, the second terminal of the storage capacitor C1 is grounded through the third reset transistor T5, thus the voltage value of the second terminal of the storage capacitor C1 (i.e., point A illustrated in
IL=k(Vgs−Vth)2=k(VGs+|Vth|)2=k(VDD−Vdata−|Vth2|+|Vthr|)2=k(VDD−Vdata)2 Expression (1)
Therefore, the drive current flowing through the light-emitting unit 113 is unrelated to the threshold voltage Vth2 of the drive transistor 111, the threshold voltage Vth2 of the drive transistor 111 has no effect on the drive current of the light-emitting unit 113, and the drive current is in a stable state and is capable of driving the light-emitting unit 113 to emit light.
In period t4, the control data writing signal Scan1=0, the first reset signal Scan2=0, the second reset signal Scan3=0, and the light-emitting control signal Emit=1.
Specifically, when the control data writing signal Scan1, the first reset signal Scan2, and the second reset signal Scan3 are all low-level signals and the light-emitting control signal Emit is a high-level signal, the light-emitting control transistor T8 is switched on, and the second switch transistor T1, the second reset transistor T3, the first reset transistor T4, the third reset transistor T5, and the first switch transistor T6 are all switched off. Thus, the light-emitting control transistor T8 is switched on, and the light-emitting control transistor T8 transmits current to the light-emitting unit 113, so that the light-emitting unit 113 emits light.
In conclusion, in the pixel circuit 110 provided in the embodiments of the disclosure, when the light-emitting unit 113 is driven to emit light by the drive transistor 111, a corresponding drive current flows through the light-emitting unit 113. A value of the corresponding drive current is related to the first power supply voltage VDD written at the first power supply voltage terminal 101 and the data voltage Vdata written at the data voltage terminal 108, but unrelated to the threshold voltage of the drive transistor 111, as such, the drive current is prevented from being affected by the threshold voltage, a problem of uneven display brightness and unstable display caused by the threshold voltage in the pixel circuit is solved, thereby effectively improving overall brightness uniformity and stability of the display apparatus. At the same time, when the light-emitting unit 113 is not emitting light, the light-emitting control transistor T8 can be controlled by the light-emitting control signal to achieve a full-black display. Moreover, the light-emitting unit 113 will be reset before emitting light and the reference voltage Vref will be written into the first reset sub-circuit 114, thus avoiding residual images of the light-emitting unit 113 due to different operating time.
In a second aspect, a display panel 10 is provided. Refer to
In a third aspect, a display apparatus is further provided. The display apparatus includes a signal generating circuit and the above-mentioned display panel 10. The signal generating circuit is configured to provide the display panel with scan driving signals, data driving signals, and control signals.
In the display apparatus provided in the embodiments of the disclosure, when the light-emitting unit 113 is not emitting light, the light-emitting control transistor T8 can be controlled by the light-emitting control signal to achieve a full-black display.
In the embodiments of the disclosure, the display panel may be an active-matrix organic light-emitting diode (AMOLED) panel.
In the embodiments of the disclosure, the display apparatus may be any electronic device or component with a display function, such as a mobile phone, a tablet computer, a navigator, a display, etc., which is not specifically limited herein.
The flow chart described in the disclosure is only one embodiment, and there may be various modifications and variations to this explanatory chart or steps in the disclosure without departing from the spirit of the disclosure. For example, the steps may be performed in a different order, or certain steps may be added, deleted, or modified. Those skilled in the art can understand that all or part of flows for realizing the above embodiments, and equivalent variations made in accordance with the claims of the disclosure, still fall within the scope of the disclosure.
In the illustration of the disclosure, descriptions with reference to terms “one embodiment”, “some embodiments”, “examples”, “specific examples”, or “some examples” and the like mean that specific features, structures, materials, or characteristics described in combination with the embodiments or examples are included in at least one embodiment or example of the disclosure. The schematic expressions of the above terms herein do not necessarily refer to the same embodiment or example. Moreover, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
It is understood that the disclosure is not to be limited to the above-identified embodiments. Those of ordinary skill in the art can make improvements or changes based on the above description, and all these improvements and changes should fall within the protection scope of the appended claims of the disclosure. Those of ordinary skill in the art can understand that all or part of methods for realizing the above embodiments, and equivalent changes made in accordance with the claims of the disclosure, still fall within the scope covered by the disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202211049501.X | Aug 2022 | CN | national |
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