The present application claims priority to Chinese Patent Application No. 201811422764.4, filed on Nov. 27, 2018, the content of which is incorporated herein by reference in its entirety.
The present disclosure relates to the field of display technologies, and in particular, to a pixel circuit, a display panel and a display device.
In the display technologies, an Organic Light Emitting Diode (OLED) display is commonly regarded in the industry as a third-generation display technology after Liquid Crystal Display (LCD) due to its advantages such as lightness and thinness, autonomous light-emitting, fast response, wide viewing angle, rich color, high brightness, low power consumption, high temperature resistance and the like.
The existing OLED display mainly performs light-emitting under control of current, and its light uniformity is controlled by a corresponding current. When an actual product adopts the optimized a pixel circuit in the related art, non-uniform display problems such as an OLED light-emitting element being not dark in a dark state and being not bright in a bright state still occur.
The present disclosure provides a pixel circuit, a display panel and a display device, aiming to solve the non-uniform display problem and the screen crosstalk problem existing in the related art by providing a piezoresistor.
In an aspect, the present disclosure provides a pixel circuit, including: a first scan signal input terminal; a second scan signal input terminal; a data signal input terminal; a first power supply signal input terminal; a light-emitting control signal input terminal; a reference voltage input terminal; a first transistor, controlled by the light-emitting control signal input terminal and configured to transmit a first power supply signal from the first power supply signal input terminal; a second transistor, controlled by the second scan signal input terminal and configured to transmit a data signal from the data signal input terminal; a third transistor, configured to generate a driving current in accordance with the data signal transmitted by the second transistor; a fourth transistor, configured to detect and self-compensate for a threshold voltage deviation of the third transistor; a fifth transistor, controlled by the first scan signal input terminal, and connected to a reference voltage of the reference voltage input terminal; a sixth transistor, controlled by the light-emitting control signal input terminal, and transmitting the driving current generated by the third transistor; a first capacitor, configured to store the data signal transmitted to the third transistor; and a piezoresistor having a first electrode plate electrically connected to a first electrode of the first capacitor, and a second electrode electrically connected to a first electrode of the third transistor.
In another aspect, the present disclosure provides a display panel, including: a plurality of gate lines; a plurality of data lines; a plurality of reference voltage signal lines; a plurality of light-emitting signal control lines; a plurality of light-emitting elements, each including an anode, a light-emitting material, and a cathode; at least one first power supply signal line; at least one second power supply signal line; and a plurality of pixel circuits, each of the plurality of pixel circuits being the pixel circuit. The plurality of pixel circuits is arranged in N rows and M columns, and both N and M are positive integers greater than or equal to 2.
In still another aspect, the present disclosure provides a display device including the display panel described above.
In order to more clearly illustrate technical solutions in embodiments of the present disclosure or in the related art, the accompanying drawings used in the embodiments and in the related art are briefly introduced as follows. It should be noted that the drawings described as follows are merely part of the embodiments of the present disclosure, other drawings can also be acquired by those skilled in the art without paying creative efforts.
In order to clarify the purpose, technical solutions, and advantages of the embodiments of the present disclosure, the technical solutions in the embodiments of the present disclosure are described in the following with reference to the accompanying drawings. It should be understood that the described embodiments are merely exemplary embodiments of the present disclosure, which shall not be interpreted as providing limitations to the present disclosure. All other embodiments obtained by those skilled in the art without creative efforts according to the embodiments of the present disclosure are within the scope of the present disclosure.
The terms used in the embodiments of the present disclosure are merely for the purpose of describing particular embodiments but not intended to limit the present disclosure. Unless otherwise noted in the context, the singular form expressions “a”, “an”, “the” and “said” used in the embodiments and appended claims of the present disclosure are also intended to represent plural form expressions thereof.
It should be understood that the term “and/or” used herein is merely an association relationship describing associated objects, indicating that there may be three relationships, for example, A and/or B may indicate that three cases, i.e., A existing individually, A and B existing simultaneously, B existing individually. In addition, the character “/” herein generally indicates that the related objects before and after the character form an “or” relationship.
It should be understood that although a transistor, a power supply signal line, a metal layer and a semiconductor layer may be described using the terms of “first”, “second”, “third”, etc. in the embodiments of the present disclosure, the transistor, the power supply signal line, the metal layer and the semiconductor layer will not be limited to these terms.
These terms are merely used to distinguish transistors, power supply signal lines, metal layers and semiconductor layers from one another. For example, without departing from the scope of the embodiments of the present disclosure, a first transistor, a first power supply signal line, a first metal layer, and a first semiconductor layer may also be referred to as a second transistor, a second power supply signal line, a second metal layer and a second semiconductor layer, respectively, and similarly, a second transistor, a second power supply signal line, a second metal layer, and a second semiconductor layer may also be referred to as a first transistor, a first power supply signal line, a first metal layer and a first semiconductor, respectively.
An embodiment of the present disclosure provides a pixel circuit Pe. As shown in
The first transistor M1 is controlled by the light-emitting control signal input terminal Emit, and is configured to transmit a first power supply signal V1 from the first power supply signal input terminal PVDD. The second transistor M2 is controlled by the second scan signal input terminal S2, and is configured to transmit a data signal Vdata from the data signal input terminal VD. The third transistor M3 is configured to generate a driving current I according to the data signal Vdata transmitted by the second transistor M2. The fourth transistor M4 is configured to detect and self-compensate a threshold voltage deviation of the third transistor M3. The fifth transistor M5 is controlled by the first scan signal input terminal S1, and is connected to a reference voltage Vvref of the reference voltage input terminal VF. The sixth transistor M6 is controlled by the light-emitting control signal input terminal Emit, and is configured to transmit the driving current I generated by the third transistor M3. The first capacitor C1 is configured to store the data signal Vdata transmitted to the third transistor M3.
With further reference to
The pixel circuit Pe provided by this embodiment of the present disclosure is used to drive the third transistor (the transistor that generates the driving current I) and the sixth transistor (the transistor that provides a light-emitting current Ito a light-emitting element). In a circuit threshold detection phase, the data signal Vdata is written into the first electrode of the third transistor M3 until a Vgs of the third transistor M3 achieves a balance, at which a voltage at the first electrode of the third transistor M3 is equal to a difference between the data signal Vdata and a threshold voltage of the third transistor M3. Then, in a light-emitting phase, the third transistor M3 functions as a current source, and drives the light-emitting element to emit light through the sixth transistor M6.
It can be seen from the driving process of the pixel circuit Pe provided by this embodiment of the present disclosure that stability of a potential at the gate electrode of the third transistor M3 is related to the display effect. In the pixel circuit Pe provided by this embodiment of the present disclosure, the piezoresistor RV is arranged between the first electrode of the third transistor M3 and the first electrode plate of the first capacitor C1, so that the potential at the gate electrode of the third transistor M3 can be stabilized. On the one hand, when the voltage at the piezoresistor RV is lower than the threshold voltage of the piezoresistor RV, the current flowing through the piezoresistor RV is extremely small, and the piezoresistor RV is equivalent to a resistor having an infinitely-large resistance. That is, when the voltage applied on the piezoresistor RV is lower than the threshold voltage of the piezoresistor RV, the piezoresistor RV disconnects the first electrode of the third transistor M3 from the gate electrode of the third transistor M3, thereby avoiding current leakage. On the other hand, when the voltage applied on the piezoresistor RV exceeds the threshold voltage of the piezoresistor RV, the current flowing through the piezoresistor RV increases sharply, and the piezoresistor RV is equivalent to a resistor having an infinitely-small resistance. That is, when the voltage applied on the piezoresistor RV is higher than its threshold voltage, the piezoresistor RV is equivalent to a switch in a closed state. Thus, the piezoresistor RV can clamp the potential at the gate electrode of the third transistor M3 to a relatively fixed voltage value, thereby solving the non-uniform display problem.
Further, the threshold voltage of the piezoresistor RV may be equal to the threshold voltage of the third transistor M3.
An embodiment of the present disclosure further provides a pixel circuit Pe. As shown in
An embodiment of the present disclosure further provides a pixel circuit Pe, as shown in
An embodiment of the present disclosure further provides a pixel circuit Pe. As shown in
An embodiment of the present disclosure further provides a pixel circuit Pe. As shown in
An embodiment of the present disclosure further provides a pixel circuit Pe. As shown in
It should be noted that the first transistor M1, all of the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 shown in
When the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are all P-type transistors, the reference voltage Vvref is a low potential signal. When the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are all N-type transistors, the reference voltage Vvref is a high potential signal.
In the pixel circuit Pe provided by this embodiment of the present disclosure, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 is of a same type, so that the process for manufacturing the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 can be simplified, thereby improving the manufacturing efficiency.
An embodiment of the present disclosure further provides a display panel 100. As shown in
As shown in
The plurality of pixel circuit Pe can be any type of the pixel circuits shown in
For the display panel 100 provided by this embodiment of the present disclosure, the piezoresistor RV is arranged in the pixel circuit Pe. Thus, in a light-emitting phase of the pixel circuit Pe, the first electrode of the third transistor M3 can be controlled at a high voltage and may not be influenced at a low voltage. In this way, the voltage at the first electrode of the third transistor M3 can be stabilized. As a result, the non-uniform display problems in the related art such as an OLED light-emitting element being not dark in a dark state and being not bright in a bright state can be solved, thereby improving the display effect.
Further, with reference to
Further, with reference to
Further, with reference to
The second scan signal input terminal of the pixel circuit arranged in the nth row is electrically connected to the scan line of the (n-1)th row.
The light-emitting control signal input terminal of the pixel circuit arranged in the nth row is electrically connected to the light-emitting control signal line of the nth row.
Further, with reference to
For one pixel circuit Pe, signals from the first scan signal input terminal S1, the second scan signal input terminal S2, and the light-emitting control signal input terminal Emit are as shown in
With reference to
With further reference to
With reference to
In the above three phases, the light-emitting phase takes up the main part of time. In the light-emitting phase, the piezoresistor RV functions as voltage limiting, thereby limiting the current output from the pixel circuit Pe to the light-emitting element, thereby solving the non-uniform display problem.
For the display panel 100 provided by this embodiment of the present disclosure, the pixel circuits Pe are arranged in a matrix with N rows and M columns, and match up with the matrix arrangement of m rows of the gate lines GATE and m rows of the data lines DATA, the reference voltage signal line VREF, the light-emitting signal control line EM, the first power supply signal line VDD and the second power supply signal line VSS,. In this way, the display effect of each pixel point of the display panel 100 can be optimized, thereby solving the non-uniform display problem and thus improving the display effect of the display panel 100.
Embodiments of the present disclosure also provide layered structures of various display panels 100 and various manners of arranging the piezoresistor RV.
An embodiment of the present disclosure provides a display panel 100. As shown in
With reference to
Further, the first semiconductor layer 21 is made of a low temperature poly-silicon. The second semiconductor layer 22 is a made of a metal oxide, such as an II-VI group oxide semiconductor (such as zinc oxide ZnO), and the second semiconductor layer 22 includes a divalent element zinc (Zn) and a hexavalent elemental oxygen (O).
In other embodiments of the present disclosure, the semiconductor portion of the piezoresistor RV may also be arranged at other positions. As shown in
The second semiconductor layer 22 includes indium zinc oxide (IZO), and may also include In2O3, Ga2O3, or ZnO.
An embodiment of the present disclosure further provides a display panel 100. As shown in
Further, the second semiconductor layer 22 includes indium zinc oxide, and may also include In2O3, Ga2O3, or ZnO. The third semiconductor layer 23 is a metal oxide. The third semiconductor layer 23 and the second semiconductor layer 22 are made of different materials.
For the display panel 100 provided by this embodiment of the present disclosure, various feasible solutions are provided for arranging the piezoresistor RV in different layers of the display panel 100 on the premise of arranging the first electrode plate of the first capacitor C1 in the first semiconductor layer 21. In combination with the existing manufacturing process of the display panel, the piezoresistor RV is arranged in the pixel circuit, so that the non-uniform display problem can be solved.
An embodiment of the present disclosure further provides a display panel 100. As shown in
With further reference to
Further, the first semiconductor layer 21 is made of a low temperature poly-silicon. The second semiconductor layer 22 is made of a metal oxide, such as an II-VI group oxide semiconductor (such as zinc oxide ZnO), and the second semiconductor layer 22 includes a divalent element zinc (Zn) and a hexavalent elemental oxygen (O).
In other embodiments of the present disclosure, the semiconductor portion of the piezoresistor RV may also be arranged at other positions. As shown in
An embodiment of the present disclosure further provides a display panel 100. As shown in
Further, the second semiconductor layer 22 includes indium zinc oxide (IZO), and may also include In2O3, Ga2O3, or ZnO. The third semiconductor layer 23 is a metal oxide.
The third semiconductor layer 23 and the second semiconductor layer 22 may be made different materials.
For the display panel 100 provided by this embodiment of the present disclosure, various feasible solutions are provided for arranging the piezoresistor RV in different layers of the display panel 100 on the premise of arranging the first electrode plate of the first capacitor
Cl in the capacitor metal layer 3C. In combination with the existing manufacturing process of the display panel, the piezoresistor RV is arranged in the pixel circuit, so that the non-uniform display problem can be solved.
An embodiment of the present disclosure further provides a display device 500. As shown in
It should be noted that
For the display device 500 provided by this embodiment of the present disclosure, the piezoresistor RV is arranged in the pixel circuit Pe. Thus, in a light-emitting phase of the pixel circuit Pe, the first electrode of the third transistor M3 can be controlled at a high voltage and may not be influenced at a low voltage. In this way, the voltage of the first electrode of the third transistor M3 can be stabilized. As a result, the non-uniform display problems in the related art such as a display panel being not dark in a dark state and being not bright in a bright state can be solved, thereby improving the display effect.
The device embodiments described above are merely illustrative, the units illustrated as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, i.e., they may be located in one place, or may be distributed to at least two network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the embodiment. Those skilled in the art can understand and implement without paying creative efforts.
Finally, it should be noted that the above-described embodiments are merely for illustrating the present disclosure but not intended to provide any limitation. Although the present disclosure has been described in detail with reference to the above-described embodiments, it should be understood by those skilled in the art that it is still possible to modify the technical solutions described in the above embodiments or to equivalently replace some or all of the technical features therein, but these modifications or replacements do not cause the essence of corresponding technical solutions to depart from the scope of the present disclosure.
Number | Date | Country | Kind |
---|---|---|---|
2018 1 1422764 | Nov 2018 | CN | national |
Number | Name | Date | Kind |
---|---|---|---|
20120001893 | Jeong | Jan 2012 | A1 |
20120001896 | Han | Jan 2012 | A1 |
20130002632 | Choi | Jan 2013 | A1 |
20130201172 | Jeong | Aug 2013 | A1 |
20140027719 | Kim | Jan 2014 | A1 |
20150170576 | Bae | Jun 2015 | A1 |
20150187270 | Lee | Jul 2015 | A1 |
20170110048 | Kim | Apr 2017 | A1 |
20170316740 | Yang | Nov 2017 | A1 |
Number | Date | Country |
---|---|---|
1725273 | Jan 2006 | CN |
103903564 | Jul 2014 | CN |
107154239 | Sep 2017 | CN |
Entry |
---|
Chinese Office Action dated Dec. 11, 2019 for corresponding CN Patent Application No. 201811422764.4. |
Number | Date | Country | |
---|---|---|---|
20200168155 A1 | May 2020 | US |