The present application claims priority to Japanese Priority Patent Application JP 2010-039782 filed in the Japan Patent Office on Feb. 25, 2010, the entire contents of which are hereby incorporated by reference.
The present application relates to a pixel circuit, a liquid-crystal device including the pixel circuit, and an electronic device including the liquid-crystal device.
Medium-sized and small-sized displays typified by a liquid-crystal display device are applied to many portable electronic devices (such as a mobile phone, a digital still camera, a digital video camera, a digital picture frame, and an electronic paper) due to their portability. Portable electronic devices are commonly driven by batteries, so that less power consumption of a display used in the portable electronic devices is demanded from the viewpoint of securement of operating time.
A liquid-crystal display device includes a plurality of pixels which are arranged in matrix. An image is displayed by writing a voltage corresponding to gradation which is to be displayed in each of the plurality of pixels and controlling transmittance of liquid crystal depending on the written voltage.
In order to reduce power consumption of a display, such a method that a driving frequency of pixels is lowered can be considered. However, if a driving frequency is lowered, an interval for writing a voltage in pixels is increased. Charges accumulated in a liquid-crystal capacitor are reduced with time due to leak current and therefore a potential of the pixels is lowered. Therefore, image quality of a display is deteriorated when the writing interval is increased. Accordingly, in order to lower a driving frequency and maintain image quality of a display, it is necessary to suppress leak current and maintain a voltage which is applied to liquid crystal.
Japanese Unexamined Patent Application Publication No. 10-111491 discloses a pixel circuit which suppresses leak current. This pixel circuit is configured such that two transistors are connected in series between a data line and a pixel electrode (liquid crystal) and a holding capacitor is connected to a node of the two transistors. Gates of the two transistors are connected to one scanning line. Accordingly, when a scanning signal is supplied to the scanning line during a writing period, the two transistors are turned on and a same voltage is written in the holding capacitor and a pixel capacitor of the liquid crystal. Subsequently, the two transistors are turned off. Here, the transistor which is connected to the data line is referred to as a first transistor, and the transistor which is connected to the pixel electrode (liquid crystal) is referred to as a second transistor. A level of leak current is increased when a voltage between a source and a drain is increased. However, the same voltage is written in the holding capacitor and the pixel capacitor, so that leak current of the second transistor can be suppressed.
However, in the related art pixel circuit, the holding capacitor may have a size enough to suppress the leak current of the second transistor. Thus, the holding capacitor and the pixel capacitor are not particularly optimized. Accordingly, the related art pixel circuit has such a problem that variation of a voltage applied to the pixel capacitor is not adequately suppressed.
It is preferable to provide a pixel circuit, a liquid-crystal device including the pixel circuit, and an electronic device including the liquid-crystal device. The pixel circuit includes an auxiliary capacitor, which has a layered structure for increasing capacitance per unit area, and is capable of minimizing variation of a potential applied to a liquid-crystal element by changing a ratio between capacitance values of the auxiliary capacitor and a holding capacitor and thus minimizing a leak current amount.
According to an, there is provided a pixel circuit that is connected with a scanning line and a data line and includes a first transistor of which a gate electrode is connected with the scanning line and one of a source electrode and a drain electrode is connected with the data line, a second transistor of which a gate electrode is connected with the scanning line, one of a source electrode and a drain electrode is connected with the first transistor, and the other one of the source electrode and the drain electrode is connected with a first node, an auxiliary capacitor that is connected with a node at which the first transistor and the second transistor are connected to each other, a pixel electrode that is connected with the first node, a counter electrode that is opposed to the pixel electrode, liquid crystal that is held between the pixel electrode and the counter electrode, and a holding capacitor that is connected with the first node. In the pixel circuit, a ratio between a capacitance value of the auxiliary capacitor and a capacitance value of the holding capacitor is set so as to minimize a change amount of a potential of the first node when the first transistor and the second transistor are turned off.
According to the, the ratio between the capacitance value of the auxiliary capacitor and the capacitance value of the holding capacitor is set so as to minimize the change amount of the potential of the first node when the first transistor and the second transistor are turned off. Even when the first transistor and the second transistor are in an off state, leak current corresponding to a voltage between the drain and the source of the transistors flows in the first transistor and the second transistor. The voltage applied between the drain and the source of the transistors varies depending on a capacitance value of a capacitor which is connected to the transistors. According to the embodiment, the ratio between the capacitance value of the auxiliary capacitor that is connected with the node at which the first transistor and the second transistor are connected to each other and the capacitance value of the holding capacitor that is connected with the first node to which the second transistor is connected is set so as to minimize the change amount of the potential of the first node. Accordingly, accuracy of displayed gradation can be improved.
Here, it is preferable that the ratio between the capacitance value of the auxiliary capacitor and the capacitance value of the holding capacitor be set such that the change amount of the potential of the first node can be minimized by minimizing a total leak current amount of an amount of leak current, which decreases as the capacitance value of the auxiliary capacitor increases, of the first transistor and the second transistor and an amount of leak current that is generated between the pixel electrode and the counter electrode and decreases as the capacitance value of the holding capacitor increases. In this case, the total leak current amount is minimized based on the amount of leak current, which decreases as the capacitance value of the auxiliary capacitor increases, of the first transistor and the second transistor and the amount of leak current that is generated between the pixel electrode and the counter electrode and decreases as the capacitance value of the holding capacitor increases. Therefore, the ratio between the capacitance value of the auxiliary capacitor and the capacitance value of the holding capacitor can be more efficiently set and accordingly, the change amount of the potential of the first node can be more efficiently minimized.
Further, it is preferable that N (N is an integer number of 3 or more) pieces of transistors be connected in series between the data line and the first node instead of the first transistor and the second transistor, a gate electrode of the N pieces of transistors be connected with the scanning line, one electrode of N−1 pieces of auxiliary capacitors, instead of the auxiliary capacitor, be connected to each of a plurality of nodes at which the N pieces of transistors are connected to each other, and a ratio between each capacitance value of the N−1 pieces of auxiliary capacitors and the capacitance value of the holding capacitor be set so as to minimize the change amount of the potential of the first node when the N pieces of transistors are turned off. In this case, the transistors are connected in multiple stages, so that the magnitude of leak current of the transistor that is connected to the first node can be further reduced.
It is preferable that the auxiliary capacitor include one electrode that is connected with the pixel electrode and other electrodes that are disposed on an upper layer side and a lower layer side of the one electrode with dielectrics interposed respectively. In this case, the capacitance value of the auxiliary capacitor per unit area can be increased by the layered structure of the electrode. Thus, the capacitance value of the auxiliary capacitor can be varied more flexibly, whereby the ratio between the capacitance value of the auxiliary capacitor and the capacitance value of the holding capacitor can be set adequately. It is preferable that the liquid crystal be memory-type liquid crystal. In this case, an image can be maintained for a longer period of time than a case where common liquid crystal is used. It is preferable that a signal supplied from the data line to the pixel circuit be a binary signal that is on either one level between two levels. In this case, a kind of a signal that drives the data line may be a binary signal. Therefore, a driving method is simpler than a case where a binary or more signal is used, and the driving circuit can be simplified.
A liquid-crystal device according to another embodiment includes a plurality of scanning lines, a plurality of data lines, a plurality of pixel circuits that are provided in a manner to correspond to intersections of the scanning lines and the data lines, and a driving circuit configured to drive the plurality of pixel circuits. In the liquid-crystal device, each of the plurality of pixel circuits is the pixel circuit described in the above embodiment. An electronic device according to still another embodiment includes the liquid-crystal device described in the above embodiment.
Additional features and advantages are described herein, and will be apparent from the following Detailed Description and the figures.
Embodiments of the present application will be described below in detail with reference to the drawings.
The scanning line driving circuit 100 generates scanning signals Y1, Y2, Y3, . . . , Ym for sequentially selecting the plurality of scanning lines 102.
The data line driving circuit 200 supplies data signals X1, X2, X3, . . . , Xn respectively to the pixel circuits 400A which are positioned on the selected scanning lines 102. In this example, the data signals X1 to Xn are supplied as voltage signals instructing gradation luminance.
The control circuit 700 generates various control signals and outputs the signals to the scanning line driving circuit 100 and the data line driving circuit 200. Further, the control circuit 700 generates gradation data D to which image processing such as gamma compensation is executed and outputs the gradation data D to the data line driving circuit 200. Though the control circuit 700 is provided outside the electrooptic panel AA in this example, a part or the whole of these constituent elements may be taken in the electrooptic panel AA. Further, a part of the constituent elements provided on the electrooptic panel AA may be provided as an external circuit.
While one end of the auxiliary capacitor Cs is connected to the drain electrode of the TFT 401 and the source electrode of the TFT 402, the other end of the auxiliary capacitor Cs is connected to a counter electrode (not shown) via a node q. The liquid-crystal element 410 is composed of a pixel electrode 411, a counter electrode 412, and liquid crystal Clc which is held between the pixel electrode 411 and the counter electrode 412. Here, the counter electrode 412 is common in other pixel circuits 400A, and a common potential Vcom is supplied to the counter electrode 412.
While one ends of the liquid-crystal element 410 and the holding capacitor Ch are respectively connected to the drain electrode of the TFT 402, the other ends of the liquid-crystal element 410 and the holding capacitor Ch are connected to a counter electrode (not shown) via the node q.
The liquid crystal Clc may be memory-type liquid crystal. The memory-type liquid crystal is stable in both of a light transmitting state and a no-light transmitting state, that is, the memory-type liquid crystal has a bistable property. Liquid crystal is categorized into “nematic liquid crystal”, “cholesteric liquid crystal”, and “smectic liquid crystal” depending on a molecular arrangement. Any type of these includes liquid crystal having an excellent holding characteristic. For example, a product manufactured by using “cholesteric liquid crystal” and a product manufactured by using a kind of smectic liquid crystal which is ferroelectric liquid crystal (FLC) and has liquid crystal molecules having a spiral structure are common. By using memory-type liquid crystal for the liquid crystal Clc, an image can be maintained for a longer period of time than a case where common liquid crystal is used.
When a gate-source voltage (Vgs) varies from a negative value to a positive value and exceeds a threshold voltage, drain-source current (Ids) sharply rises. Further, as the drain-source voltage (Vds) decreases, the drain-source current (Ids) also decreases. However, even when the gate-source voltage (Vgs) becomes equal to or less than the threshold voltage to have a negative value, the drain-source current (Ids) flows. This means that leak current flows in an actual circuit even in an off state of the TFT.
In such the pixel circuit 400A, it is assumed that a voltage on the node p and the node o is 30 V and a voltage on the node m is 10 V at time when writing of a voltage, which corresponds to a gradation, to the pixel circuit 400A is finished. In this case, since the voltage between the node m and the node o is 20 V, the drain-source voltage Vds of the TFT 401 is 20 V and the leak current Ileak1 flows (refer to
On the other hand, since a voltage between the node o and the node p is 0 V, the leak current Ileak2 does not flow in the TFT 402. The voltage on the node o gradually becomes closer to the voltage on the node m. Here, when the change amount of the voltage on the node o is denoted as ΔV, ΔV=Ileak1×ΔT(holding time)/Csc1 can be expressed. For example, when a driving frequency is 4 Hz and Csc1=200 fF, the change amount becomes about 2 V. Accordingly, a final voltage on the node o becomes about 28 V. Thus, leak current Ileak2 of the TFT 402 can be suppressed by lowering the voltage between the node o and the node p. As a result, a driving frequency can be lowered, whereby power consumption can be lowered.
Next, a relationship among a driving frequency, a ratio between capacitance values of the auxiliary capacitor Cs and the holding capacitor Ch, and leak current of the pixel circuit 400A used in the embodiment is described in reference to
As shown in
As described above, the sum S of the capacitance values of the auxiliary capacitor Cs and the holding capacitor Ch is constant. Therefore, when the capacitance value of the auxiliary capacitor Cs is increased, the capacitance value of the holding capacitor Ch falls, and when the capacitance value of the holding capacitor Ch is increased, the capacitance value of the auxiliary capacitor Cs falls. That is, the capacitance value of the holding capacitor Ch and the capacitance value of the auxiliary capacitor Cs are in a trade-off relationship.
Further, as shown in
As described above, potential variation caused by generation of leak current can be controlled by varying the ratio between the capacitance values of the auxiliary capacitor Cs and the holding capacitor Ch under a certain driving frequency even in a state that the capacitance value of the whole circuit is constant. Namely, by varying the capacitance values of the auxiliary capacitor Cs and the holding capacitor Ch and thus striking a balance between a leak current amount of the TFT and a leak current amount of the liquid-crystal element under a certain driving frequency, the potential variation ΔVp which influences a potential applied to the liquid-crystal element can be controlled and, for example, the potential variation ΔVp can be minimized.
The configuration of the auxiliary capacitor used in the embodiment is next described.
It is common that integration of a pixel circuit used in a display is demanded, so that an area which can be used for the pixel circuit is limited. Therefore, it is difficult to enlarge an area of the auxiliary capacitor included in the pixel circuit and to vary the capacitance value so as to vary the ratio between the capacitance values of the auxiliary capacitor Cs and the holding capacitor Ch described above. Accordingly, it is demanded to increase the capacitance value while suppressing the area of the auxiliary capacitor.
That is, though a common auxiliary capacitor is composed of a single source wiring metal layer, a single insulation layer, and a single gate wiring metal layer, the auxiliary capacitor used in this embodiment has a layered structure in which the insulation layers 520 and 540 are respectively provided on the both sides sandwiching the gate wiring metal layer 530 and the source wiring metal layers 510 and 550 are also respectively provided on the both sides sandwiching the gate wiring metal layer 530 so as to increase a capacitance per unit area. By structuring as this, the capacitance per unit area can be approximately doubled.
By using such the auxiliary capacitor, the capacitance value of the auxiliary capacitor can be varied and the ratio between the capacitance value of the holding capacitor Ch and the capacitance value of the auxiliary capacitor Cs can be varied without increasing the size of the pixel circuit.
The pixel circuit 400A includes two TFTs in the embodiment described above. However, the embodiment is not limited to this but can be applied to a pixel circuit including three or more TFTs.
While one end of the auxiliary capacitor Cs3 is connected to the drain electrode of the TFT 401 and the source electrode of the TFT 402, the other end of the auxiliary capacitor Cs3 is connected to a counter electrode (not shown). While one end of the auxiliary capacitor Cs4 is connected to the drain electrode of the TFT 402 and the source electrode of the TFT 403, the other end of the auxiliary capacitor Cs4 is connected to a counter electrode (not shown). While one ends of the liquid-crystal element 410 and the holding capacitor Ch are respectively connected to the drain electrode of the TFT 403, the other ends of the counter electrode 412 of the liquid-crystal element 410 and the holding capacitor Ch are connected to a counter electrode (not shown). From the counter electrode, a common potential Vcom is supplied.
Operation of the pixel circuit 400B configured in a three-divided fashion and shown in
As described above, when the driving frequency is lowered, an interval for writing a voltage in the pixel circuit is increased. Electric charges accumulated in a liquid-crystal capacitor are reduced with time due to leak current and therefore a potential of a pixel is lowered. Therefore, image quality of a display is deteriorated when the writing interval is increased. Namely, a driving frequency for maintaining a certain level of image quality of the display rises as leak current is easily generated. Since leak current is easily generated in the pixel circuit having no division, a drive-enabling frequency has a high value, namely, 30 Hz. Since leak current is further suppressed in the two-divided pixel circuit than the pixel circuit having no division, the two-divided pixel circuit can be driven by a lower frequency, namely, 4 Hz. Since leak current is furthermore suppressed in the three-divided pixel circuit than the two-divided pixel circuit, the three-divided pixel circuit can be driven by a further lower frequency, namely, 3 Hz. Thus, even though the capacitance value of the whole pixel circuit is constant, a drive-enabling frequency can be suppressed low by increasing a division number of the pixel circuit, and accordingly, the power consumption can be reduced.
Electronic devices to which the electrooptic device 1 according to the above-described embodiment is applied are next described.
Examples of electronic devices to which the electrooptic device 1 is applied include a digital still camera, a digital picture frame, an electronic paper, a liquid-crystal television, viewfinder-type and monitor direct-view-type videotape recorders, a monitor direct-view-type digital video camera, a car navigation device, a pager, an electronic diary, a calculator, a word processor, a workstation, a videophone, a POS terminal, and devices including a touch panel as well as the devices shown in
It should be understood that various changes and modifications to the presently preferred embodiments described herein will be apparent to those skilled in the art. Such changes and modifications can be made without departing from the spirit and scope and without diminishing its intended advantages. It is therefore intended that such changes and modifications be covered by the appended claims.
Number | Date | Country | Kind |
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P2010-039782 | Feb 2010 | JP | national |