The present invention relates to a pixel circuit of a display panel, and more particularly, to the structure of a pixel circuit of a display panel capable of canceling the offset of threshold voltages.
Among those next-generation display technologies, the micro organic light emitting diode (micro-OLED) panel has become important in recent years. Unlike conventional LED or OLED panels with their screens being built on a glass substrate, the screen of a micro-OLED panel is directly mounted to a silicon wafer. The silicon-based implementation could achieve a wide variety of benefits such as small size, light weight, low power consumption, high luminous efficiency, high contrast and high pixel density. With the above advantages, the micro-OLED panel is particularly suitable for augmented reality (AR) and virtual reality (VR) applications.
However, in the silicon-based implementation, the data voltages for controlling the driving transistors in the pixels fall within an operational range about 200 mV-300 mV, which is far smaller than the operational range of the data voltages in the thin-film transistor (TFT)-based implementation under the same pixel structure. This is because the device mobility of the transistors in the silicon-based implementation is higher, which means that the voltage swing range required for generating the same driving current becomes smaller. The smaller voltage swing range requires a much finer resolution to achieve the same grayscale and gamma level, which is accompanied by higher design difficulty and more circuit costs. For example, in an application with 256 grayscales, one step voltage may be about 1 mV for each gray level if the operational voltage range is between 200 mV and 300 mV, which easily generates an error on the data voltage due to non-ideal grayscale-to-voltage mapping. Thus, there is a need for improvement over the prior art.
It is therefore an objective of the present invention to provide a novel pixel circuit for an organic light emitting diode (OLED) panel, especially a micro-OLED panel, so as to solve the abovementioned problems.
An embodiment of the present invention discloses a pixel circuit of a display panel, which comprises a driving transistor, a first capacitor, a second capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a light emitting device. The driving transistor comprises a first terminal, a second terminal and a gate terminal. The first capacitor is coupled to the gate terminal of the driving transistor. The second capacitor is connected to the first terminal of the driving transistor. The first transistor is coupled to the second terminal of the driving transistor. The second transistor is coupled to the second capacitor. The third transistor is coupled between the first terminal of the driving transistor and the gate terminal of the driving transistor. The fourth transistor is coupled to the first terminal of the driving transistor. The fifth transistor is coupled to the driving transistor. The light emitting device is coupled to the fourth transistor.
Another embodiment of the present invention discloses a pixel circuit of a display panel, which comprises a driving transistor, a first capacitor, a second capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a light emitting device. The driving transistor comprises a first terminal, a second terminal and a gate terminal. The first capacitor is coupled to the gate terminal of the driving transistor. The second capacitor is connected to the first terminal of the driving transistor. The first transistor is coupled to the first terminal of the driving transistor. The second transistor is coupled to the second capacitor. The third transistor is coupled between the first terminal of the driving transistor and the gate terminal of the driving transistor. The fourth transistor is coupled to the second terminal of the driving transistor. The fifth transistor is coupled to the first capacitor and the fourth transistor. The light emitting device is coupled to the fourth transistor.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
The display panel 100 may perform display operations by receiving control signals from the gate driver 104 and receiving display data voltages from the source driver 102 based on a control timing determined by the timing controller 106. As shown in
The source driver 102 (or called data driver) is configured to output data voltages to the target pixels on the display panel 100 through the data lines. The source driver 102 may receive grayscale data from the timing controller 106 and correspondingly generate the data voltages based on the gamma voltages selected from the gamma control circuit 108. The source driver 102 may include a plurality of channels each coupled to one or more columns of pixels on the display panel 100, depending on whether the demultiplexer control is applied. Each channel may be composed of a shift register, latch circuit, digital-to-analog converter (DAC) and/or output buffer, but not limited thereto.
The gate driver 104 (or called scan driver) is configured to output gate control signals and emission control signals to the target pixels on the display panel 100 through the gate lines. In an embodiment, the gate driver 104 may be in the form of a gate on array (GOA) circuit which is deployed on the substrate of the display panel 100. The GOA circuit may generate the gate control signals and emission control signals by receiving gate/emission control clocks and gate/emission start pulses from the timing controller 106.
The timing controller 106 is configured to control the timing associated with the operations of the source driver 102 and the gate driver 104. In an embodiment, the timing controller 106 may receive display grayscale data from a front-end video source, perform necessary video processing on the grayscale data, and then send the grayscale data to the source driver 102. In an embodiment, the timing controller 106 along with the source driver 102 (and/or the gate driver 104) may be implemented in an integrated circuit (IC) to realize a display driver IC (DDIC).
The gamma control circuit 108 may include one or more resistor strings for generating a plurality of gamma voltages to be selected by the source driver 102 based on the values of the grayscale data. The gamma control circuit 108 may be integrated with the timing controller 106 and/or the source driver 102, or may include a stand-alone gamma voltage generator.
In various embodiments, each pixel of the display panel 100 may have an active matrix pixel circuit, which may be composed of a LED/OLED and several transistors, and may be coupled to the source drive 102 through a data line and coupled to the gate driver 104 through one or more gate lines. The display data voltages are delivered to the pixels through the data lines and stored in the capacitors of the pixels based on the scan control row by row, where each pixel receives the corresponding data voltage when scanned by the gate/emission control signals through the gate lines.
The driving transistor MPDRV is used to output a driving current ILED to control the light emitting device L1. More specifically, the driving transistor MPDRV may generate a drain current according to a received display data Vdata (which may be in the form of a data voltage), and the drain current may serve as the driving current ILED to be output to drive the light emitting device L1 to emit light.
Other transistors MP1-MP5 of the pixel circuit 20 may serve as switches for controlling the operations of the driving transistor MPDRV and the light emitting device L1. These transistors MP1-MP5 may be deployed and controlled appropriately to cancel the deviations of the driving current ILED generated from the offset of the threshold voltage of the driving transistor MPDRV. In this embodiment, these transistors MP1-MP5 may receive control signals PH1-PH4 to realize the offset cancellation in several phases. The control signals PH1-PH4 may be received from a GOA circuit through the gate lines, where the GOA circuit may be implemented in the gate driver 104 as shown in
The capacitor C1 is coupled between the gate terminal of the driving transistor MPDRV and the power supply terminal that supplies the power supply voltage PVDD. More specifically, a first terminal of the capacitor C1 may be coupled to the gate terminal of the driving transistor MPDRV, and a second terminal of the capacitor C1 may be coupled to the power supply terminal of PVDD, which is further coupled to the upper terminal of the driving transistor MPDRV (through the control transistor MP1), where the upper terminal of the driving transistor MPDRV may be its source terminal according to the current direction.
The capacitor C2 is coupled between the lower terminal of the driving transistor MPDRV and the control transistor MP2. More specifically, a first terminal of the capacitor C2 may be coupled to the lower terminal of the driving transistor MPDRV, and a second terminal of the capacitor C2 may be coupled to the control transistor MP2, where the lower terminal of the driving transistor MPDRV may be its drain terminal according to the current direction. When the display data Vdata is received, the information associated with the display data Vdata may be stored in the capacitors C1 and/or C2. The capacitors C1 and/or C2 may also store the information of the threshold voltage of the driving transistor MPDRV.
The control transistor MP1 is coupled to the upper terminal of the driving transistor MPDRV. In detail, a first terminal of the control transistor MP1 may be coupled to the power supply terminal to receive the power supply voltage PVDD, a second terminal of the control transistor MP1 may be coupled to the upper terminal of the driving transistor MPDRV, and the gate terminal of the control transistor MP1 may receive the control signal PH3. The control transistor MP1 may serve as a switch for controlling the pixel circuit 20 to receive the power supply voltage PVDD.
The control transistor MP2 is coupled to the lower terminal of the driving transistor MPDRV through the capacitor C2. In detail, a first terminal of the control transistor MP2 may be coupled to the capacitor C2 and the lower terminal of the driving transistor MPDRV, a second terminal of the control transistor MP2 may be coupled to a data line DL to receive the display data Vdata, and the gate terminal of the control transistor MP2 may receive the control signal PH2. The control transistor MP2 may serve as a switch for controlling display data reception, to control the pixel circuit 20 to receive the display data Vdata.
The control transistor MP3 is coupled between the lower terminal of the driving transistor MPDRV and the gate terminal of the driving transistor MPDRV. In detail, a first terminal of the control transistor MP3 may be coupled to the lower terminal of the driving transistor MPDRV, a second terminal of the control transistor MP3 may be coupled to the gate terminal of the driving transistor MPDRV, and the gate terminal of the control transistor MP3 may receive the control signal PH2. The control transistor MP3 may serve as a switch for initialization and compensation information writing. More specifically, the control transistor MP3 may be connected with the driving transistor MPDRV to form a diode-connected structure, to help initialize the driving transistor MPDRV to an appropriate voltage in each operation cycle, allowing the input data Vdata to be successfully received by the driving transistor MPDRV after initialization.
The control transistor MP4 is coupled between the lower terminal of the driving transistor MPDRV and the light emitting device L1. In detail, a first terminal of the control transistor MP4 maybe coupled to the lower terminal of the driving transistor MPDRV, a second terminal of the control transistor MP4 may be coupled to the light emitting device L1, and the gate terminal of the control transistor MP4 may receive the control signal PH4. The control transistor MP4 may serve as a switch for controlling light emission of the pixel circuit 20. More specifically, the control transistor MP4 may be used to control the driving current ILED generated by the driving transistor MPDRV to flow to the light emitting device L1, in order to drive the light emitting device L1 to emit light.
The control transistor MP5 is coupled to the gate terminal of the driving transistor MPDRV. In detail, a first terminal of the control transistor MP5 may be coupled to the gate terminal of the driving transistor MPDRV, a second terminal of the control transistor MP5 may be coupled to a reset input terminal to receive an initial voltage Vinitp, and the gate terminal of the control transistor MP5 may receive the control signal PH1. The control transistor MP5 may serve as a switch for controlling the initialization or reset of the driving transistor MPDRV, where the control transistor MP5 may form a signal path for forwarding the initial voltage Vinitp to the driving transistor MPDRV to initialize the driving transistor MPDRV.
The light emitting device L1 is coupled between the driving transistor MPDRV and the power supply terminal that supplies the power supply voltage ELVSS. In detail, a first terminal of the light emitting device L1 may be coupled to the lower terminal of the driving transistor MPDRV through the control transistor MP4, and a second terminal of the light emitting device L1 may be coupled to the power supply terminal of ELVSS. The light emitting device L1, which is configured to emit light as being driven by the driving current ILED received from the driving transistor MPDRV, may be any device capable of emitting light by receiving currents, such as an OLED or a micro-OLED.
The operations of the pixel circuit 20 include four phases: an initial phase, a compensation phase, a scan phase, and an emission phase.
As shown in
As shown in
As shown in
As shown in
In this embodiment, in the scan phase P3, the display data Vdata is coupled through the capacitor C2 with a ratio α, where α is equal to C2/(C1+C2). The coupled electric charges are generated at the driving transistor MPDRV and stored into the capacitor C1. This generates a voltage variation equal to ΔV×α on the drain terminal and the gate terminal of the driving transistor MPDRV. Therefore, the electric charges stored in the capacitor C1 may become Vthp+ΔV×α, and the gate voltage VG of the driving transistor MPDRV may be equal to:
VG=PVDD−Vthp−ΔV×α.
The driving current ILED generated in the emission phase P4 may be calculated as follows:
where
ΔV=Vinitp−Vdata;
α=C2/(C1+C2);
As can be seen in Equation (1), the value of the driving current ILED only includes a signal dependent term consisting of the input data Vdata and the initial voltage Vinitp, and will not depend on the threshold voltage Vthp, which means that the offset of the threshold voltage Vthp between pixels will not influence the current magnitude and thus will not influence the brightness of the light emitting device L1.
In addition, in this embodiment, the input voltage variation ΔV is multiplied by a ratio α when coupled to the driving transistor MPDRV to be used to determine the driving current ILED; and this is different from the conventional pixel circuit where the input voltage variation is directly applied to determine the driving current without being modified by a ratio. This improves the operational voltage range of the display data Vdata. The value of the ratio may be well controlled by allocating appropriate values of the capacitors C1 and C2 in the pixel circuit.
As mentioned above, in the silicon-based implementation, 256 grayscales should be generated within an operational voltage range between 200 mV-300 mV, and thus one step voltage may be about 1 mV for each gray level. In comparison, based on the pixel circuit of the present invention, the input voltage variation ΔV may be expanded by applying appropriate values of the capacitors C1 and C2; that is, the possible range of the display data voltage Vdata may be expanded. For example, if the ratio α to be multiplied with the display data Vdata equals 3, the operational voltage range may be approximately tripled. This significantly reduces the burden of the design of grayscale-to-voltage mapping.
Please note that the present invention aims at providing a novel pixel circuit capable of canceling the offset of threshold voltages and applicable to the silicon-based implementation. Those skilled in the art may make modifications and alterations accordingly. For example, in the pixel circuit, the light emitting device may be an OLED, a micro-OLED, or any other possible device capable of light emission function. The pixel circuit structure of the present invention is preferably applied to a micro-OLED panel implemented with the CMOS process, but not limited thereto. In fact, the pixel circuit of the present invention may be applied to any self-luminous panel, which includes, but not limited to, a mini-LED panel, micro-LED panel, ultra-LED panel, OLED panel, and micro-OLED panel.
In addition, the pixel circuit structure as shown in
Note that the pixel circuits in the above embodiments apply all PMOS transistors to control the light emitting device, but the present invention is not limited thereto. In another embodiment, similar implementations may be realized by using NMOS transistors or combinations of PMOS and NMOS transistors, where the levels of the control signals and the initial voltage may be modified accordingly.
In the pixel circuit 50, the driving transistor MNDRV is used to output a driving current ILED to control the light emitting device L2 based on the received display data Vdata. Other transistors MN1-MN5 of the pixel circuit 50 may serve as switches for controlling the operations of the driving transistor MNDRV and the light emitting device L2. These transistors MN1-MN5 may be deployed and controlled appropriately to cancel the deviations of the driving current ILED generated from the offset of the threshold voltage of the driving transistor MNDRV. These transistors MN1-MN5 may receive control signals PH1-PH4 to realize the offset cancellation in several phases. The control signals PH1-PH4 may be received from a GOA circuit through the gate lines, where the GOA circuit may be implemented in the gate driver 104 as shown in
The capacitor C1 is coupled to the gate terminal of the driving transistor MNDRV and the control transistor MN4. More specifically, a first terminal of the capacitor C1 may be coupled to the gate terminal of the driving transistor MNDRV, and a second terminal of the capacitor C1 may be coupled to the lower terminal of the control transistor MN4, which is further coupled to the lower terminal of the driving transistor MNDRV, where the lower terminal of the driving transistor MNDRV may be its source terminal according to the current direction.
The capacitor C2 is coupled between the upper terminal of the driving transistor MNDRV and the control transistor MN2. More specifically, a first terminal of the capacitor C2 may be coupled to the upper terminal of the driving transistor MNDRV, and a second terminal of the capacitor C2 may be coupled to the control transistor MN2, where the upper terminal of the driving transistor MNDRV may be its drain terminal according to the current direction. When the display data Vdata is received, the information associated with the display data Vdata may be stored in the capacitors C1 and/or C2. The capacitors C1 and/or C2 may also store the information of the threshold voltage of the driving transistor MNDRV.
The control transistor MN1 is coupled to the upper terminal of the driving transistor MNDRV. In detail, a first terminal of the control transistor MN1 may be coupled to the power supply terminal to receive the power supply voltage PVDD, a second terminal of the control transistor MN1 may be coupled to the upper terminal of the driving transistor MNDRV, and the gate terminal of the control transistor MN1 may receive the control signal PH2. The control transistor MN1 may serve as a switch for controlling the pixel circuit 50 to receive the power supply voltage PVDD.
The control transistor MN2 is coupled to the upper terminal of the driving transistor MNDRV through the capacitor C2. In detail, a first terminal of the control transistor MN2 may be coupled to the capacitor C2 and the upper terminal of the driving transistor MNDRV, a second terminal of the control transistor MN2 may be coupled to a data line DL to receive the display data Vdata, and the gate terminal of the control transistor MN2 may receive the control signal PH1. The control transistor MN2 may serve as a switch for controlling display data reception, to control the pixel circuit 50 to receive the display data Vdata.
The control transistor MN3 is coupled between the upper terminal of the driving transistor MNDRV and the gate terminal of the driving transistor MNDRV. In detail, a first terminal of the control transistor MN3 may be coupled to the upper terminal of the driving transistor MNDRV, a second terminal of the control transistor MN3 may be coupled to the gate terminal of the driving transistor MNDRV, and the gate terminal of the control transistor MN3 may receive the control signal PH4. The control transistor MN3 may serve as a switch for initialization and compensation information writing. More specifically, the control transistor MN3 may be connected with the driving transistor MNDRV to form a diode-connected structure, to help initialize the driving transistor MNDRV to an appropriate voltage in each operation cycle, allowing the input data Vdata to be successfully received by the driving transistor MNDRV after initialization.
The control transistor MN4 is coupled between the lower terminal of the driving transistor MNDRV and the light emitting device L2. In detail, a first terminal of the control transistor MN4 may be coupled to the lower terminal of the driving transistor MNDRV, a second terminal of the control transistor MN4 may be coupled to the light emitting device L2, and the gate terminal of the control transistor MN4 may receive the control signal PH3. The control transistor MN4 may serve as a switch for controlling light emission of the pixel circuit 50. More specifically, the control transistor MN4 may be used to control the driving current ILED generated by the driving transistor MNDRV to flow to the light emitting device L2, in order to drive the light emitting device L2 to emit light.
The control transistor MN5 is coupled to the capacitor C1, the control transistor MN4 and the light emitting device L2. In detail, a first terminal of the control transistor MN5 may be coupled to the capacitor C1, the control transistor MN4 and the light emitting device L2, a second terminal of the control transistor MN5 may be coupled to a reset input terminal to receive an initial voltage Vinitn, and the gate terminal of the control transistor MN5 may receive the control signal PH1. The control transistor MN5 may serve as a switch for controlling the initialization or reset of the driving transistor MNDRV, where the control transistor MN5 may form a signal path for forwarding the initial voltage Vinitn to the light emitting device L2 to initialize the light emitting device L2.
The light emitting device L2 is coupled between the driving transistor MNDRV and the power supply terminal that supplies the power supply voltage ELVSS. In detail, a first terminal of the light emitting device L2 may be coupled to the lower terminal of the driving transistor MNDRV through the control transistor MN4, and a second terminal of the light emitting device L2 may be coupled to the power supply terminal of ELVSS. The light emitting device L2, which is configured to emit light as being driven by the driving current ILED received from the driving transistor MNDRV, may be any device capable of emitting light by receiving currents, such as an OLED or a micro-OLED.
Similarly, the operations of the pixel circuit 50 include four phases: an initial phase, a compensation phase, a scan phase, and an emission phase.
As shown in
As shown in
As shown in
As shown in
The operational principles of the pixel circuit 50 are similar to those of the pixel circuit 20; hence, the driving current ILED may be calculated following a similar equation associated with NMOS transistors, which may be derived in a similar manner as Equation (1) for PMOS transistors as described above. More specifically, in the scan phase P3, the gate voltage VG of the driving transistor MNDRV may be equal to:
VG=Vinitn+Vthn+ΔV×α;
ILED=I(′(ΔV×α)2; (2)
where
ΔV=Vdata−Vinitp;
α=C2/(C1+C2);
where K′ represents the gain factor of the driving transistor MNDRV. In such a situation, the offset of the threshold voltage between pixels may be canceled in a similar manner.
In various embodiments of the present invention, the display data input to a pixel circuit is coupled to the driving transistor through a capacitor (e.g., the capacitor C2 in the pixel circuit 20 or 50), to generate a reduced voltage variation on the driving transistor which is smaller than the voltage variation of the data line. In other words, the input display data is multiplied by a ratio which is usually smaller than 1. Therefore, in order to generate a specific current level for driving the light emitting device to emit light, the operational voltage range of the input display data may be expanded. This facilitates the gamma voltage design to allocate more preferable gamma voltages for the grayscale values with finer resolution, so as to achieve a better display quality. In addition, the input display data is coupled to the drain terminal of the driving transistor and then forwarded to the gate terminal of the driving transistor. The above implementations are more feasible to a silicon-based display panel where the transistors are implemented with the CMOS process and have a higher mobility. In the silicon-based display panel, the desired driving current for the light emitting device is generated by a smaller voltage range (e.g., between 200 mV and 300 mV). The pixel circuit provided in the present invention may expand the operational voltage range of the display data, so as to facilitate the design of grayscale-to-voltage mapping.
To sum up, the present invention provides a novel pixel circuit of a display panel. In the pixel circuit, the input display data is coupled to the drain terminal of the driving transistor through a capacitor, and then forwarded to the gate terminal of the driving transistor. The capacitor coupling generates a smaller voltage variation on the driving transistor for generating the desired current to drive the light emitting device, which means that the operational voltage range of the display data is expanded. The pixel circuit is more feasible to a silicon-based display panel such as a micro-OLED panel.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
This application claims the benefit of U.S. Provisional Application No. 63/424,140, filed on Nov. 10, 2022. The content of the application is incorporated herein by reference.
Number | Date | Country | |
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63424140 | Nov 2022 | US |