Patent Grant
12125435
This application claims priority to China Application Serial Number 202211344595.3, filed Oct. 31, 2022, which is herein incorporated by reference.
The present invention relates to pixel circuits and operation methods, and more particularly, a pixel circuit with pulse width compensation and an operation method thereof.
In recent years, with the vigorous development of display technology, active organic light emitting diode display technology with advantages such as high contrast ratio and low power consumption has been widely used in mobile phones, tablets, and screen displays.
In view of the foregoing, there still exist some problems on the driving capability of the pixel circuit that await further improvement. However, those skilled in the art sought vainly for a solution. Accordingly, there is an urgent need in the related field to propose a new pixel circuit to improve the driving capability.
The following presents a simplified summary of the disclosure in order to provide a basic understanding to the reader. This summary is not an extensive overview of the disclosure and it does not identify key/critical components of the present invention or delineate the scope of the present invention. Its sole purpose is to present some concepts disclosed herein in a simplified form as a prelude to the more detailed description that is presented later.
According to embodiments of the present disclosure, the present disclosure provides a pixel circuit with pulse width compensation and its operation method, to solve or circumvent aforesaid problems and disadvantages in the related art.
An embodiment of the present disclosure is related to a pixel circuit with pulse width compensation, and the pixel circuit includes a pulse width modulation circuit and a pulse amplitude modulation circuit, and the pulse amplitude modulation circuit is electrically connected to the pulse width modulation circuit. The pulse width modulation circuit includes a P-type pulse width compensation transistor and a first P-type control transistor, and the first P-type control transistor is electrically connected to the P-type pulse width compensation transistor. The pulse amplitude modulation circuit includes a second P-type control transistor, a first capacitor, a P-type driving transistor and a light-emitting element. The second P-type control transistor is electrically connected to the first P-type control transistor. The first capacitor is electrically connected to the second P-type control transistor. The P-type driving transistor is electrically connected to the first capacitor, and the light-emitting element is electrically connected to the P-type driving transistor.
In one embodiment of the present disclosure, the first P-type control transistor includes a control terminal, the P-type pulse width compensation transistor includes a first terminal, a second terminal and a control terminal, the first terminal of the P-type includes compensation transistor is electrically connected to the control terminal of the first P-type control transistor, the second terminal of the P-type pulse width compensation transistor receives a scanning voltage, and the control terminal of the P-type pulse width compensation transistor receives a light-emitting signal.
In one embodiment of the present disclosure, the first P-type control transistor includes a control terminal, and the pulse width modulation circuit includes a data writing transistor. The data writing transistor includes a first terminal, a second terminal and a control terminal. The first terminal of the data writing transistor is electrically connected to the control terminal of the first P-type control transistor, the second terminal of the data writing transistor receives a data voltage, and the control terminal of the data writing transistor receives a control signal.
In one embodiment of the present disclosure, the first P-type control transistor includes a first terminal, a second terminal and a control terminal, and the pulse width modulation circuit includes a first P-type reset transistor and a second P-type reset transistor. The first P-type reset transistor includes a first terminal, a second terminal and a control terminal. The first terminal of the first P-type reset transistor is electrically connected to the first terminal of the first P-type control transistor, the second terminal of the first P-type reset transistor is electrically connected to the control terminal of the first P-type control transistor, and the control terminal of the first P-type reset transistor receives a control signal. The second P-type reset transistor includes a first terminal, a second terminal and a control terminal. The first terminal of the second P-type reset transistor is electrically connected to the second terminal of the first P-type control transistor, the second terminal of the second P-type reset transistor receives a reference voltage, and the control terminal of the second P-type reset transistor receives the control signal.
In one embodiment of the present disclosure, the first P-type control transistor includes a first terminal, the second P-type control transistor includes a control terminal, and the pulse width modulation circuit includes a P-type reset transistor. The P-type reset transistor includes a first terminal, a second terminal and a control terminal. The first terminal of the P-type reset transistor is electrically connected to the first terminal of the first P-type control transistor terminal and the control terminal of the second P-type control transistor, the second terminal of the P-type reset transistor receives a reference voltage, and the control terminal of the P-type reset transistor receives an inverted light-emitting signal.
In one embodiment of the present disclosure, the second P-type control transistor includes a first terminal, a second terminal and a control terminal, the second terminal of the second P-type control transistor receives a driving voltage, and the pulse amplitude modulation circuit includes a P-type reset transistor. The P-type reset transistor includes a first terminal, a second terminal and a control terminal. The first terminal of the P-type reset transistor is electrically connected to the first terminal of the second P-type control transistor, the second terminal of the P-type reset transistor receives a reference voltage, and the control terminal of the P-type reset transistor receives an inverted light-emitting signal.
In one embodiment of the present disclosure, the second P-type control transistor includes a first terminal, and the pulse amplitude modulation circuit includes a second capacitor connected in series with the first capacitor. One terminal of the second capacitor is electrically connected to the first terminal of the second P-type control transistor and the first capacitor, and another terminal of the second capacitor receives a reference voltage.
In one embodiment of the present disclosure, the P-type driving transistor includes a first terminal, a second terminal and a control terminal, the light-emitting element includes an anode and a cathode, the anode of the light-emitting element receives a first operating voltage, the cathode of the light-emitting element is electrically connected to the second terminal of the P-type driving transistor, the first terminal of the P-type driving transistor receives a second operating voltage, the control terminal of the P-type driving transistor is electrically connected to the first capacitor, and the first operating voltage is higher than the second operating voltage.
In one embodiment of the present disclosure, the pulse amplitude modulation circuit includes a P-type switching transistor. The P-type switching transistor includes a first terminal, a second terminal and a control terminal. The first terminal of the P-type switching transistor is electrically connected to the control terminal of the P-type driving transistor, the second terminal of the P-type switching transistor receives the first operating voltage, and the control terminal of the P-type switching transistor receives a control signal.
In one embodiment of the present disclosure, the pulse amplitude modulation circuit includes a P-type threshold voltage compensation transistor and a P-type switching transistor. The P-type threshold voltage compensation transistor includes a first terminal, a second terminal and a control terminal. The second terminal and the control terminal of the P-type threshold voltage compensation transistor receive a reference voltage. The P-type switching transistor includes a first terminal, a second terminal and a control terminal. The first terminal of the P-type switching transistor is electrically connected to the first capacitor, the second terminal of the P-type switching transistor is electrically connected to the first terminal of the P-type threshold voltage compensation transistor, and the control terminal of the P-type switching transistor receives a control signal.
Another embodiment of the present disclosure is related to a pixel circuit with pulse width compensation, and the pixel circuit includes a pulse width modulation circuit and a pulse amplitude modulation circuit, and the pulse amplitude modulation circuit is electrically connected to the pulse width modulation circuit. The pulse width modulation circuit includes a P-type pulse width compensation transistor and a first P-type control transistor, and the first P-type control transistor is electrically connected to the P-type pulse width compensation transistor. The pulse amplitude modulation circuit includes a P-type driving transistor and a second P-type control transistor. The P-type driving transistor is electrically connected to a light-emitting element. The second P-type control transistor is electrically connected to the first P-type control transistor, and the second P-type control transistor is electrically connected to the P-type driving transistor through a capacitor. In an emission period, the P-type pulse width compensation transistor is turned on, so that the first P-type control transistor is turned on to turn on the second P-type control transistor, so as to turn on the P-type driving transistor for driving the light-emitting element to emit light.
In one embodiment of the present disclosure, the pulse width modulation circuit includes a first P-type reset transistor, a second P-type reset transistor and a third P-type reset transistor, the pulse amplitude modulation circuit includes a fourth P-type reset transistor and a P-type switching transistor, the first P-type control transistor includes a first terminal, a second terminal and a control terminal, the first terminal of the first P-type control transistor is electrically the first and third P-type reset transistors, the second terminal of the first P-type control transistor is electrically connected to the second P-type reset transistor, the control terminal of the first P-type control transistor is electrically connected between the P-type pulse width compensation transistor and the first P-type reset transistor, the fourth P-type reset transistor is electrically connected to the second P-type control transistor, and the P-type switching transistor is electrically connected to the P-type driving transistor and the light-emitting element. In a reset period, the P-type pulse width compensation transistor is turned off by a disabling level of a light-emitting signal, the third and fourth P-type reset transistors are turned on by an enabling level of an inverted light-emitting signal, and the first and second P-type reset transistors and the P-type switching transistor are turned on by the enabling level of a control signal, so that the P-type driving transistor is turned off.
In one embodiment of the present disclosure, the pulse width modulation circuit includes a data writing transistor, the pulse amplitude modulation circuit includes a P-type threshold voltage compensation transistor and a P-type switching transistor, the first P-type control transistor includes a control terminal, the control terminal of the first P-type control transistor is electrically connected to the P-type pulse width compensation transistor and the data writing transistor, the P-type switching transistor is electrically connected to the P-type driving transistor and the capacitor through a node, the P-type threshold voltage compensation transistor is electrically connected to the P-type switching transistor, and the P-type threshold voltage compensation transistor receives a reference voltage. In a compensation and data input period, the P-type pulse width compensation transistor is turned off by a disabling level of a light-emitting signal, the data writing transistor and the P-type switching transistor are turned on by an enabling level of a control signal, so that the data writing transistor writes a data voltage to the control terminal of the first P-type control transistor, and the P-type threshold voltage compensation transistor discharges the node to the reference voltage plus a threshold voltage of the P-type threshold voltage compensation transistor.
In one embodiment of the present disclosure, the first P-type control transistor further includes a first terminal, the second P-type control transistor includes a first terminal, a second terminal and a control terminal, the P-type driving transistor includes a control terminal, the control terminal of the first P-type control transistor is electrically connected to the data writing transistor, the first terminal of the first P-type control transistor is electrically connected to the control terminal of the second P-type control transistor, and the first terminal of the second P-type control transistor is electrically connected to the control terminal of the P-type driving transistor through the capacitor. In the emission period, the P-type pulse width compensation transistor is turned on by the enabling level of the light-emitting signal, when the data voltage is greater than a sawtooth voltage received by the P-type plus width compensation transistor, the first P-type control transistor is turned on to turn on the second P-type control transistor, and the second terminal of the second P-type control transistor receive a driving voltage having the enabling level, so that the P-type driving transistors are turned on to drive the light-emitting element to emit the light.
In one embodiment of the present disclosure, the pulse width modulation circuit includes a P-type reset transistor, the pulse amplitude modulation circuit includes a P-type reset transistor, the P-type reset transistor of the pulse width modulation circuit is electrically connected to the first P-type control transistor, and the P-type reset transistor of the pulse amplitude modulation circuit is electrically connected to the second P-type control transistor. In a turn-off period, the P-type pulse width compensation transistor is turned off by a disabling level of a light-emitting signal, and the P-type reset transistor of the pulse width modulation circuit and the P-type reset transistor of the pulse amplitude modulation circuit are turned on by an enabling level of an inverted light-emitting signal.
Yet another embodiment of the present disclosure is related to an operation method of a pixel circuit with pulse width compensation, the pixel circuit includes a pulse width modulation circuit and a pulse amplitude modulation circuit, the pulse width modulation circuit includes a P-type pulse width compensation transistor and a first P-type control transistor, the pulse amplitude modulation circuit includes a P-type driving transistor and a second P-type control transistor, and the operation method includes steps of: in an emission period, turning on the P-type pulse width compensation transistor is, so that the first P-type control transistor is turned on to turn on the second P-type control transistor, so as to turn on the P-type driving transistor; driving the light-emitting element to emit light through the P-type driving transistor when the P-type driving transistor is turned on.
In one embodiment of the present disclosure, the pulse width modulation circuit includes a first P-type reset transistor, a second P-type reset transistor and a third P-type reset transistor, the pulse amplitude modulation circuit includes a fourth P-type reset transistor and a P-type switching transistor, and the operation method further includes steps of: in a reset period, providing a light-emitting signal having a disabling level for the P-type pulse width compensation transistor, so that the P-type pulse width compensation transistor is turned off; in the reset period, providing an inverted light-emitting signal having an enabling level for the third and fourth P-type reset transistors, so that the third and fourth P-type reset transistors are turned on; in the reset period, providing a control signal having the enabling level for the first and second P-type reset transistors and the P-type switching transistor, so that the first and second P-type reset transistors and the P-type switching transistor are turned on, and the P-type driving transistor is turned off.
In one embodiment of the present disclosure, the pulse width modulation circuit includes a data writing transistor, the pulse amplitude modulation circuit includes a P-type threshold voltage compensation transistor and a P-type switching transistor, and the operation method further includes steps of: in a compensation and data input period, providing a light-emitting signal having a disabling level for the P-type pulse width compensation transistor, so that the P-type pulse width compensation transistor is turned off; in the compensation and data input period, providing a control signal having an enabling level for the data writing transistor, so that the data writing transistor is turned on, and the data writing transistor writes a data voltage to a control terminal of the first P-type control transistor; in the compensation and data input period, providing the control signal having the enabling level for the P-type switching transistor, so that the P-type switching transistor is turned on, and the P-type threshold voltage compensation transistor discharges a node to a reference voltage plus a threshold voltage of the P-type threshold voltage compensation transistor.
In one embodiment of the present disclosure, the operation method further includes steps of: in the emission period, providing the light-emitting signal having the enabling level for the P-type pulse width compensation transistor, so that the P-type pulse width compensation transistor is turned on; in the emission period, when the data voltage is greater than a sawtooth voltage received by the P-type plus width compensation transistor, turning on the first P-type control transistor to turn on the second P-type control transistor, and providing a driving voltage having the enabling level for the second P-type control transistor, so that the P-type driving transistor is turned on to drive the light-emitting element to emit the light.
In one embodiment of the present disclosure, the pulse width modulation circuit includes a P-type reset transistor electrically connected to the first P-type control transistor, the pulse amplitude modulation circuit includes a P-type reset transistor electrically connected to the second P-type control transistor, and the operation method further includes steps of: in a turn-off period, providing a light-emitting signal having a disabling level for the P-type pulse width compensation transistor, so that the P-type pulse width compensation transistor is turned off; in the turn-off period, providing an inverted light-emitting signal having an enabling level for the P-type reset transistor of the pulse width modulation circuit and the P-type reset transistor of the pulse amplitude modulation circuit, so that the P-type reset transistor of the pulse width modulation circuit and the P-type reset transistor of the pulse amplitude modulation circuit are turned on.
In view of the above, according to the present disclosure, the pixel circuit of the present disclosure and the operation method thereof using all P-type transistors (e.g., low temperature polysilicon thin film transistors) can save costs and also avoid the problem of insufficient driving capability due to excessive size.
Many of the attendant features will be more readily appreciated, as the same becomes better understood by reference to the following detailed description considered in connection with the accompanying drawings.
The invention can be more fully understood by reading the following detailed description of the embodiment, with reference made to the accompanying drawings as follows:
Reference will now be made in detail to the present embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
The terms used in this specification generally have their ordinary meanings in the art, within the context of the invention, and in the specific context where each term is used. Certain terms that are used to describe the invention are discussed below, or elsewhere in the specification, to provide additional guidance to the practitioner regarding the description of the invention. The use of examples anywhere in this specification, including examples of any terms discussed herein, is illustrative only, and in no way limits the scope and meaning of the invention or of any exemplified term. Likewise, the invention is not limited to various embodiments given in this specification.
As used in the description herein and throughout the claims that follow, the meaning of “a”, “an”, and “the” includes reference to the plural unless the context clearly dictates otherwise.
As used herein, “around”, “about”, “substantially” or “approximately” shall generally mean within 20 percent, preferably within 10 percent, and more preferably within 5 percent of a given value or range. Numerical quantities given herein are approximate, meaning that the term “around”, “about”, “substantially” or “approximately” can be inferred if not expressly stated.
Also, as used in the description herein and throughout the claims that follow, the terms “comprise or comprising”, “include or including”, “have or having”, “contain or containing” and the like are to be understood to be open-ended, i.e., to mean including but not limited to.
Referring to
The subject disclosure provides the pixel circuit 100 of
As shown in
With the above all-P-type transistor structure, in the emission period, the P-type pulse width compensation transistor T11 is turned on, so that the first P-type control transistor T12 is turned on to turn on the second P-type control transistor T5, thereby turning on the P-type driving transistor. The transistorT1 drives the light-emitting element111 to emit light.
As shown in
Structurally, the first terminal of the first P-type control transistor T12 is electrically connected to the first and third P-type reset transistors T8 and T6, and the second terminal of the first P-type control transistor T12 is electrically connected to the second P-type reset transistor T9. The control terminal of the first P-type control transistorT12 is electrically connected between the P-type pulse width compensation transistor T11 and the first P-type reset transistor T8, the fourth P-type reset transistor T7 is electrically connected to the second P-type control transistor T5, and the P-type switching transistor The transistor T3 is electrically connected to the P-type driving transistor T1 and the light-emitting element 111.
With the above all-P-type transistor structure, in the reset period, the P-type pulse width compensation transistor T11 is turned off by the disabling level of the light-emitting signal EM, and the third and fourth P-type reset transistors T6 and T7 are turned on by the enabling level of the inverted light-emitting signal EMB, the first and second P-type reset transistors T8 and T9 and P-type switching transistor T3 are turned on by the enabling level of the control signal S1, so that the P-type driving transistor T1 is turned off; the voltage of A is about the first operating voltage VDD, which turns off the P-type driving transistor T1.
As shown in
Structurally, the control terminal of the first P-type control transistor T12 is electrically connected to the P-type pulse width compensation transistor T11 and the data writing transistor T10, and the P-type switching transistor T4 is electrically connected to the P-type driving transistor T1 and the first capacitorC1 through the node A, the P-type threshold voltage compensation transistor T2 is electrically connected to the P-type switching transistorT4, and the P-type threshold voltage compensation transistorT2 receives the reference voltage Vref1.
With the above-mentioned all-P-type transistor structure, after the above-mentioned reset period, in the compensation and data input period, the P-type pulse width compensation transistor T11 is turned off by the disabling level of the light-emitting signal, and the data writing transistor T6 and P-type switching transistor T4 are turned on by the enabling level of control signal S2, so that the data writing transistor T10 writes data voltage Vdata to the control terminal of first P-type control transistor T12, and P-type threshold voltage compensation transistor T2 discharges the node A to the reference voltage plus the threshold voltage of P-type threshold voltage compensation transistor T2. However, the voltage between source and gate of P-type driving transistor T1 is lower than the threshold voltage of P-type driving transistor T1, and the voltage from the source to the gate of first P-type control transistor T12 is lower than the threshold voltage of the first P-type control transistor T12; at this time, the P-type driving transistor T1 and the first P-type control transistor T12 are not turned on.
As shown in
With the above-mentioned all-P-type transistor structure, after the above-mentioned compensation and data input period, during the emission period, the P-type pulse width compensation transistor T11 is turned on by the enabling level of the light-emitting signal EM, when the data voltage Vdata is greater than the scanning voltage Vsweep (e.g., a sawtooth voltage) received by the P-type pulse width compensation transistor T11, the first P-type control transistor T12 is turned on to turn on the second P-type control transistor T5. The second terminal of the second P-type control transistor T5 receives the driving voltage V5 having the enabling level, so that the P-type driving transistor T1 is turned on to drive the light-emitting element 111 to emit light.
Then, after the above-mentioned emission period, in the turn-off period, the P-type pulse width compensation transistorT11 is turned off by the disabling level of the light-emitting signal, and the third P-type reset transistor T6 and the fourth P-type reset transistor T7 are turned on by the enabling level of the inverted light-emitting signal, so that the P-type driving transistor T1 is turned off.
Regarding the overall circuit structure of the pulse width modulation circuit 120, as shown in
Specifically, regarding the connection structure of the P-type pulse width compensation transistor T11, as shown in
Specifically, regarding the connection structure of the data writing transistor T10, as shown in
Specifically, regarding the connection structure of the first and second P-type reset transistors T8 and T9, as shown in
Specifically, regarding the connection structure of the third P-type reset transistor T6, the first terminal of the third P-type reset transistor T6 is electrically connected to the first terminal of the first P-type control transistor T12 and the control terminal of the second P-type control transistor T5, the second terminal of the third P-type reset transistor T6 receives the reference voltage Vref6 (e.g., about 7V), and the control terminal of the third P-type reset transistor T6 receives the inverted light-emitting signal EMB.
Specifically, regarding the overall circuit structure of the pulse amplitude modulation circuit 110, as shown in
Specifically, regarding the connection structure of the fourth P-type reset transistor T7, as shown in
Specifically, regarding the connection structure of the first and second capacitors C1 and C2, as shown in
Specifically, regarding the connection structure of the P-type driving transistor T1, as shown in
Specifically, regarding the connection structure of the P-type switching transistor T3, as shown in
Specifically, regarding the connection structure of the P-type threshold voltage compensation transistor T2 and the P-type switching transistor T4, as shown in
In view of above, for example, the reference voltage Vref1 can be about 6.8V, the reference voltage Vref2 and the reference voltage Vref9 can be about 3V, and the reference voltage Vref6 and the reference voltage Vref7 can be about 3V, but the present disclosure is not limited thereto. However, in practice, the values of the reference voltages Vref1, Vref2, Vref6, Vref7 and Vref9 can be flexibly adjusted depending on the actual application, so as to adjust the output or switching time.
For further illustrating the operation method of the pixel circuit 100, refer to
In the reset period T01, the light-emitting signal EM having disabling level is provided to the P-type pulse width compensation transistor T11, so that the P-type pulse width compensation transistor T11 is turned off; the inverted light-emitting signal EMB having the enabling level is provided to third and fourth P-type reset transistors T6 and T7, so that the third and fourth P-type reset transistors T6 and T7 are turned on; a control signal S1 having the enabling level is provided to the first and second P-type reset transistorsT8 and T9 and the P-type switching transistor T3, so that the first and second P-type reset transistorsT8 and T9 and the P-type switching transistor T3 are turned on, and the P-type driving transistor T1 is turned off; the control signal S2 having the disabling level is provided to the data writing transistor T10 and P-type switching transistor T4, so that the data writing transistor T10 and the P-type switching transistor T4 are turned off. At this time, the first and second P-type control transistors T12 and T5 are turned off, and the P-type threshold voltage compensation transistor T2 is turned on.
In the compensation and data input period T02, the light-emitting signal EM having the disabling level is provided to the P-type pulse width compensation transistor T11, so that the P-type pulse width compensation transistor T11 is turned off; the control signal S2 having the enabling level is provided to the data writing transistor T10, so that the data writing transistor T10 is turned on to write the data voltage Vdata to the control terminal of the first P-type control transistor T12, but the voltage from the source to the gate of the first P-type control transistor T12 is less than the threshold voltage of the first P-type control transistor T12, at this time, the first P-type control transistor T12 is not turned on; the control signal S2 having the enabling level is provided to the P-type switching transistorT4, so that the P-type switching transistor T4 is turned on, and the P-type threshold voltage compensation transistor T2 discharges the node A to the reference voltage Vref1 plus the threshold voltage of the upper P-type threshold voltage compensation transistor T2, but the voltage between the source and the gate stage of the P-type driving transistor T1 is lower than the threshold voltage of the P-type driving transistor T1, so that the P-type driving transistor T1 is not turned on. In addition, the inverted light-emitting signal EMB having the enabling level is provided to the third and fourth P-type reset transistors T6 and T7, so that the third and fourth P-type reset transistors T6 and T7 are turned on; the control signal S1 having the disabling level is provided to the first and second P-type reset transistors T8 and T9 and the P-type switching transistor T3, so that the first and second P-type reset transistors T8 and T9 and the P-type switching transistor T3 are turned off.
In the emission periodT03, the light-emitting signal EM having the enabling level is provided to the P-type pulse width compensation transistor T11, so that the P-type pulse width compensation transistor T11 is turned on, and when the data voltage Vdata is greater than the scanning voltage Vsweep (e.g., the sawtooth voltage) received by the P-type pulse width compensation transistor T11, the first P-type control transistorT12 is turned on to turn on the second P-type control transistor T5; the driving voltage V5 having the enabling level to the second P-type control transistor T5, so that the P-type driving transistor T1 is turned on, so as to drive the light-emitting element 111 to emit light. In practice, for example, the above-mentioned sawtooth voltage can be linearly decreased from the disabling level to the enabling level within the emission period T03, but the present disclosure is not limited thereto.
Specifically, when the data voltage Vdata is greater than the scanning voltage Vsweep, the first P-type control transistor T12 is turned on, thereby pulling down the voltage level of the node C; at this time, the driving voltage V5 is in the enabling level (i.e., a low level). The voltage between the source and the gate of the second P-type control transistor T5 is greater than the threshold voltage of the second P-type control transistor T5, and thus the second P-type control transistor T5 is turned on, thereby pulling down the voltage of the node A, so that the P-type driving transistor T1 is turned on.
In addition, the inverted light-emitting signal EMB having the disabling level is provided to the third and fourth P-type reset transistors T6 and T7, the third and fourth P-type reset transistors T6 and T7 are turned off; the control signal S1 having the disabling level is provided to the first and second P-type reset transistors T8 and T9 and P-type switching transistor T3, so that the first and second P-type reset transistors T8 and T9 and the P-type switching transistor T3 are turned off; the control signal S2 having the disabling level is provided to the data writing transistorT10 and the P-type switching transistor T4, so that the data writing transistor T10 and the P-type switching transistor T4 are turned off.
In this way, in the emission period T03, the P-type pulse width compensation transistor T11 is turned on, so that the first P-type control transistor P12 is turned on to turn on the second P-type control transistor T5, thereby turning on the P-type driving transistor T1; when the P-type driving transistor T1 is turned on, the light-emitting element 111 is driven to emit light through the P-type driving transistor T1. The current through the light-emitting element 111 satisfies the relation as below.
ILED=½k[(VGS-VTH)]{circumflex over ( )}2=½k[(Vref1+Vth_T2+V5−Vref7−VSS−Vth_T1)]{circumflex over ( )}2=½k [(Vref1+V5−Vref7−VSS)]{circumflex over ( )}2, where k is a parameter (e.g., μCoxW/L), ILED is the current through the light-emitting element 111, Vth_T2 is the threshold voltage of the P-type threshold voltage compensation transistor T2, and Vth_T1 is the threshold voltage of the P-type driving transistor T2, where Vth_T2 is used to compensate Vth_T1.
In the turn-off period T04, the light-emitting signal EM having the disabling level is provided to the P-type pulse width compensation transistor T11, so that the P-type pulse width compensation transistor T11 is turned off; the inverted light-emitting signal EM having the enabling level is provided to the third P-type reset transistor T6 and the fourth P-type reset transistor T7, so that the third P-type reset transistor T6 and the fourth P-type reset transistor T7 are turned on. The other signals are in the disabling level; at this time, the P-type driving transistor T1 is turned off.
In order to describe the current waveform of the pixel circuit 100 in detail, referring to
As shown in
In view of the above, according to the present disclosure, the pixel circuit 100 of the present disclosure and the operation method thereof using all P-type transistors (e.g., low temperature polysilicon thin film transistors) can save costs and also avoid the problem of insufficient driving capability due to excessive size.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202211344595.3 | Oct 2022 | CN | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 11361701 | Tung | Jun 2022 | B1 |
| 20100007386 | Jinta | Jan 2010 | A1 |
| 20220215797 | Zhai | Jul 2022 | A1 |
| Number | Date | Country |
|---|---|---|
| 108694908 | Oct 2018 | CN |
| 114299864 | Apr 2022 | CN |
| I732602 | Jul 2021 | TW |
| Number | Date | Country | |
|---|---|---|---|
| 20240144868 A1 | May 2024 | US |
