BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a circuit diagram illustrating an example of a pixel circuit in the past;
FIG. 2 is a block diagram illustrating the overall configuration of an image display apparatus incorporating a pixel circuit associated with an embodiment of the present invention;
FIG. 3 is a circuit diagram illustrating a reference example of a pixel circuit;
FIG. 4 is a timing diagram used for a description of the operation of the pixel circuit illustrated in FIG. 3;
FIG. 5 is a circuit diagram illustrating a first embodiment of the pixel circuit associated with the embodiment of the present invention;
FIG. 6 is a timing diagram used for a description of the operation of the first embodiment;
FIG. 7 is a circuit diagram illustrating a second embodiment of the pixel circuit associated with the embodiment of the present invention;
FIG. 8 is a timing diagram used for a description of the operation of the second embodiment;
FIG. 9 is a circuit diagram illustrating a third embodiment of the pixel circuit associated with the embodiment of the present invention;
FIG. 10 is a timing diagram used for a description of the operation of the third embodiment;
FIG. 11 is a circuit diagram illustrating a fourth embodiment of the pixel circuit associated with the embodiment of the present invention;
FIG. 12 is a timing diagram used for a description of the operation of the fourth embodiment;
FIG. 13 is a circuit diagram illustrating a fifth embodiment of the pixel circuit associated with the embodiment of the present invention; and
FIG. 14 is a circuit diagram illustrating a sixth embodiment of the pixel circuit associated with the embodiment of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 2 is a block diagram illustrating the overall configuration of an image display apparatus having a pixel circuit associated with an embodiment of the present invention which is integrated into an IC. As shown in the figure, the image display apparatus includes a pixel array unit in the center and a data line drive circuit and a scan line drive circuit which are provided around the pixel array unit. The pixel array unit includes scan lines 1 to m arranged in row directions, data lines 1 to n arranged in column directions, and pixel circuits each disposed where a scan line and a data line intersect each other. The scan line drive circuit is connected to the scan lines 1 to m and sequentially supplies a control signal for linear sequential scanning of the same circuits. The data line drive circuit is connected to the data lines 1 to n. and supplies a video signal to each of the pixel circuits.
FIG. 3 is a circuit diagram illustrating a configuration example of the pixel circuit illustrated in FIG. 2. It is to be noted that this pixel circuit is a reference example on which the present invention is based. The reference example will be described briefly as it is useful to clarify the background of the present invention. The pixel circuit includes four P-channel transistors T1 to T4, two capacitors C1 and C2 and a light-emitting device OLED. Of the four transistors T1 to T4, T1 is a drive transistor, T2 and T3 are switching transistors, and T4 is a sampling transistor. One current path end (source) of the drive transistor T1 is connected to a power supply potential VDD. The other current path thereof (drain D) is connected to the anode of the light-emitting device OLED via the switching transistor T2. The cathode of the light-emitting device OLED is connected to a ground potential GND. The gate of the switching transistor T2 is connected to a drive line arranged in parallel with a scan line. The drain D of the driving transistor T1 is connected to the gate G of the same transistor T1 via the other switching transistor T3. The capacitor C2 is connected between the gate G and a given power supply potential. An auto-zero line, arranged in parallel with the scan line, is connected to the gate of the switching transistor T3. One current path end of the sampling transistor T4 is connected to one end of the capacitor C1. This connection point may be referred to as an input node in the present specification. The other end of the capacitor C1 is connected to the gate G of the drive transistor T1. The other current path end of the sampling transistor T4 is connected to the data line. As a result, the current path end of the sampling transistor T4 and the control end (gate G) of the drive transistor T1 are connected together in an AC fashion by the coupling capacitor C1. The scan line is connected to the gate of the sampling transistor T4.
FIG. 4 is a timing diagram used for a description of the operation of the pixel circuit illustrated in FIG. 3. FIG. 4 illustrates not only the changes in potential (i.e., control signal waveforms) of the drive, auto-zero and scan lines respectively connected to the control ends (gates) of the transistors T2, T3 and T4 but also the change in signal potential of the data line. This figure also presents a waveform showing the change in gate potential of the drive transistor T1.
First in a preparatory period J1, the drive and auto-zero lines are pulled down to a low level, causing the transistors T2 and T3 to conduct. At this time, the drive transistor T1 is connected to the light-emitting device OLED in a diode-connected state, causing a drain current to flow through the drive transistor T1.
In a next auto-zero period J2, the drive line is pulled up to high level, causing the switching transistor T2 to become non-conducting. At this time, the scan line is at low level, causing the sampling transistor T4 to conduct, and a reference potential Vref to be applied to the data line. As the current flow to the drive transistor T1 is shut off, the gate potential of the drive transistor T1 increases. However, when this potential rises to a level VDD-|Vth|, the drive transistor T1 will be non-conducting, causing the potential to stabilize. This operation may be hereinafter referred to as “auto-zero operation.” This auto-zero operation allows a voltage equivalent to the threshold voltage Vth of the drive transistor T1 to be written to the gate G.
In a next data writing period J3, the auto-zero line swings to high level, causing the switching transistor T3 to be non-conducting. Further, the data line potential is reduced from Vref by a signal voltage ΔVdata. This change in the data line potential causes the gate potential of the drive transistor T1 to decrease by ΔVg1 via the capacitor C1.
In a mobility correction period J4 set within the data writing period J3, the auto-zero line is pulled down to low level for a short period of time, causing the switching transistor T3 to temporarily conduct. At this time, the drive transistor T1 is conducting, causing a current to flow from the source to the drain D of the same transistor T1. This current is negatively fed back to the gate G of the drive transistor T1 via the switching transistor T3. This negative feedback operation causes the gate potential of the drive transistor T1 to increase. When the gate potential increases by ΔVg2, the auto-zero line swings back to a high level, causing the switching transistor T3 to turn off (non-conducting).
In a light emission period J5, the scan line is pulled up to a high level, causing the sampling transistor T4 to be non-conducting. The drive line is pulled down to a low level, causing the switching transistor T2 to conduct. As a result, an output current flows through the drive transistor T1 and the light-emitting device OLED, causing the same device OLED to start emitting light.
In the data writing during the above data writing period J3, ΔVg1 and a gate potential Vg of the drive transistor T1 are expressed respectively by the following formulas 2 and 3 if parasitic capacitance is ignored:
ΔVg1=ΔVdata×C1/(C1+C2) (2)
Vg=VDD−|Vth|−ΔVdata×C1/(C1+C2) (3)
Here, the case is considered in which the mobility correction operation is not performed during the mobility correction period J4. In this case, the control proceeds to a light emission period J5 when the data writing period J3 ends. Assuming the current flowing through the light-emitting device OLED in the light emission period J5 to be Ioled, the amount of this current Ioled is controlled by the drive transistor T1 which is connected in series with the light-emitting device OLED. Assuming that the drive transistor T1 operates in its saturation region, Ioled is expressed as follows by formula 4 using the well-known MOS transistor characteristic formula 1 and the above two formulas:
Ioled=μ·Cox(W/L)(½)(VDD−Vg−|Vth|)2=μ·Cox(W/L)(½)(ΔVdata×C1/(C1+C2)2 (4)
where μ is a mobility of the majority carrier in the drive transistor T1, Cox a gate capacitance per unit area, W a gate width, and L a gate length. According to the above formula 4, Ioled is controlled by a signal voltage ΔVdata which is externally given irrespective of the threshold voltage Vth of the drive transistor T1. In other words, the pixel circuit illustrated in FIG. 3 is immune to pixel-to-pixel variations in the threshold voltage Vth of the drive transistor, thus providing a display device with a relatively high current uniformity, and in its turn, a relatively high brightness uniformity.
According to the above formula 4, however, it is clear that variations in the mobility μ between pixels lead directly to variations in the output current Ioled. In the timing diagram shown in FIG. 4, therefore, the mobility μ is corrected in the mobility correction period J4 set within the data writing period J3. If the auto-zero line is pulled down to a low level for a short period of time during the correction period J4, the gate potential of the drive transistor T1 increases by ΔVg2 as a result of a current flowing through the same transistor T1. This causes the amount of current flowing from the drive transistor T1 into the light-emitting device OLED to decrease in the light emission period J5. This function of reducing the gate potential is termed negative feedback operation in the present specification. The larger the mobility μ of the drive transistor T1, the more the gate voltage Vgs (potential difference between the gate and source) of the same transistor T1 diminishes by the negative feedback operation. Therefore, it is clear that variations in the mobility μ are corrected by the mobility correction operation illustrated in the timing diagram of FIG. 4.
If the aforementioned negative feedback operation is set too long, the amount of current flowing from the drive transistor T1 into the light-emitting device OLED decreases, resulting in failure to achieve the desired brightness. Therefore, the negative feedback time should be kept to within a certain limit. On the other hand, the drive transistor T1 commonly has a large current driving capability to drive the light-emitting device OLED. The capacitors C1 and C2 need to be formed within a small pixel. Therefore, their capacitances are limited. This makes the T1 gate potential more likely to increase at a fast pace at the time of the negative feedback operation. More specifically, the T1 current of 1 uA and the C2 capacitance of about 500 fF are practical from a panel design viewpoint. In this case, assuming the negative feedback time to be 3 μs, the increase in the gate potential is as follows:
ΔVg2=1 uA×3 μs/500 fF=6 [V]
That is, the negative feedback operation reduces Vgs as much as 6V. In this case, the data line should be driven in advance with an amplitude sufficiently larger than the reduction of Vgs. However, this is not practically acceptable from the standpoint of power consumption, cost of the driver to drive the data line and so on. A shorter negative feedback time may be an option to ease this problem. However, the auto-zero line, adapted to control the negative feedback time, has a wiring delay. As a result, selection and deselection operations are difficult to perform in a short period of time particularly if the panel is large.
FIG. 5 is a circuit diagram illustrating a first embodiment of the pixel circuit associated with the embodiment of the present invention. To facilitate the understanding thereof, like components as those of the pixel circuit associated with the reference example in FIG. 3 are designated by like reference numerals. As illustrated in the figure, the pixel circuit includes five transistors T1 to T5, the two capacitors C1 and C2, and the light-emitting device OLED. As is clear from the comparison with the reference example illustrated in FIG. 4, the pixel circuit has one additional switching transistor T5. The switching transistor T5 makes up the negative feedback means and has been added exclusively for the negative feedback operation. It is to be noted that although PMOS transistors are used as the transistors T1 to T5 in the first embodiment in FIG. 5, the present invention is not limited thereto. In particular, the transistors T2 to T5 are simple switches. Therefore, all or some of the PMOS transistors may be replaced with NMOS transistors or other switching devices.
This pixel circuit is basically disposed where a scan line, arranged in a row direction to supply a control signal, and a data line, arranged in a column direction to supply a video signal, intersect each other. The pixel circuit includes at least the sampling transistor T4, the drive transistor T1, the capacitor C1 connected between the current path end of the sampling transistor T4 and the gate G of the drive transistor T1. The pixel circuit further includes the capacitor C2 connected between one end of the capacitor C1 and a given power supply potential, and the light-emitting device OLED connected to the current path end (drain D) of the drive transistor T1. The gate of the sampling transistor T4 is connected to the scan line. One current path end of the same transistor T4 is connected to the data line, whereas the other current path end thereof serves as a connection point A with the capacitor C1. The sampling transistor T4 conducts in response to a control signal supplied from the scan line during a given sampling period so as to sample the video signal supplied from the data line. The drive transistor T1 supplies an output current to the light-emitting device OLED during a given light-emitting period in accordance with the video signal sampled. The light-emitting device OLED emits light at the brightness commensurate with the video signal by the output current from the drive transistor T1. The pixel circuit is characterized in that it has negative feedback means. The negative feedback means operate during a correction period set within a sampling period of the video signal to electrically connect the drain D of the drive transistor T1 to the connection point A of the sampling transistor T4, thus negatively feeding the output current back to the connection point A and correcting the mobility μ during the correction period.
In the present embodiment, the switching transistor T5 makes up the negative feedback means. The same transistor T5 intervenes between the drain D of the drive transistor T1 and the connection point A of the sampling transistor T4. This switching transistor T5 conducts in response to a control signal applied to the gate thereof during the correction period to electrically connect the drain D of the drive transistor T1 to the connection point A of the sampling transistor T4. This pixel circuit includes the separate switching transistor T3 connected between the gate G and the drain D of the drive transistor T1. The switching transistor T3 turns on ahead of the sampling of the video signal to write a voltage equivalent to the threshold voltage Vth of the drive transistor T1 to the gate G thereof.
FIG. 6 is a timing diagram used for a description of the operation of the pixel circuit illustrated in FIG. 5. To facilitate the understanding thereof, like reference numerals are used to designate like components as those illustrated in the timing diagram of FIG. 4. First in the preparatory period J1, the drive and auto-zero lines are pulled down to low level, causing the switching transistors T2 and T3 to conduct. At this time, the drive transistor T1 is connected to the light-emitting device OLED in a diode-connected state, causing a current to flow through the drive transistor T1.
In the next auto-zero period J2, the drive line is pulled up to high level, causing the switching transistor T2 to non-conducting. At this time, the scan line is at low level, causing the sampling transistor T4 to conduct, and a reference potential Vref to be applied to the data line. As the current flow to the drive transistor T1 is shut off, the gate potential of the drive transistor T1 increases. However, when this potential rises to a level VDD-|Vth|, the drive transistor T1 will non-conducting, causing the potential to stabilize.
In the next data writing period J3, the auto-zero line swings to a high level, causing the switching transistor T3 to be non-conducting. Further, the data line potential is reduced from Vref by ΔVdata. This change in the data line potential causes the gate potential of the drive transistor T1 to decrease by ΔVg1 via the capacitor C1.
In the correction period J4 set particularly within the data writing period J3, a μ correction line, connected to the gate of the switching transistor T5, is pulled down to a low level for a short period of time, causing the switching transistor T5 to conduct. At this time, the drive transistor T1 is conducting as a result of the data writing operation, causing a current to flow from the source to the drain D of the same transistor T1. This current is negatively fed back to the connection point A with the capacitor C1 via the switching transistor T5. As a result, the input side potential of the capacitor C1 increases, causing the gate potential of the drive transistor T1 to increase. When the gate potential increases by ΔVg2, the μ correction line rises to a high level, causing the switching transistor T5 to be non-conducting.
In the light emission period J5, the scan line is pulled up to a high level, causing the sampling transistor T4 to be non-conducting. The drive line is pulled down to a low level, causing the switching transistor T2 to conduct. As a result, an output current flows through the drive transistor T1 and the light-emitting device OLED, causing the same device OLED to start emitting light. It is to be noted that all the aforementioned periods, namely, the preparatory period J1, the auto-zero period J2, and the data writing period J3 including the correction period J4, are all allocated within one horizontal selection period (1 H) which is assigned to the pixel.
The first embodiment illustrated in FIGS. 5 and 6 includes the capabilities to cancel variations in Vth and correct variations in the mobility μ, as with the reference example illustrated in FIGS. 3 and 4. Here, the first embodiment is significantly characterized in that the current path end (drain node) of the drive transistor T1 and the input side node of the capacitor C1 are electrically connected by the switching transistor T5 during the correction of variations in the mobility μ. At this time, the sampling transistor T4 is also conducting. As a result, the drain of the drive transistor T1 and the data line are electrically connected. The data lines are typically disposed from top to bottom of the panel. Therefore, these lines have a relatively large stray capacitance. As a result, the data line potential increases at a relatively slow pace when the current from the drive transistor T1 is negatively fed back to the data line during the correction of variations in the mobility μ. As a consequence, the reduction of Vgs takes place slowly in the negative feedback operation. Therefore, the timing control of the μ correction line is performed equally slowly. This makes it possible to correct variations in the mobility μ in a stable manner even in the event of an increased wiring delay of the μ correction line resulting from a larger panel.
FIG. 7 is a circuit diagram illustrating a second embodiment of the pixel circuit associated with the embodiment of the present invention. To facilitate the understanding thereof, like components as those of the first embodiment in FIG. 5 are designated by like reference numerals. The second embodiment differs from the first embodiment in that the switching transistor T5 making up the negative feedback means is connected between the current path end (drain D) of the drive transistor T1 and the data line. The control end (gate) of the same transistor T5 is connected to the μ correction line which is arranged in parallel with the scan line. The same transistor T5 conducts in response to a control signal applied to the gate thereof during the correction period, thus connecting the drain D of the drive transistor T1 to the connection point A via the data line and further via the sampling transistor T4 which is conducting during the sampling period. As a result, the negative feedback operation is performed with electrical continuity established between the connection point A and the data line, thus providing completely the same effect as with the first embodiment.
FIG. 8 is a timing diagram used for a description of the operation of the second embodiment illustrated in FIG. 7. The second embodiment operates in the same manner as the first embodiment. That is, in the correction period J4 set within the data writing period J3, the μ correction line is pulled down to a low level for a short period of time, causing the switching transistor T5 to conduct. At this time, the drive transistor T1 is on, causing a current to flow from its source to its drain. This current flows through the switching transistor T5 onto the data line. As a result, the data line potential increases. Further, the input side potential of the capacitor C1 also increases via the sampling transistor T4 which is conducting. This causes the gate potential of the drive transistor T1 to increase. When the gate potential increases by ΔVg2, the μ correction line rises to a high level, causing the switching transistor T5 to be non-conducting.
FIG. 9 is a circuit diagram illustrating a third embodiment of the pixel circuit associated with the embodiment of the present invention. The third embodiment is basically similar to the first embodiment. Like components as those of the first embodiment are designated by like reference numerals to facilitate the understanding thereof. The third embodiment differs from the first embodiment in that a switching transistor T6 has been added. One current path end of the same transistor T6 is connected to the connection point A, whereas the other current path end thereof is connected to the reference potential Vref. The gate of the same transistor T6 is connected to a second auto-zero line. It is to be noted that the auto-zero line connected to the gate of the switching transistor T3 is denoted as a first auto-zero line particularly in FIG. 9 for distinction from the second auto-zero line.
FIG. 10 is a timing diagram used for a description of the operation of the third embodiment illustrated in FIG. 9. To facilitate the understanding thereof, like reference numerals are used to designate like components as those illustrated in the timing diagram of FIG. 6. In the first embodiment illustrated in FIGS. 5 and 6, the auto-zero and data writing operations are necessary to be carried out within one horizontal selection period (1 H). That is, the data line potential is switched between the reference potential Vref and the signal voltage ΔVdata. As a result, the auto-zero and data writing operations should be completed within one horizontal selection period. In contrast, in the present embodiment, the switching transistor T6 has been added to separate the reference potential Vref from the data line so that this potential is set to the connection point A. The switching transistor T6 makes it possible to perform the auto-zero operation ahead of the data writing operation. As a result, the signal waveform on the data line can be simplified, providing more time available for the auto-zero and data writing operations. As is clear from the timing diagram in FIG. 10, the whole of one horizontal selection period (1 H) can be spent as the data writing period J3. The timing and duration of the auto-zero period J2 can be set freely so long as the period J2 is provided prior to the horizontal selection period.
FIG. 11 is a circuit diagram illustrating a fourth embodiment of the pixel circuit associated with the embodiment of the present invention. The fourth embodiment is basically similar to and a modified version of the third embodiment illustrated in FIG. 9. In the present embodiment, the first auto-zero line connected to the gate of the switching transistor T3 and the second auto-zero line connected to the gate of the switching transistor T6 have been combined into a single common auto-zero line. This common auto-zero line is used to simultaneously control the on/off state of the switching transistors T3 and T6. This provides a reduced number of control lines arranged in parallel with the scan line.
FIG. 12 is a timing diagram used for a description of the operation of the fourth embodiment illustrated in FIG. 11. The auto-zero line swings to a low level in the auto-zero period J2. As a result, the switching transistors T3 and T6 conduct at the same time, performing the given auto-zero operation.
FIG. 13 is a circuit diagram illustrating a fifth embodiment of the pixel circuit associated with the embodiment of the present invention. The fifth embodiment is basically similar to the second embodiment illustrated in FIG. 7. The fifth embodiment differs from the second embodiment in that the switching transistor T6 for the auto-zero operation has been added between the reference potential Vref and the connection point A. In this respect, the fifth embodiment is similar in configuration to the third embodiment illustrated in FIG. 9. The operational timing diagram of the present embodiment is similar to that in FIG. 10. As with the third embodiment, the present embodiment allows for the auto-zero operation to be performed ahead of the data writing operation. As a result, the signal waveform on the data line can be simplified, providing more time available for the auto-zero and data writing operations.
FIG. 14 is a circuit diagram illustrating a sixth embodiment of the pixel circuit associated with the embodiment of the present invention. The sixth embodiment is basically similar to the fifth embodiment illustrated in FIG. 13. The sixth embodiment differs from the fifth embodiment in that the auto-zero line is shared by the switching transistors T3 and T6. In this respect, the sixth embodiment is similar to the fourth embodiment. The present embodiment allows for the auto-zero operation to be performed with a single auto-zero line, providing a reduced number of control lines as a whole.
It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.
Patent Application
20080048955
