Patent Grant
8896591
1. Field of the Invention
The present invention generally relates to a pixel circuit, and in particular, to a pixel circuit capable of improving color shift and frame flicker.
2. Description of Related Art
Liquid crystal displays (LCDs), having advantages of good space utilization, low power consumption, and no radiation etc., have gradually become mainstream products in the market. However, the market tends to develop LCDs having wide viewing angle, high resolution, and large scale.
Among them, the technical requirement of the wide viewing angle is originated from the circumstance that when the LCD is viewed at a large viewing angle, a severe color shift of the image occurs, and thus the color is distorted. Therefore, under the trend of more vivid frames, the technique of the wide viewing angle is absolutely necessary. The so-called color shift is that when viewing the LCD at a large viewing angle, the frame becomes whiter, that is, the larger viewing angle at the LCD which is viewed results in more serious problem of higher brightness of middle and low grayscale. So, if the higher brightness may be reduced, the circumstance of color shift may be effectively solved. In the conventional design, the scan lines or data lines are increased twice so as to achieve the better effect, but the cost of gate driver ICs and data driver ICs may be added.
In order to solve the circumstance of color shift, in the conventional art, a multi switch (MS) pixel structure is proposed. In brief, each pixel unit is divided into two display regions in the MS pixel structure, so as to effectively solve the circumstance of color shift. However, although the conventional MS pixel structure may effectively solve the circumstance of color shift, the frame flicker may be caused.
Accordingly, the present invention is directed to a pixel circuit, capable of effectively improving the frame flicker problem.
The present invention provides a pixel circuit having a scan line, a data line, and at least a first pixel and a second pixel wherein the first pixel and the second pixel respectively include a first sub-pixel and a second sub-pixel. The first sub-pixel may be coupled to the scan line and the data line, so as to determine whether to be enabled according to a first scan signal transmitted on the scan line, and to determine whether to be driven according to a data signal transmitted on the data line. In addition, the second sub-pixel may be coupled to the scan line, so as to determine whether to be enabled according to the first scan signal. When the first scan signal is in a pre-charged period, the data signal is in a first state. During a time interval after a pre-charged period is over and before the first scan signal enters a turn-on period, the data signal is in a second state. Voltage polarities of the first state and the second state are opposite.
In addition, the first sub-pixel may include a first transistor, a first liquid crystal capacitor, and a first storage capacitor. A source of the first transistor is coupled to the data line, and a gate of the first transistor is coupled to the scan line. In addition, the first liquid crystal capacitor may be used to ground a drain of the first transistor, and the first storage capacitor may be used to couple the drain of the first transistor to a common voltage line, so as to receive a common voltage. Comparatively, the second sub-pixel includes a second transistor, a second liquid crystal capacitor, and a second storage capacitor. A gate of the second transistor is coupled to the scan line, and a source of the second transistor is coupled to the data line through a switch, wherein the switch is adapted to determine whether or not to turn on according to a second scan signal. The second liquid crystal capacitor is used to ground a drain of the second transistor. The second storage capacitor is used to couple the drain of the second transistor to a common voltage line, so as to receive a common voltage.
In an embodiment of the present invention, the switch includes a source coupled to the data line, a gate for receiving the second scan signal, and a drain coupled to the source of the second transistor.
In the structure of the present invention, a complete pixel is divided into two sub-pixels (a first sub-pixel and a second sub-pixel), which is different from the conventional design to improve color shift by increasing gate driver ICs and data driver ICs, thereby saving the cost. Particularly, the driving method of the present invention achieves that the two sub-pixels have two voltages and opposite polarities, thereby further solving the frame flicker problem.
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
The scans line G1, G2, and G3 . . . and the data lines D1, D2, and D3 . . . may enclose a plurality of display regions on the display panel 100, and the display regions are arranged in an array. One pixel is disposed in each display region, thereby forming a pixel array on the display panel 100. Particularly, each pixel is at least divided into a first sub-pixel and a second sub-pixel. In this embodiment, the first sub-pixels and the second sub-pixels of the pixels in an Mth row along the first direction are all coupled to an Mth scan line of the scan lines. In addition, the first sub-pixels and the second sub-pixels of the pixels in an Nth column along the second direction receive the data signal transmitted on an Nth data line of the data lines, in which M and N are positive integers.
For example, the pixels respectively enclosed by the scan lines G1˜G3 and the data lines D1˜D3 are 111˜113, 121˜123, and 131˜133. The first sub-pixels 111a, 112a, and 113a and the second sub-pixels 111b, 112b, and 113b of the pixels 111, 112, and 113 are all coupled to the scan line G1, and determined whether to be enabled according to a first scan signal transmitted on the scan line G1. Comparatively, the first sub-pixels 111a, 121a, and 131a and the second sub-pixels 111b, 121b, and 131b of the pixels 111, 121, and 131 receive the data signal transmitted on the data line. Particularly, the first sub-pixels 111a, 121a, and 131a are all coupled to the data line D1, so the first sub-pixels 111a, 121a, and 131a after being enabled by the first scan signal may be driven according to the data signal transmitted on the data line D1. The second sub-pixels 111b and 121b are coupled to the data line D1 through the switch transistors 160 and 170. The switch determines whether or not to turn on according to the second scan signal.
Accordingly, the gate of the first transistor 140 in the first sub-pixel 111a is coupled to the scan line G1 and receives the scan signal transmitted on the scan line G1, and the source of the first transistor 140 is coupled to the data line D1 and receives the data signal transmitted on the data line D1. In addition, the first liquid crystal capacitor 141 grounds the drain of the first transistor 140, and the first storage capacitor 142 couples the drain of the first transistor 140 to a common voltage line and receives a common voltage Vcom.
In addition, the gate of the second transistor 150 in the second sub-pixel 111b is coupled to the scan line G1 and receives the scan signal transmitted on the scan line G1, and the source of the second transistor 150 is coupled to the data line D1 through the switch transistor 160. It may be clearly seen from
During t2, the scan signal SG1 may be dropped, and the scan signal SG2 sustains its original state. In addition, the data signal SD1 may transit to a second state. At this time, the first transistor 140 and the second transistor 150 may be turned off, and the state of the first storage capacitor 142 remains unchanged. In this embodiment, the voltage polarities of the first state and the second state are opposite.
During t3, the scan signal SG1 may be enabled again to enter a turn-on period. At the same time, the scan signal SG2 may also be enabled to enter the pre-charged period. In addition, the data signal SD1 restores the first state. At this time, the scan signals SG1 and SG2 are enabled, the second transistor 150 and the first transistors 140 and 160 may all be turned on, such that the data signal SD1 in first state may be transferred to the first liquid crystal capacitor 141, the second liquid crystal capacitor 151, the first storage capacitor 142, and the second storage capacitor 152 through the second transistor 150, and the first transistors 140 and 160.
Next, during t4, the pre-charged period of the scan signal SG2 is over, and the scan signal SG2 transits to a low potential, and the scan signal SG1 remains at a high potential. In addition, the data signal SD1 also transits from the first state to the second state. Here, the first transistor 160 transits to be turn-off, but the first transistor 140 and the second transistor 150 remain the turn-on state. Therefore, the data signal SD1 in the second state may be transferred to the first liquid crystal capacitor 141 and the first storage capacitor 142 through the first transistor 140, such that the voltages of the first liquid crystal capacitor 141 and the first storage capacitor 142 are in the second state (the negative polarity state in this embodiment). In contrast, the first transistor (switch transistor) 160 is turned off, so the second liquid crystal capacitor 151 and the second storage capacitor 152 still remain in the first state (the positive polarity state in this embodiment), such that the polarities of the second sub-pixel 111b and the first sub-pixel 111a are opposite, thereby realizing the operation of dot inversion. Through the operation of dot inversion, the frame flicker of the LCD may be reduced.
Although only the waveforms and the illustrations of the scan signals SG1 and SG2 are provided in the above description, those of ordinary skill in the art may deduce the operating manner of other pixels with reference to the above description, and the details will not be described in the present invention. In addition, the waveform of the data signal in the present invention is not limited to the above description. For example, the waveform diagrams as shown in the
It may be known from the driving method of the first embodiment that the pixels in the last row along the first direction may not be displayed normally unless the second sub-pixels of the pixels in the last row along the first direction are driven by the first sub-pixels in the next row. Therefore, a row of pixels and a scan line GM+1 below a display region AA of the display panel 600 must be added, so as to be correspondingly coupled to the pixels in the last row along the first direction respectively. In order to obtain a symmetrical panel design, a row of pixels and a scan line G0 are added above the display region AA of the display panel 600, so as to be correspondingly coupled to the pixels in the first row along the first direction respectively, thereby obtaining the most complete architecture.
The flicker problem has been effectively overcome in the first embodiment. However, in the first embodiment, the polarity of each data signal must be continually switched in the same image, which results in the difficulty in operation. Therefore, an architecture diagram of another display panel as shown in
In addition, the second sub-pixel of each pixel along the second direction is coupled to the first sub-pixel of next pixel. For example, the second sub-pixels 711b and 721b are coupled to the first sub-pixels 721a and 731a of the pixels 721 and 731.
Accordingly, the gate of the first transistor 740 of the first sub-pixel 711a is coupled to the scan line G1 and receives the scan signal transmitted on the scan line G1, and the source of the first transistor 740 of the first sub-pixel 711a is coupled to the data line D0 and receives the data signal transmitted on the data line D0. In addition, the first liquid crystal capacitor 741 grounds the drain of the first transistor 740, and the first storage capacitor 742 couples the drain of the first transistor 740 to a common voltage line and receive the common voltage Vcom.
In addition, the gate of the second transistor 750 of the second sub-pixel 711b is coupled to the scan line G1 and receives the scan signal transmitted on the scan line G1, and the source of the second transistor 750 of the second sub-pixel 711b is coupled to the data line D1 through switch transistor 760. It may be clearly seen from
During t6, the scan signal SG2 transits to the low potential, and the scan signal SG1 remains at the high potential. In addition, the data signal SD1 is the first data signal (the positive polarity state in this embodiment, and the voltage level is +B during t6). At this time, the first transistor 760 may transit to the turn-off, but the second transistor 750 and the first transistor 770 may sustain the turn-on state. Therefore, the first data signal SD1 may be transferred to the first liquid crystal capacitor (not shown) and the first storage capacitor (not shown) of the first sub-pixel 712a through the first transistor 770. It may be deduced from the above that when the data signal SD2 is the second data signal (the voltage level is −B in this embodiment), the second data signal SD2 may be transferred to the first liquid crystal capacitor (not shown) and the first storage capacitor (not shown) of the first sub-pixel 713a. Therefore, at this time, the first sub-pixel 712a of the pixel 712 has the positive polarity and the second sub-pixel 712b has the negative polarity, i.e., the polarities of the first sub-pixel 712a and the second sub-pixel 712b are opposite.
During t7, the scan signal SG2 may be enabled, and at the same time, the scan signal SG3 may also be enabled. In addition, the data signal SD1 is the first data signal (the positive polarity state in this embodiment, and the voltage level is +A during t7). At this time, the scan signals SG2 and SG3 are enabled, the first transistors 760 and 790 and the second transistor 780 may be turned on, such that the first data signal SD1 may be transferred to a first liquid crystal capacitor 761 and a first storage capacitor 762 of a first sub-pixel 721a, and a second liquid crystal capacitor (not shown) and a second storage capacitor (not shown) of a second sub-pixel 722b through the first transistors 760 and 790 and the second transistor 780. It may be deduced from the above that when the data signal SD2 is the second data signal (in this embodiment, the voltage level is −A here), such that the second data signal SD2 may be transferred to a first liquid crystal capacitor (not shown) and a first storage capacitor (not shown) of a first sub-pixel 722a and a second liquid crystal capacitor (not shown) and a second storage capacitor (not shown) of a second sub-pixel 723b.
Next, during t8, the scan signal SG3 transits to the low potential, and the scan signal SG2 remains at the high potential. In addition, the data signal SD1 is the first data signal (the positive polarity state in this embodiment, and the voltage level is +B during t8). At this time, the first transistor 790 may transit to the turn-off, but the first transistor 760 and the second transistor 780 sustain the turn-on state. Therefore, the first data signal SD1 may be transferred to the first liquid crystal capacitor 761 and the first storage capacitor 762 through the first transistor 760. It may be deduced from the above that when the data signal SD2 is the second data signal (the voltage level is −B in this embodiment), the second data signal SD2 may be transferred to the first liquid crystal capacitor (not shown) and the first storage capacitor (not shown) of the first sub-pixel 722a. Therefore, the first sub-pixel 722a of the pixel 722 has the negative polarity, and the second sub-pixel 722b of the pixel 722 has the positive polarity, i.e., the polarities of the first sub-pixel 722a and the second sub-pixel 722b are opposite.
Further, when switching frames, the display panel 700 switches the polarities of the first data signal and the second data signal in sync. In the above operating manner, the polarities of the first sub-pixel and the second sub-pixel of the same pixel are made to be opposite, so the display panel 700 exhibits the driving method like the dot inversion, thereby reducing the frame flicker of the LCD.
It may be known from the above that each data line can only drive one sub-pixel of a left pixel and a right pixel disposed beside the data line. In order to keep the completeness in driving, the above driving method includes disposing a data line D0, such that the pixels in the first column along the second direction may be displayed normally. In other words, a data line DN+1 (not shown) may also be disposed in the pixel array 710, such that the pixels in the last column along the second direction may be displayed normally. It should be noted that the architecture diagram of the display panel 700 is only one of the examples of this embodiment, and the present invention is not limited to the above architecture.
Although the waveforms and the illustrations of the scan signals SG1, SG2, and SG3 are provided, those of ordinary art in the field may deduce the operating manners of other pixels through the above illustrations, so the details will not be described in the present invention.
It may be known from the above that in this embodiment, the polarities of the data signals in the same data line are the same in the same frame. Therefore, in this embodiment, the dot inversion operation may be realized by using a simple driving method.
It may be known from the driving method of the third embodiment that the pixels in the last row along the first direction may not be displayed normally unless the second sub-pixels of the pixels in the last row along the first direction are driven by the first sub-pixels in the next row. Therefore, a row of pixels and a scan line GM+1 below a display region AA of the display panel 900 must be added, so as to be correspondingly coupled to the pixels in the last row along the first direction respectively. In order to obtain a symmetrical panel design, a row of pixels and a scan line G0 are added above the display region AA of the display panel 900, so as to be correspondingly coupled to the pixels in the first row along the first direction respectively, thereby obtaining the most complete architecture.
It may be known from the above that through the characteristics of the scan signal, the two sub-pixels of one pixel may have difference voltages, which may effectively solve the color shift problem, and the voltage polarities of the data signals transmitted on neighbouring data lines are opposite, such that the driving voltages of the first sub-pixel and the second sub-pixel of each pixel are opposite, thereby reducing the frame flicker. In addition, the driving method of this embodiment is a column inversion. When switching frames, the display panel switches the voltage polarity of each data signal in sync, such that display panel exhibits the driving method like the dot inversion, thereby overcoming the disadvantage of the power consumption resulting from the dot inversion and having the advantage of the dot inversion that the frame flicker is reduced. In order to achieve the normal display of the panel and the symmetry of the panel design, a row of pixels and a scan line are added above and below the display region respectively, so as to achieve the completeness of the design.
Based on the organization of the above descriptions, the present invention further provides several driving methods of a display panel, as shown in
Referring to
Referring to
To sum up, the present invention provides a pixel circuit, a display panel, and a driving method thereof. The present invention needs not increase gate driver ICs and data driver ICs to achieve that one pixel is divided into a first sub-pixel and a second sub-pixel, and the two sub-pixels of the pixel have two voltages. This pixel architecture is referred to as Multi Switch (MS). With this design, the sub-pixel region with larger voltage can maintain the brightness of the high grayscale, and the sub-pixel region with the smaller voltage value can make middle and low grayscales darker, thereby improving the color shift. However, the present invention is characterized in that the polarities of the sub-pixels are opposite through the polarities of the data signals of the data line, so as to reduce the frame flicker. MSHD in conjunction with column inversion can achieve the same driving effect of the dot inversion, and requires a lower power, thereby reducing the power consumption.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
| Number | Date | Country | Kind |
|---|---|---|---|
| 97116533 A | May 2008 | TW | national |
This application is a Divisional of and claims the priority benefit of U.S. patent application Ser. No. 12/257,397, filed on Oct. 24, 2008, now pending, which claims the priority benefits of Taiwan application Serial No. 97116533, filed on May 5, 2008. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification.
| Number | Name | Date | Kind |
|---|---|---|---|
| 20070164957 | Hsieh et al. | Jul 2007 | A1 |
| 20090009449 | Uchida et al. | Jan 2009 | A1 |
| 20090051641 | Irie et al. | Feb 2009 | A1 |
| 20090195561 | Iisaka et al. | Aug 2009 | A1 |
| Number | Date | Country | |
|---|---|---|---|
| 20140240309 A1 | Aug 2014 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 12257397 | Oct 2008 | US |
| Child | 14269207 | US |
