Patent Application
20180204536
The present application claims priority to the Chinese Patent Application No. 201710036348.X, filed on Jan. 17, 2017, entitled “PIXEL CIRCUITS AND METHODS FOR DRIVING THE SAME AND DISPLAY APPARATUSES AND METHODS FOR DRIVING THE SAME,” which is incorporated herein by reference in its entirety.
The present disclosure relates to the field of display technology, and more particularly, to a pixel circuit and a method for driving the same and a display apparatus and a method for driving the same.
With the development of display technology, requirements for display effects of display apparatuses are gradually increased. When a moving image is displayed on a display apparatus, a flicker phenomenon that occurs when a first frame of image and a second frame of image partly overlap with each other has a great influence on the display effects, which thus has always been a hot research spot for those skilled in the art.
In order to at least partially solve or alleviate the above-mentioned problems, embodiments of the present disclosure provide a pixel circuit and a method for driving the same and a display apparatus and a method for driving the same.
In order to achieve the above purposes, the following technical solutions are used in the embodiments of the present disclosure.
In a first aspect, there is provided a pixel circuit, comprising an energy storage circuit, a driving circuit, a display circuit and a reset circuit, wherein the energy storage circuit is connected to a first scanning signal line, a data signal line and the driving circuit respectively, and is configured to store a data signal input through the data signal line under the control of the first scanning signal line; the driving circuit is further connected to a second scanning signal line and the display circuit, and is configured to drive the display circuit to display a picture under the control of the second scanning signal line; the display circuit is further connected to a second voltage terminal, and is configured to display a picture under the control of the driving circuit and the second voltage terminal; and the reset circuit is connected to a third scanning signal line, the data signal line and the display circuit respectively, and is configured to set a reset signal input through the data signal line to the display circuit under the control of the third scanning signal line to reset a voltage in the display circuit.
In some embodiments, the energy storage circuit comprises a first transistor and a first capacitor, wherein the first transistor has a gate connected to the first scanning signal line, a first electrode connected to the data signal line and a second electrode connected to the driving circuit; and the first capacitor has a first terminal connected to the second electrode of the first transistor and the driving circuit respectively, and a second terminal connected to a first voltage terminal.
In some embodiments, the driving circuit comprises a second transistor having a gate connected to the second scanning signal line, a first electrode connected to the energy storage circuit and a second electrode connected to the display circuit.
In some embodiments, the display circuit comprises a liquid crystal capacitor and a second capacitor, wherein the liquid crystal capacitor has a first terminal connected to the driving circuit and a second terminal connected to the second voltage terminal, wherein the first terminal is a pixel electrode and the second terminal is a common electrode; and the second capacitor has a first terminal connected to the driving circuit and a second terminal connected to a first voltage terminal.
In some embodiments, the reset circuit comprises a third transistor having a gate connected to the third scanning signal line, a first electrode connected to the data signal line and a second electrode connected to the display circuit.
In some embodiments, when the display circuit comprises a liquid crystal capacitor and a second capacitor, the third transistor has a second electrode connected to a first terminal of the liquid crystal capacitor and a first terminal of the second capacitor respectively.
In some embodiments, both the first voltage terminal and the second voltage terminal are connected to a common voltage terminal.
In a second aspect, there is provided a display apparatus comprising the pixel circuit according to the first aspect.
In a third aspect, there is provided a method for driving the pixel circuit according to the first aspect, wherein a frame of image comprises a charging phase, a reset phase and a display phase, and in the frame of image, the method comprises: in the charging phase, inputting a turn-on signal through the first scanning signal line to control the energy storage circuit to be turned on, and storing, by the energy storage circuit which is turned on, a data signal input through the data signal line; in the reset phase, inputting a turn-on signal through the third scanning signal line to control the reset circuit to be turned on, and outputting, by the reset circuit which is turned on, a reset signal input through the data signal line to the display circuit, to reset a voltage of the display circuit; in the display phase, inputting a turn-off signal through the first scanning signal line to control the energy storage circuit to be turned off; inputting a turn-off signal through the third scanning signal line to control the reset circuit to be turned off; inputting a turn-on signal through the second scanning signal line to control the driving circuit to be turned on, releasing, by the energy storage circuit, the data signal stored therein to the display circuit through the driving circuit which is turned on, to charge the display circuit and drive the display circuit to display a picture; and inputting a turn-off signal through the second scanning signal line to control the driving circuit to be turned off and control the display circuit to hold picture display.
In some embodiments, the method further comprises: in the charging phase, inputting the turn-on signal through the first scanning signal line to control the first transistor to be turned on and storing the data signal input through the data signal line to the first capacitor; in the reset phase, inputting the turn-on signal through the third scanning signal line to control the third transistor to be turned on and outputting the reset signal input through the data signal line to the liquid crystal capacitor and the second capacitor through the third transistor to reset voltages across the liquid crystal capacitor and the second capacitor; in the display phase, inputting the turn-off signal through the first scanning signal line to control the first transistor to be turned off; inputting the turn-off signal through the third scanning signal line to control the third transistor to be turned off; inputting the turn-on signal through the second scanning signal line to control the second transistor to be turned on, releasing, by the first capacitor, the data signal stored therein to the liquid crystal capacitor and the second capacitor through the second transistor to charge the liquid crystal capacitor and the second capacitor, and displaying, by the liquid crystal capacitor, a picture under the driving of the data signal and a signal at the second voltage terminal; and inputting the turn-off signal through the second scanning signal line to control the second transistor to be turned off, and outputting, by the second capacitor, the data signal stored therein to the liquid crystal capacitor to control the liquid crystal capacitor to hold picture display.
In some embodiments, when data signals input in two adjacent frames of image have opposite polarities, polarities of reset signals are same as those of the corresponding data signals.
In some embodiments, the reset signal has a voltage value of 0V or is grounded.
According to a fourth aspect, there is provided a method for driving the display apparatus according to the second aspect, wherein a frame of image comprises a charging phase, a reset phase and a display phase, and in the frame of image, the method comprises: in the charging phase, inputting turn-on signals sequentially through a plurality of first scanning signal lines to control energy storage circuits to be turned on progressively, and storing, by each of the energy storage circuits which are turned on, a data signal input through a corresponding data signal line; in the reset phase, inputting turn-on signals simultaneously through a plurality of third scanning signal lines to control reset circuits to be turned on, and outputting, by each of the reset circuits which are turned on, a reset signal input through a corresponding data signal line to a corresponding display circuit, to reset a voltage of the display circuit; in the display phase, inputting turn-off signals simultaneously through the plurality of first scanning signal lines to control all the energy storage circuits to be turned off; inputting turn-off signals simultaneously through the plurality of third scanning signal lines to control all the reset circuits to be turned off; inputting turn-on signals simultaneously through a plurality of second scanning signal lines to control all the driving circuits to be turned on, releasing, by each of the energy storage circuits, the data signal stored therein to a corresponding display circuit through a corresponding driving circuit of the driving circuits which are turned on, to charge the display circuit and drive the display circuit to display a picture; and inputting turn-off signals simultaneously through the plurality of second scanning signal lines to control the driving circuits to be turned off and control the display circuits to hold picture display.
In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or in the related art, the accompanying drawings, which are intended to be used in the description of the embodiments or related art, will be briefly described below. It will be apparent that the accompanying drawings in the following description are merely some embodiments of the present disclosure, and other accompanying drawings can further be obtained by those of ordinary skill in the art according to the accompanying drawings without contributing any creative work.
The technical solutions in the embodiments of the present disclosure will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present disclosure, and it will be apparent that the described embodiments are merely a part of the embodiments of the present disclosure instead of all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present disclosure without contributing any creative work are within the protection scope of the present disclosure.
In the related art, there is provided a display apparatus comprising a plurality of pixel units which are arranged in an array. As shown in
A specific display principle is as follows. A first scanning signal line IN1 controls the first transistor TFT1 to be turned on and the first capacitor C1 stores a data signal input through a data signal line D; the first scanning signal line IN1 controls the first transistor TFT1 to be turned off, a second scanning signal line IN2 controls the second transistor TFT2 to be turned on, and the first capacitor C1 outputs a first data signal to the liquid crystal capacitor LC and the second capacitor C2 to drive the liquid crystal capacitor LC to display a picture; the second scanning signal line IN2 controls the second transistor TFT2 to be turned off; and the second capacitor C2 outputs the data signal stored therein to the liquid crystal capacitor LC to drive the liquid crystal capacitor LC to hold picture display.
During display, as charges during display of a previous frame are stored still in the liquid crystal capacitor LC, residual charges in the liquid crystal capacitor LC are Qp=Cp×Vp, where Cp is capacitance of the liquid crystal capacitor LC, and Vp is a residual voltage across the liquid crystal capacitor LC. Charges supplied from the first capacitor C1 to the liquid crystal capacitor LC are Q=C×Vd, where C is capacitance of the first capacitor C1 and Vd is an input voltage across the liquid crystal capacitor LC during the display. In this way, total charges in the liquid crystal capacitor LC are Qt=Q+Qp=C×Vd+Cp×Vp=Vd′×(C+Cp), where Vd′ is a voltage released from the first capacitor C1 to the liquid crystal capacitor LC. Thereby, Vd′=(C×Vd+Cp×Vp)/(C+Cp) may be deduced. As a polarity of Vp is opposite to a polarity of Vd, Vp may offset Vd, which thus may result in a considerable voltage loss. In addition, in a case that the polarity of Vp is opposite to the polarity of Vd, it needs to increase C to ensure normal display. However, if C becomes large, the TFT1 for charging C1 is also increased, which may cause a large loss of an aperture rate of sub-pixels.
In order to at least partially alleviate or solve the problem, the embodiments of the present disclosure provide a pixel circuit, as shown in
The energy storage circuit 10 is connected to a first scanning signal line IN1, a data signal line D, a first voltage terminal V1 and the driving circuit 20 respectively, and is configured to store a data signal input through the data signal line D under the control of the first scanning signal line IN1.
The driving circuit 20 is further connected to a second scanning signal line IN2 and the display circuit 30 and is configured to drive the display circuit 30 to display a picture under the control of the second scanning signal line IN2.
The display circuit 30 is further connected to the first voltage terminal V1 and a second voltage terminal V2 and is configured to display a picture under the control of the driving circuit 20 and the second voltage terminal V2.
The reset circuit 40 is connected to a third scanning signal line IN3, the data signal line D and the display circuit 30 respectively, and is configured to set a reset signal input through the data signal line D to the display circuit 30 under the control of the third scanning signal line IN3 to reset a voltage in the display circuit 30.
The reset signal is not specifically limited, as long as a residual voltage in the display circuit 30 can be reduced.
In this way, the reset circuit 40 is added in the pixel circuit, and before the driving circuit 20 and the second voltage terminal V2 control the display circuit 30 for display, the reset circuit 40 outputs the reset signal input through the data signal line D to the display circuit 30 under the control of the third scanning signal line IN3 to reset the voltage in the display circuit 30 so that a polarity of the voltage in the display circuit 30 is same as a polarity of the data signal input through the data signal line D or reset the voltage in the display circuit 30 to 0V, which prevents the voltage in the display circuit 30 from offsetting the data signal input through the data signal line D, thereby reducing the voltage loss. The embodiments of the present disclosure can increase the aperture ratio of the pixels when normal display can be ensured without increasing the energy storage capacity of the energy storage circuit 10.
A specific structure of each circuit in
Specifically, as shown in
The first capacitor C1 has a first terminal connected to the second electrode of the first transistor TFT1 and the driving circuit 20 respectively, and a second terminal connected to the first voltage terminal V1.
The driving circuit 20 comprises a second transistor TFT2 having a gate connected to the second scanning signal line IN2, a first electrode connected to the energy storage circuit 10 and a second electrode connected to the display circuit 30.
The display circuit 30 comprises a liquid crystal capacitor LC and a second capacitor C2. The liquid crystal capacitor LC has a first terminal connected to the driving circuit 20 and a second terminal connected to the second voltage terminal V2, wherein the first terminal is a pixel electrode and the second terminal is a common electrode.
The second capacitor C2 has a first terminal connected to the driving circuit 20 and a second terminal connected to the first voltage terminal V1.
The reset circuit 40 comprises a third transistor TFT3 having a gate connected to the third scanning signal line IN3, a first electrode connected to the data signal line D and a second electrode connected to the display circuit 30.
Further, specifically, the third transistor TFT3 has a second electrode connected to the first terminal of the liquid crystal capacitor LC and the first terminal of the second capacitor C2 respectively.
Further, in another embodiment illustrated in
It is to be noted that the transistors described above may be N-type transistors or P-type transistors, or may also be enhancement mode transistors or depletion mode transistors; the first electrodes of the transistors may be sources, and the second electrodes of the transistors may be drains, or the first electrodes of the transistors may be drains, and the second electrodes of the transistors may be sources, and the present disclosure is not limited thereto.
Turn-on and turn-off conditions of each of the transistors in the pixel circuits shown in
In the charging phase P1, IN1=1, IN2=0 and IN3=0, where “0” represents a low level, and “1” represents a high level.
At this time, as the first signal line IN1 outputs a high level, the first transistor TFT1 is turned on, and the first capacitor C1 stores the data signal Vd input through the data signal line D, so that the charges on the first capacitor C1 are Q=C×Vd, where C is the capacitance of the first capacitor C1. As both the second signal line IN2 and the third signal line IN3 output a low level, both the second transistor TFT2 and the third transistor TFT3 are turned off.
In the reset phase P1, IN1=0, IN2=0 and IN3=1.
At this time, as the third signal line IN3 outputs a high level, the third transistor TFT3 is turned on, and the reset signal Vr input through the data signal line D is output to the liquid crystal capacitor LC and the second capacitor C2 through the third transistor TFT3, so that the charges on the liquid crystal capacitor LC are Qp=Cp×Vr, where Cp is the capacitance of the liquid crystal capacitor LC. As both the second signal line IN2 and the first signal line IN1 output a low level, both the second transistor TFT2 and the first transistor TFT1 are turned off. It should be noted that when the voltage across the liquid crystal capacitor LC is reset, a reset process is also completed for the voltage across the second capacitor C2.
In the display phase P3, the display phase P3 is divided into two phases.
In a charging display phase P31, IN1=0, IN2=1 and IN3=0.
At this time, as the second signal line IN2 outputs a high level, the second transistor TFT2 is turned on, the first capacitor C1 releases the data signal Vd stored therein to the liquid crystal capacitor LC and the second capacitor C2 through the second transistor TFT2 to charge the liquid crystal capacitor LC and the second capacitor C2, and the liquid crystal capacitor LC displays a picture under the driving of the data signal Vd and a signal at the second voltage terminal V2. In this phase, the total charges in the liquid crystal capacitor LC are Qt=Q+Qp=C×Vd+Cp×Vr=Vd′×(C+Cp), where Vd′ is the voltage released from the first capacitor C1 to the liquid crystal capacitor LC. Thereby, Vd′=(C×Vd+Cp×Vr)/(C+Cp) may be deduced. As the reset signal Vr and the data signal Vd input through the data signal line D have the same polarity, there is no phenomenon that Vr and Vd offset each other, so that the voltage loss can be reduced. In this way, there is no need to increase the storage capacity of the first capacitor C1 to ensure the normal display, and therefore the aperture ratio of the sub-pixels can be increased. It should be noted that a value of the reset signal Vr should be selected reasonably according to practical situations of the pixel circuit.
In addition, if the reset signal Vr input through the data signal line D is Vr=0V, the residual charges in the liquid crystal capacitor LC are 0V, charges input to the liquid crystal capacitor LC are the same in various frames, and Qt=Q+Qp=C×Vd+0, which can minimize the voltage loss and enable effects of the picture display to be optimal.
In a hold display phase P32, IN1=1, IN2=0 and IN3=0.
At this time, as the second signal line IN2 inputs a low level, the second transistor TFT2 is turned off, and the first capacitor C1 stops supplying power to the display circuit 30. The second capacitor C2 outputs the data signal stored therein to the liquid crystal capacitor LC so that the liquid crystal capacitor LC holds picture display.
In addition, as the first signal line IN1 outputs a high level, the first transistor TFT1 is turned on, and the first capacitor C1 stores the data signal Vd input through the data signal line D. As an input terminal of the third signal line IN3 outputs a low level, the third transistor TFT3 is turned off.
In this way, a hold display phase P32 of a Uth frame is overlapped with a charging phase P1 of a (U+1)th frame, so as to prevent a picture displayed in the Uth frame from being partially overlapped with a picture displayed in the U+1th frame, which well eliminates the flicker problem in the screen.
It is to be noted that, firstly, the turn-on and turn-off processes of the transistors in the above embodiments are described by taking all the transistors being N-type transistors as an example. When all the transistors are P-type transistors, it needs to reverse various control signals in
Secondly, when the voltage in the display circuit 30 is not reset by the reset circuit 40, a correspondence relationship between a ratio of the capacitance of the first capacitor C1 relative to the capacitance of the liquid crystal capacitor LC and an actual value of a received voltage across the liquid crystal capacitor LC when the input data signal is Vd=8V is experimentally obtained, as shown in Table 1. After the voltage in the display circuit 30 is reset by the reset circuit 40, a correspondence relationship between a ratio of the capacitance of the first capacitor C1 relative to the capacitance of the liquid crystal capacitor LC and an actual value of a received voltage across the liquid crystal capacitor LC when the input data signal is Vd=8V is experimentally obtained, as shown in Table 2. It can be seen from the comparison between Table 1 and Table 2 that reset of the voltage in the display circuit 30 by the reset circuit 40 before the display can reduce the requirements for the capacity of the first capacitor C1, thereby reducing a size of the first thin film transistor TFT1 connected to the first capacitor C1 to achieve the effect of increasing the aperture ratio of the sub-pixels. After the reset circuit 40 is added in the pixel circuit, a range of C:Cp=1:1-2:1 can well ensure normal display of the sub-pixels.
The embodiments of the present disclosure further provide a method for driving the pixel circuit described above, wherein a frame of image comprises a charging phase P1, a reset phase P2 and a display phase P3, and in the frame of image, the method comprises:
in the charging phase P1,
inputting a turn-on signal through the first scanning signal line IN1 to control the energy storage circuit 10 to be turned on, and storing, by the energy storage circuit 10 which is turned on, a data signal input through the data signal line D;
in the reset phase P2,
inputting a turn-on signal through the third scanning signal line IN3 to control the reset circuit 40 to be turned on, and outputting, by the reset circuit 40 which is turned on, a reset signal input through the data signal line D to the display circuit 30, to reset a voltage of the display circuit 30;
in the display phase P3,
in a charging display phase P31, inputting a turn-off signal through the first scanning signal line IN1 to control the energy storage circuit 10 to be turned off;
inputting a turn-off signal through the third scanning signal line IN3 to control the reset circuit 40 to be turned off;
inputting a turn-on signal through the second scanning signal line IN2 to control the driving circuit 20 to be turned on, releasing, by the energy storage circuit 10, the data signal stored therein to the display circuit 30 through the driving circuit 20 which is turned on, to charge the display circuit 30 and drive the display circuit 30 to display a picture; and
in a hold display phase P32, inputting a turn-off signal through the second scanning signal line IN2 to control the driving circuit 20 to be turned off and control the display circuit 30 to hold picture display.
In this way, the reset circuit 40 is added in the pixel circuit, and before the driving circuit 20 and the second voltage terminal V2 control the display circuit 30 for display, the reset circuit 40 outputs the reset signal input through the data signal line D to the display circuit 30 under the control of the third scanning signal line IN3 to reset the voltage in the display circuit 30 so that a polarity of the voltage in the display circuit 30 is same as a polarity of the data signal input through the data signal line D or reset the voltage in the display circuit 30 to 0V, which prevents the voltage in the display circuit 30 from offsetting the data signal input through the data signal line D, thereby reducing the voltage loss. The embodiments of the present disclosure can increase the aperture ratio of the pixels when normal display can be ensured without increasing the energy storage capacity of the energy storage circuit 10.
Specifically, as shown in
inputting the turn-on signal through the first scanning signal line IN1 to control the first transistor TFT1 to be turned on and storing the data signal input through the data signal line D to the first capacitor C1;
in the reset phase P2,
inputting the turn-on signal through the third scanning signal line IN3 to control the third transistor TFT3 to be turned on and outputting the reset signal input through the data signal line D to the liquid crystal capacitor LC and the second capacitor C2 through the third transistor TFT3 to reset voltages across the liquid crystal capacitor LC and the second capacitor C2;
wherein, when data signals input in two adjacent frames of image have opposite polarities, a polarity of a reset signal is same as that of a data signal in a frame of image;
alternatively, when the polarities of the data signals input in the two adjacent frames of image are not taken into account, the reset signal may have a voltage value of 0V or may be grounded;
in the display phase P3,
in the charging display phase P31, inputting the turn-off signal through the first scanning signal line IN1 to control the first transistor TFT1 to be turned off;
inputting the turn-off signal through the third scanning signal line IN3 to control the third transistor TFT3 to be turned off;
inputting the turn-on signal through the second scanning signal line IN2 to control the second transistor TFT2 to be turned on, releasing, by the first capacitor C1, the data signal stored therein to the liquid crystal capacitor LC and the second capacitor C2 through the second transistor TFT2 to charge the liquid crystal capacitor LC and the second capacitor C2, and displaying, by the liquid crystal capacitor LC, a picture under the driving of the data signal and a signal at the second voltage terminal V2; and
in the hold display phase P32, inputting the turn-off signal through the second scanning signal line IN2 to control the second transistor TFT2 to be turned off, and outputting, by the second capacitor C2, the data signal stored therein to the liquid crystal capacitor LC to control the liquid crystal capacitor LC to hold picture display.
The embodiments of the present disclosure further provide a display apparatus comprising any of the pixel circuits described above, and the display apparatus have the same structure and advantageous effects as those of the pixel circuits according to the embodiments described above. As the structure and the advantageous effects of the pixel circuits have been described in detail in the embodiments described above, the description thereof will not be repeated here.
The embodiments of the present disclosure further provide a method for driving a display apparatus, wherein as shown in
in the charging phase P1,
inputting turn-on signals sequentially through a plurality of first scanning signal lines IN1 to control energy storage circuits 10 to be turned on progressively, and storing, by each of the energy storage circuits 10 which are turned on, a data signal input through a corresponding data signal line D;
in the reset phase P2,
inputting turn-on signals simultaneously through a plurality of third scanning signal lines IN3 to control reset circuits 40 to be turned on, and outputting, by each of the reset circuits 40 which are turned on, a reset signal input through a corresponding data signal line D to a corresponding display circuit 30, to reset a voltage of the display circuit 30;
in the display phase P3,
in the charging display phase P31, inputting turn-off signals simultaneously through the plurality of first scanning signal lines IN1 to control all the energy storage circuits 10 to be turned off;
inputting turn-off signals simultaneously through the plurality of third scanning signal lines IN3 to control all the reset circuits 40 to be turned off;
inputting turn-on signals simultaneously through a plurality of second scanning signal lines IN2 to control all the driving circuits 20 to be turned on, releasing, by each of the energy storage circuits 10, the data signal stored therein to a corresponding display circuit 30 through a corresponding driving circuit 20 of the driving circuits 20 which are turned on, to charge the display circuit 30 and drive the display circuit 30 to display a picture; and
in the hold display phase P32, inputting turn-off signals simultaneously through the plurality of second scanning signal lines IN2 to control the driving circuits 20 to be turned off and control the display circuits 30 to hold picture display.
When turn-on signals are input simultaneously through the third scanning signal lines IN3, the reset signals inputted through the data signal lines D may be 0V or another preset value, for example, may be 1V. When the input reset signals are 1V, if the data signals input in the two adjacent frames of image have opposite polarities, the reset signal input in the (U+1)th frame is −1V when the reset signal input in the Uth frame is 1V.
Further, the second scanning signal lines IN2 may be turned on immediately while the third scanning signal lines IN3 are turned off as shown in
The embodiments of the present disclosure provide a pixel circuit and a method for driving the same and a display apparatus and a method for driving the same. The reset circuit is added in the pixel circuit, and before the driving circuit and the second voltage terminal control the display circuit for display, the reset circuit outputs the reset signal input through the data signal line to the display circuit under the control of the third scanning signal line to reset the voltage in the display circuit so that a polarity of the voltage in the display circuit is same as a polarity of the data signal input through the data signal line or reset the voltage in the display circuit to 0V, which prevents the voltage in the display circuit from offsetting the data signal input through the data signal line, thereby reducing the voltage loss. Compared with the related art, the present disclosure can increase the aperture ratio of the pixels when normal display can be ensured without increasing the energy storage capacity of the energy storage circuit.
The foregoing description is only some specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any variation or substitution which is easily reached by those skilled in the art within the technical scope disclosed in the present disclosure shall fall into the protection scope of the present disclosure. Accordingly, the protection scope of the present disclosure should be based on the protection scope of the claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201710036348.X | Jan 2017 | CN | national |
