Patent Application
20190371244
The disclosure relates generally to display technologies, and more particularly, to pixel circuits.
Emerging applications of display technologies, such as head-mounted displays (HMDs) for virtual reality (VR), augmented reality (AR), and mixed reality (MR), oftentimes have strict requirements for display quality. For example, HMDs usually require high frame rate and low latency in order to respond immediately to users' movement with updated display images, thereby providing immersion experience and preventing cybersickness, motion blur, and image broken. Moreover, high brightness, high contrast ratio, high motion contrast, and high resolution are also important specifications for HMDs. For example, high contrast ratio is important for nighttime applications in the dark environment, and high brightness is important for outdoor applications in strong ambient light.
Embodiments of pixel circuits for light emitting elements are disclosed herein.
In one example, a pixel circuit includes a pixel driver and a bridge transistor. The pixel driver is configured to receive a data signal and drive a light emitting element based on the data signal. The bridge transistor includes a gate terminal receiving a first bias signal, a source terminal coupled to the pixel driver, a drain terminal coupled to a terminal of the light emitting element, and a body terminal coupled to the source terminal or receiving the data signal. The first bias signal controls a voltage at the source terminal.
In another example, a circuit for driving a plurality of light emitting elements includes a plurality of pixel circuits and a discharge controller. Each of the plurality of pixel circuits is configured to drive one of a plurality of light emitting elements arranged in a same row and includes a pixel driver and a bridge transistor. The pixel driver is configured to receive a data signal and drive the corresponding light emitting element based on the data signal. The bridge transistor includes a gate terminal receiving a same first bias signal, a source terminal coupled to the pixel driver, a drain terminal coupled to a terminal of the light emitting element, and a body terminal coupled to the source terminal or receiving the data signal. The first bias signal controls a voltage at the source terminal. The discharge controller is coupled to the pixel drivers of each of the plurality of pixel circuits and is configured to, in response to a global discharge signal, simultaneously control discharge of the plurality of light emitting elements in the same row.
In still another example, a circuit for driving a plurality of light emitting elements includes a plurality of pixel circuits, a discharge controller, and a light emission controller. Each of the plurality of pixel circuits is configured to drive one of a plurality of light emitting elements arranged in a same row and includes a pixel driver. The pixel driver is configured to receive a data signal and drive the corresponding light emitting element based on the data signal. The discharge controller is coupled to the pixel drivers of each of the plurality of pixel circuits and configured to, in response to a global discharge signal, simultaneously control discharge of the plurality of light emitting elements in the same row. The light emission controller is coupled to a power source and the pixel drivers of each of the plurality of pixel circuits and configured to, in response to a global light emission signal, simultaneously control light emission of the plurality of light emitting elements in the same row.
The accompanying drawings, which are incorporated herein and form part of the specification, illustrate the presented disclosure and, together with the description, further serve to explain the principles of the disclosure and enable a person of skill in the relevant art(s) to make and use the disclosure.
The presented disclosure is described with reference to the accompanying drawings. In the drawings, generally, like reference numbers indicate identical or functionally similar elements. Additionally, generally, the left-most digit(s) of a reference number identifies the drawing in which the reference number first appears.
Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. It is contemplated that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It is further contemplated that the present disclosure can also be employed in a variety of other applications.
It is noted that references in the specification to “one embodiment.” “an embodiment,” “an example embodiment,” “some embodiments.” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it is contemplated that such feature, structure or characteristic may also be used in connection with other embodiments whether or not explicitly described.
In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exelusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.
As will be disclosed in detail below, among other novel features, the pixel circuits for light emitting elements, such as organic light emitting elements (OLEDs) and micro-LEDs, disclosed herein can improve a variety of display specifications. In some embodiments, the pixel circuits having global emission and discharge control for multiple light emitting elements can reduce display motion blur and increase the granularity of brightness control without significantly increasing the area of the pixel circuits. In some embodiments, the pixel circuits having isolation devices (e.g., bridge transistors) for voltage boosting can increase the withstand voltage of pixel drivers and avoid junction break-down, thereby increasing the driving voltage, contrast ratio, and display resolution of HMDs.
Control logic 104 may be any suitable hardware, software, firmware, or combination thereof, configured to receive display data 106 (e.g., pixel data) and generate control signals 108 for driving the subpixels on display 102. Control signals 108 are used for controlling writing of display data 106 to the subpixels and directing operations of display 102. For example, subpixel rendering (SPR) algorithms for various subpixel arrangements may be part of control logic 104 or implemented by control logic 104. Control logic 104 may be implemented as a standalone integrated circuit (IC) chip, such as an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). Apparatus 100 may also include any other suitable components, such as, but not limited to tracking devices 110 (e.g., inertial sensors, camera, eye tracker. GPS receiver, or any other suitable devices for tracking motion of eyeballs, facial expression, head movement, body movement, and hand gesture), input devices 112 (e.g., a mouse, keyboard, remote controller, handwriting device, microphone, scanner, etc.), and speakers (not shown).
In this embodiment, apparatus 100 may be a handheld or a VR/AR/MR device, such as a smart phone, a tablet, or a VR headset. Apparatus 100 may also include a processor 114 and memory 116. Processor 114 may be, for example, a graphics processor (e.g., graphics processing unit (GPU)), an application processor (AP), a general processor (e.g., APU, accelerated processing unit; GPGPU, general-purpose computing on GPU), or any other suitable processor. Memory 116 may be, for example, a discrete frame buffer or a unified memory. Processor 114 is configured to generate display data 106 in display frames and may temporally store display data 106 in memory 116 before sending it to control logic 104. Processor 114 may also generate other data, such as but not limited to, control instructions 118 or test signals, and provide them to control logic 104 directly or through memory 116. Control logic 104 then receives display data 106 from memory 116 or from processor 114 directly.
Each subpixel may be any of the units that make up a pixel, i.e., a subdivision of a pixel. For example, a subpixel may be a single-color display element that can be individually addressed. In some embodiments in which display 102 is a light emitting element display (e.g., an OLED display or a micro-LED display), each subpixel may include a light emitting element (e.g., an OLED or a micro-LED) and a pixel circuit for driving the light emitting element. The plurality of subpixels (and the light emitting elements thereof) may be arranged in an array having a plurality of rows and columns according to any suitable subpixel arrangement. Each light emitting element can emit light in a predetermined brightness and color, such as but not limited to, red, green, blue, yellow, cyan, magenta, or white. Each pixel circuit includes thin film transistors (TFTs) and capacitor(s) and is configured to drive the corresponding subpixel by controlling the light emitting from the respective light emitting element according to control signals 108 from control logic 104. The pixel circuit may be in a 2T1C configuration (i.e., including a switching transistor, a driving transistor, and a storage capacitor) or may include a compensation circuit with more transistors and/or capacitors for brightness uniformity, such as in a 7T1C, 5T1C, 5T2C, or 6T1C configuration.
Gate driving circuit 202 in this embodiment is operatively coupled to active region 200 via a plurality of gate lines GI-Gm (a.k.a. scan lines) and configured to scan the plurality of subpixels. For example, gate driving circuit 202 applies a plurality of scan signals, which are generated based on control signals 108 from control logic 104, to the plurality of gate lines G 1-Gm for scanning the plurality of subpixels in a gate scanning order. A scan signal is applied to the gate electrode of a switching transistor of each pixel circuit during the scan period to turn on the switching transistor so that the data signal for the corresponding subpixel can be written by source driving circuit 204. It is to be appreciated that although one gate driving circuit 202 is illustrated in
Source driving circuit 204 in this embodiment is operatively coupled to active region 200 via a plurality of source lines S1-Sn (a.k.a. data lines) and configured to write display data 106 in frames to the plurality of subpixels. For example, source driving circuit 204 may simultaneously apply a plurality of data signals to the plurality of source lines S1-Sn for the subpixels. That is, source driving circuit 204 may include one or more shift registers, digital-analog converters (DAC), multiplexers (MUX), and arithmetic circuit for controlling a timing of application of voltage to the source electrode of the switching transistor of each pixel circuit (i.e., during the scan period in each frame) and a magnitude of the applied voltage according to gradations of display data 106. It is to be appreciated that although one source driving circuit 204 is illustrated in
Additionally, a light emission driving circuit 206 may be included on the display panel. Light emission driving circuit 206 may be operatively coupled to active region 200 and configured to cause each subpixel to emit light for a certain time period in each frame by applying a plurality of light emission signals to a plurality of emission lines E1-Ek. It is to be appreciated that although one light emission driving circuit 206 is illustrated in
For each light emitting element 302, pixel circuit 300 or 400 needs to include an individual set of light emission control switch 306 and discharge control switch 308, each of which may include multiple devices (e.g., transistors). Thus, the total area of pixel circuits for the array of subpixels may be significantly increased, thereby reducing the display resolution.
As shown in
The first bias signal controls the voltage at the source terminal (at node N_1). The voltage at the source terminal VN_1 is the summation of the voltage of the first bias signal VBIAS1 and the gate-source voltage VGS of bridge transistor 802 (VN_1=VBIAS1+VCS). When light emitting element 804 is turned-off (without current passing through), the voltage drop across light emitting element 804 is at the minimum value. The minimum voltage drop across bridge transistor 802 is 0 when bridge transistor 802 is turned-off. At this time, turning off bridge transistor 802 (VCS=0) can cause the voltage at the source terminal VN_1 to become the same as the first bias signal VBIAS1 (VN_1=VBIAS1). Bridge transistor 802 and the driving transistor of pixel driver 806 share the remaining voltage drop between the power source VPNL and the ground GND1, thereby reducing the voltage drop across the driving transistor of pixel driver 806. In some embodiments, the first bias signal may control the voltage at the source terminal to be a midpoint voltage when light emitting element 804 is turned-off. That is, the drain-source voltage of the driving transistor of pixel driver 806 may be the same as the drain-source voltage of bridge transistor 802 as controlled by the first bias signal.
On the other hand, when light emitting element 804 is fully turned-on (i.e., at the highest brightness), the voltage drop across light emitting element 804 is at the maximum value. In this situation, bridge transistor 802 is turned-on and thus, light emitting element 804 does not suffer from performance degrade due to the extra voltage drop across bridge transistor 802. Accordingly, the first bias signal can control the voltage drop distribution between the driving transistor of pixel driver 806 and bridge transistor 802. The first bias signal can also control the off-state current (leakage current) when light emitting element 804 is turned-off.
The first bias signal controls the voltage at the source terminal (at node N_4). The voltage at the source terminal VN_4 is the summation of the voltage of the first bias signal VBIAS1 and the gate-source voltage VGS of bridge transistor 902 (VN_1=VBIAS1+VGS). When light emitting element 904 is turned-off (without current passing through), the voltage drop across light emitting element 904 is at the minimum value. The minimum voltage drop across bridge transistor 902 is 0 when bridge transistor 902 is turned-off. At this time, turning off bridge transistor 902 (VGS=0) can cause the voltage at the source terminal VN_4 to become the same as the first bias signal VBIAS1 (VN_1=VBIAS1). Bridge transistor 902 and the driving transistor of pixel driver 906 share the remaining voltage drop between the power source VPNL and the ground GND1, thereby reducing the voltage drop across the driving transistor of pixel driver 906. In some embodiments, the first bias signal may control the voltage at the source terminal to be a midpoint voltage when light emitting element 904 is turned-off. That is, the drain-source voltage of the driving transistor of pixel driver 906 may be the same as the drain-source voltage of bridge transistor 902 as controlled by the first bias signal.
On the other hand, when light emitting element 904 is fully turned-on (i.e., at the highest brightness), the voltage drop across light emitting element 904 is at the maximum value. In this situation, bridge transistor 902 is turned-on and thus, light emitting element 904 does not suffer from performance degrade due to the extra voltage drop across bridge transistor 902. Accordingly, the first bias signal can control the voltage drop distribution between the driving transistor of pixel driver 906 and bridge transistor 902. The first bias signal can also control the off-state current (leakage current) when light emitting element 904 is turned-off.
Pixel circuit 1101 also includes a pixel driver having a driving transistor 1106, a switch 1108 (e.g., a switching transistor), and a capacitor 1110 (e.g., a storage transistor). Driving transistor 1106 includes a source terminal, a drain terminal, a gate terminal, and a body terminal. In this embodiment, driving transistor 1106 is an n-type transistor, and its source terminal is coupled to the source terminal of bridge transistor 1102. The body terminal of driving transistor 1106 receives a second bias signal VBIAS2 that is different from the voltage of ground GND1. In some embodiments, the voltage of the second bias signal received by the body terminal of driving transistor 1106 may be the same as the voltage of the first bias signal VBIAS1 received by the body terminal of bridge transistor 1102. It is understood that driving transistor 1106 can be a p-type transistor with its drain terminal coupled to the source terminal of bridge transistor 1102, according to some embodiments. Capacitor 1110 includes a terminal coupled to the gate terminal of driving transistor 1106. Switch 1108 includes a first terminal receiving a corresponding data signal DATA[0] from source driving circuit 204 via a source line and a second terminal coupled to capacitor 1110 and the gate terminal of driving transistor 1106. Switch 1108 may include one or more transistors configured to, in response to a scan signal, charge capacitor 1110 to a voltage based on the data signal, so that the gate terminal of driving transistor 1106 is biased based on the voltage charged to capacitor 1110.
For each of the pixel circuits in circuit 1100, the switches of the pixel drivers receive the same scan signal from gate driving circuit 202 via the same scan line. In some embodiments, the gate terminals of the bridge transistors may receive the same first bias signal VBIAS1, and the body terminals of the driving transistors may receive the same second bias signal VBIAS2. The body terminal of each bridge transistor is individually coupled to its own source terminal, e.g., having a separate well, or coupled to the terminal of the switch that receives the data signal, to achieve the maximum withstand voltage and void junction break-down.
As shown in
In this embodiment, discharge controller 1114 is coupled to the pixel drivers of each pixel circuit (at common node EM_PWR) and a terminal receiving the first bias signal VBIAS1. That is, discharge controller 1114 can achieve global discharge of all the light emitting elements in the same row as shown in
Circuits 1100 and 1200 described above in
Also, integrated circuit design systems (e.g. work stations) are known that create wafers with integrated circuits based on executable instructions stored on a computer-readable medium such as but not limited to CDROM, RAM, other forms of ROM, hard drives, distributed memory, etc. The instructions may be represented by any suitable language such as but not limited to hardware descriptor language (HDL), Verilog or other suitable language. As such, the logic, units, and circuits described herein may also be produced as integrated circuits by such systems using the computer-readable medium with instructions stored therein.
For example, an integrated circuit with the aforedescribed logic, units, and circuits may be created using such integrated circuit fabrication systems. The computer-readable medium stores instructions executable by one or more integrated circuit design systems that causes the one or more integrated circuit design systems to design an integrated circuit. In one example, the designed integrated circuit includes a pixel driver and a bridge transistor. The pixel driver is configured to receive a data signal and drive a light emitting element based on the data signal. The bridge transistor includes a gate terminal receiving a first bias signal, a source terminal coupled to the pixel driver, a drain terminal coupled to a terminal of the light emitting element, and a body terminal coupled to the source terminal or receiving the data signal. The first bias signal controls a voltage at the source terminal.
In another example, the designed integrated circuit includes a plurality of pixel circuits and a discharge controller. Each of the plurality of pixel circuits is configured to drive one of a plurality of light emitting elements arranged in a same row and includes a pixel driver and a bridge transistor. The pixel driver is configured to receive a data signal and drive the corresponding light emitting element based on the data signal. The bridge transistor includes a gate terminal receiving a same first bias signal, a source terminal coupled to the pixel driver, a drain terminal coupled to a terminal of the light emitting element, and a body terminal coupled to the source terminal or receiving the data signal. The first bias signal controls a voltage at the source terminal. The discharge controller is coupled to the pixel drivers of each of the plurality of pixel circuits and is configured to, in response to a global discharge signal, simultaneously control discharge of the plurality of light emitting elements in the same row.
In still another example, the designed integrated circuit includes a plurality of pixel circuits, a discharge controller, and a light emission controller. Each of the plurality of pixel circuits is configured to drive one of a plurality of light emitting elements arranged in a same row and includes a pixel driver. The pixel driver is configured to receive a data signal and drive the corresponding light emitting element based on the data signal. The discharge controller is coupled to the pixel drivers of each of the plurality of pixel circuits and configured to, in response to a global discharge signal, simultaneously control discharge of the plurality of light emitting elements in the same row. The light emission controller is coupled to a power source and the pixel drivers of each of the plurality of pixel circuits and configured to, in response to a global light emission signal, simultaneously control light emission of the plurality of light emitting elements in the same row.
It is to be appreciated that the Detailed Description section, and not the Summary and Abstract sections, is intended to be used to interpret the claims. The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure or the appended claims in any way.
While the present disclosure has been described herein with reference to exemplary embodiments for exemplary fields and applications, it should be understood that the present disclosure is not limited thereto. Other embodiments and modifications thereto are possible, and are within the scope and spirit of the present disclosure. For example, and without limiting the generality of this paragraph, embodiments are not limited to the software, hardware, firmware, and/or entities illustrated in the figures and/or described herein. Further, embodiments (whether or not explicitly described herein) have significant utility to fields and applications beyond the examples described herein.
Embodiments have been described herein with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined as long as the specified functions and relationships (or equivalents thereof) are appropriately performed. Also, alternative embodiments may perform functional blocks, steps, operations, methods, etc. using orderings different than those described herein.
The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
