Pixel circuits for mitigation of hysteresis

Abstract
What is disclosed are display systems and methods of compensation of images produced by active matrix light emitting diode device (AMOLED) and other emissive displays. Anomalies in luminance produced by pixel circuits due to hysteresis effects are corrected through in-pixel compensation and resetting of the driving transistor.
Description
FIELD OF THE INVENTION

The present disclosure relates to pixels circuits and signal timing of light emissive visual display technology, and particularly to systems and methods for programming and resetting pixels in active matrix light emitting diode device (AMOLED) and other emissive displays to mitigate hysteresis.


BRIEF SUMMARY

According to a first aspect there is provided a display system comprising: an array of pixel circuits arranged in rows and columns, each pixel circuit including: a driving transistor; a storage capacitor coupled across a gate terminal and a first terminal of the driving transistor; a light emitting device coupled to a second terminal of the driving transistor; and a reset switch transistor coupled between a first reference potential and a node common to a first terminal of the storage capacitor and the gate terminal of the driving transistor; and a controller for driving each pixel circuit during each frame over a plurality of operation cycles for the pixel circuit including a programming cycle for programming the storage capacitor of the pixel circuit, and a reset cycle prior to the programming cycle for resetting the driving transistor of the pixel circuit, the controller resetting the driving transistor of the pixel circuit by activating the reset switch transistor of the pixel circuit during the reset cycle to expose the node of the pixel circuit to the reference potential which causes reverse biasing across the gate and first terminal of the driving transistor.


In some embodiments, the controller activates the reset switch transistor of the pixel circuit during the reset cycle of the pixel circuit with a control signal used for controlling a programming of another pixel circuit during the programming cycle of the another pixel circuit.


In some embodiments, the pixel circuit is of one row other than another row of the another pixel circuit. In some embodiments, the one row and the another row are adjacent rows.


In some embodiments, the controller programs the pixel circuit during the programming cycle of the pixel circuit using a write signal for the one row for controlling a first switch transistor for coupling a data line with the storage capacitor of the pixel circuit and using a read signal for the one row for controlling a second switch transistor for coupling a monitor line with the storage capacitor of the pixel circuit, and the control signal used for controlling the programming of the another pixel circuit is one of a write signal and a read signal for the another row.


In some embodiments, the controller further is for driving each pixel circuit over a plurality of operation cycles including a compensation cycle and a settling cycle after the programming cycle, during the compensation cycle the controller using the read signal to deactivate the second switch transistor to decouple the monitor line from the storage capacitor of the pixel circuit allowing the storage capacitor to discharge through the driving transistor of the pixel circuit during the compensation cycle.


Some embodiments further provide for a third switch transistor shared by at least a first and a second pixel circuit of the one row, in which the second switch transistor is shared by the at least a first and a second pixel circuit, in which the controller programs the at least a first and a second pixel circuit during the programming cycle using the read signal for the one row for controlling the shared second switch transistor for coupling the monitor line with the storage capacitors of the at least a first and a second pixel circuit, and in which the controller further is for driving each pixel circuit over a plurality of operation cycles including an emission cycle after the programming cycle, during the emission cycle the controller using an emission signal line to control the third switch transistor to couple the driving transistors of the at least a first and a second pixel circuit to the first reference potential.


In some embodiments, the controller programs the pixel circuit during the programming cycle of the first circuit using a write signal for the one row for controlling a first switch transistor for coupling a data line with the storage capacitor of the pixel circuit and for controlling a second switch transistor for coupling a monitor line with the storage capacitor of the pixel circuit, in which the control signal used for controlling the programming of the another pixel is a write signal for the another row.


Some embodiments further provide for a third switch transistor shared by at least a first and a second pixel circuit of the one row, in which the second switch transistor is shared by the at least a first and a second pixel circuit, in which the controller further is for driving each pixel circuit over a plurality of operation cycles including an emission cycle after the programming cycle, during the emission cycle the controller using an emission signal line to control the third switch transistor to couple the driving transistors of the at least a first and a second pixel circuit to the first reference potential.


According to another aspect, there is provided a method of driving a display system, the display system including an array of pixel circuits arranged in rows and columns, each pixel circuit including: a driving transistor; a storage capacitor coupled across a gate terminal and a first terminal of the driving transistor; a light emitting device coupled to a second terminal of the driving transistor; and a reset switch transistor coupled between a first reference potential and a node common to a first terminal of the storage capacitor and the gate terminal of the driving transistor; the method comprising: driving each pixel circuit during each frame over a plurality of operation cycles for the pixel circuit including a programming cycle and a reset cycle, comprising: during the programming cycle, programming the storage capacitor of the pixel circuit, and during a reset cycle prior to the programming cycle, resetting the driving transistor of the pixel circuit by activating the reset switch transistor of the pixel circuit during the reset cycle to expose the node of the pixel circuit to the reference potential which causes reverse biasing across the gate and first terminal of the driving transistor.


In some embodiments resetting the driving transistor comprises activating the reset switch transistor of the pixel circuit with a control signal used for controlling a programming of another pixel circuit during the programming cycle of the another pixel circuit.


Some embodiments further provide for programming the pixel circuit during the programming cycle using a write signal for the one row for controlling a first switch transistor for coupling a data line with the storage capacitor of the pixel circuit and using a read signal for the one row for controlling a second switch transistor for coupling a monitor line with the storage capacitor of the pixel circuit, in which the control signal used for controlling the programming of the another pixel circuit is one of a write signal and a read signal for the another row.


In some embodiments, the plurality of operation cycles includes a compensation cycle and a settling cycle, in which driving each pixel circuit further comprises after the programming cycle, during compensation cycle, deactivating the second switch transistor using the read signal to decouple the monitor line from the storage capacitor of the pixel circuit allowing the storage capacitor to discharge through the driving transistor of the pixel circuit during the compensation cycle.


Some embodiments further provide for, programming the pixel circuit during the programming cycle using a write signal for the one row for controlling a first switch transistor for coupling a data line with the storage capacitor of the pixel circuit and for controlling a second switch transistor for coupling a monitor line with the storage capacitor of the pixel circuit, in which the control signal used for controlling the programming of the another pixel is a write signal for the another row.


According to a further aspect there is provided a display system comprising: an array of pixel circuits arranged in rows and columns, each pixel circuit including: a driving transistor; a storage capacitor coupled across a gate terminal and a first terminal of the driving transistor; a light emitting device coupled to a second terminal of the driving transistor; and a switch transistor coupled between a reference voltage and a node common to a first terminal of the storage capacitor and the first terminal of the driving transistor; and a controller for driving each pixel circuit during each frame over a plurality of operation cycles for the pixel circuit including a programming cycle for programming the storage capacitor of the pixel circuit, and a reset cycle prior to the programming cycle for resetting the driving transistor of the pixel circuit, the controller resetting the driving transistor of the pixel circuit by activating the switch transistor of the pixel circuit during the reset cycle to expose the node of the pixel circuit to the reference voltage which is set to a voltage to cause reverse biasing across the gate and first terminal of the driving transistor.


In some embodiments, the controller programs the pixel circuit during the programming cycle of the pixel circuit by deactivating the switch transistor, activating a first switch transistor for coupling a data line with the storage capacitor and the gate terminal of the driving transistor of the pixel circuit and activating a second switch transistor for coupling a controllable reference potential with the node of the pixel circuit.


In some embodiments, the controller further is for driving each pixel circuit over a plurality of operation cycles including a compensation cycle and a settling cycle after the programming cycle, during the compensation cycle the controller deactivating the second switch transistor to decouple the controllable reference potential from the node of the pixel circuit allowing the storage capacitor to discharge through the driving transistor of the pixel circuit during the compensation cycle.


According to yet another aspect there is provided a method of driving a display system, the display system including an array of pixel circuits arranged in rows and columns, each pixel circuit including: a driving transistor; a storage capacitor coupled across a gate terminal and a first terminal of the driving transistor; a light emitting device coupled to a second terminal of the driving transistor; and a switch transistor coupled between a reference voltage and a node common to a first terminal of the storage capacitor and the first terminal of the driving transistor; the method comprising: driving each pixel circuit during each frame over a plurality of operation cycles for the pixel circuit including a programming cycle and a reset cycle, comprising: during the programming cycle, programming the storage capacitor of the pixel circuit, and during a reset cycle prior to the programming cycle, resetting the driving transistor of the pixel circuit by activating the switch transistor of the pixel circuit during the reset cycle to expose the node of the pixel circuit to the reference voltage which is set to a voltage to cause reverse biasing across the gate and first terminal of the driving transistor.


Some embodiments further provide for programming the pixel circuit during the programming cycle by deactivating the switch transistor, activating a first switch transistor for coupling a data line with the storage capacitor and the gate terminal of the driving transistor of the pixel circuit, and activating a second switch transistor for coupling a controllable reference potential with the node of the pixel circuit.


In some embodiments, the plurality of operation cycles includes a compensation cycle and a settling cycle, in which driving each pixel circuit further comprises after the programming cycle, during the compensation cycle, deactivating the second switch transistor to decouple the controllable reference potential from the node of the pixel circuit allowing the storage capacitor to discharge through the driving transistor of the pixel circuit during the compensation cycle.


The foregoing and additional aspects and embodiments of the present disclosure will be apparent to those of ordinary skill in the art in view of the detailed description of various embodiments and/or aspects, which is made with reference to the drawings, a brief description of which is provided next.





BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other advantages of the disclosure will become apparent upon reading the following detailed description and upon reference to the drawings.



FIG. 1 illustrates an example display system utilizing the methods and comprising the pixels disclosed;



FIG. 2A is a circuit diagram of a thin film transistor (TFT) forward biased;



FIG. 2B is a circuit diagram of a thin film transistor (TFT) reverse biased;



FIG. 3 circuit diagram of a four transistor single capacitor (4T1C) pixel circuit according to an embodiment with in-pixel compensation;



FIG. 4 is a timing diagram illustrating programming and driving of a 4T1C pixel circuit;



FIG. 5 is a circuit diagram of a five transistor single capacitor (5T1C) pixel circuit according to an embodiment;



FIG. 6 is a circuit diagram of a modified 5T1C pixel circuit according to a further embodiment;



FIG. 7 a timing diagram illustrating programming and driving of a 5T1C pixel circuits of FIGS. 5 and 6;



FIG. 8 is a circuit diagram illustrating a TFT sharing implementation of the 5T1C pixel circuit of FIG. 5;



FIG. 9 is a circuit diagram illustrating a TFT sharing implementation of the 5T1C pixel circuit of FIG. 6; and



FIG. 10 is a timing diagram illustrating an alternate programming and driving of the 4T1C pixel circuit of FIG. 3.





While the present disclosure is susceptible to various modifications and alternative forms, specific embodiments or implementations have been shown by way of example in the drawings and will be described in detail herein. It should be understood, however, that the disclosure is not intended to be limited to the particular forms disclosed. Rather, the disclosure is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of an invention as defined by the appended claims.


DETAILED DESCRIPTION

Many modern display technologies suffer from defects, variations, and non-uniformities, from the moment of fabrication, and can suffer further from aging and deterioration over the operational lifetime of the display, which result in the production of images which deviate from those which are intended. Methods of image calibration and compensation are used to correct for those defects in order to produce images which are more accurate, uniform, or otherwise more closely reproduce the image represented by the image data. Some displays suffer from hysteresis effects due to the trapping of carriers in the TFT channel of the driving transistor after being forward biased in saturation mode for a sufficient time. This affects the I-V characteristics of the TFT including its threshold voltage, which are exhibited as hysteresis effects which can affect the accuracy and uniformity of the display.


The display systems, pixels, and methods disclosed below address these issues through control timing and a reset cycle for the pixel circuits as described below.


While the embodiments described herein will be in the context of AMOLED displays it should be understood that the systems and methods described herein are applicable to any other display comprising pixels which might utilize current biasing, including but not limited to light emitting diode displays (LED), electroluminescent displays (ELD), organic light emitting diode displays (OLED), plasma display panels (PSP), among other displays.


It should be understood that the embodiments described herein pertain to systems and methods of calibration and compensation and do not limit the display technology underlying their operation and the operation of the displays in which they are implemented. The systems and methods described herein are applicable to any number of various types and implementations of various visual display technologies.



FIG. 1 is a diagram of an example display system 150 implementing the methods and pixel circuits described further below. The display system 150 includes a display panel 120, an address driver 108, a data driver 104, a controller 102, and a memory storage 106.


The display panel 120 includes an array of pixels 110 (only one explicitly shown) arranged in rows and columns. Each of the pixels 110 is individually programmable to emit light with individually programmable luminance values. The controller 102 receives digital data indicative of information to be displayed on the display panel 120. The controller 102 sends signals 132 to the data driver 104 and scheduling signals 134 to the address driver 108 to drive the pixels 110 in the display panel 120 to display the information indicated. The plurality of pixels 110 of the display panel 120 thus comprise a display array or display screen adapted to dynamically display information according to the input digital data received by the controller 102. The display screen can display images and streams of video information from data received by the controller 102. The supply voltage 114 provides a constant power voltage or can serve as an adjustable voltage supply that is controlled by signals from the controller 102. The display system 150 can also incorporate features from a current source or sink (not shown) to provide biasing currents to the pixels 110 in the display panel 120 to thereby decrease programming time for the pixels 110.


For illustrative purposes, only one pixel 110 is explicitly shown in the display system 150 in FIG. 1. It is understood that the display system 150 is implemented with a display screen that includes an array of a plurality of pixels, such as the pixel 110, and that the display screen is not limited to a particular number of rows and columns of pixels. For example, the display system 150 can be implemented with a display screen with a number of rows and columns of pixels commonly available in displays for mobile devices, monitor-based devices, and/or projection-devices. In a multichannel or color display, a number of different types of pixels, each responsible for reproducing color of a particular channel or color such as red, green, or blue, will be present in the display. Pixels of this kind may also be referred to as “subpixels” as a group of them collectively provide a desired color at a particular row and column of the display, which group of subpixels may collectively also be referred to as a “pixel”.


The pixel 110 is operated by a driving circuit of the pixel circuit that generally includes a driving transistor and a light emitting device. Hereinafter the pixel 110 may be referred to also as a “pixel circuit”. The light emitting device can optionally be an organic light emitting diode, but implementations of the present disclosure apply to pixel circuits having other electroluminescence devices, including current-driven light emitting devices and those listed above. The driving transistor in the pixel 110 can optionally be an n-type or p-type amorphous silicon thin-film transistor, but implementations of the present disclosure are not limited to pixel circuits having a particular polarity of transistor or only to pixel circuits having thin-film transistors. The pixel circuit 110 can also include a storage capacitor for storing programming information and allowing the pixel circuit 110 to drive the light emitting device after being addressed. Thus, the display panel 120 can be an active matrix display array.


As illustrated in FIG. 1, the pixel 110 illustrated as the top-left pixel in the display panel 120 is coupled to a select line 124 (also referred to as a write signal line), a supply line 126, a data line 122, and a monitor line 128. A read line and an emission control line may also be included for respectively controlling connections to the monitor line and providing additional control of emission from the pixel. In one implementation, the supply voltage 114 can also provide a second supply line to the pixel 110. For example, each pixel can be coupled to a first supply line 126 charged with ELVDD and a second supply line 127 coupled with ELVSS, and the pixel circuits 110 can be situated between the first and second supply lines to facilitate driving current between the two supply lines during an emission phase of the pixel circuit. It is to be understood that each of the pixels 110 in the pixel array of the display 120 is coupled to appropriate select lines, supply lines, data lines, and monitor lines. It is noted that aspects of the present disclosure apply to pixels having additional connections, such as connections to additional select lines, and to pixels having fewer connections.


With reference to the pixel 110 of the display panel 120, the select line 124 is provided by the address driver 108, and can be utilized to enable, for example, a programming operation of the pixel 110 by activating a switch or transistor to allow the data line 122 to program the pixel 110. The data line 122 conveys programming information from the data driver 104 to the pixel 110. For example, the data line 122 can be utilized to apply a programming voltage VDATA or a programming current to the pixel 110 in order to program the pixel 110 to emit a desired amount of luminance. The programming voltage (or programming current) supplied by the data driver 104 via the data line 122 is a voltage (or current) appropriate to cause the pixel 110 to emit light with a desired amount of luminance according to the digital data received by the controller 102. The programming voltage (or programming current) can be applied to the pixel 110 during a programming operation of the pixel 110 so as to charge a storage device within the pixel 110, such as a storage capacitor, thereby enabling the pixel 110 to emit light with the desired amount of luminance during an emission operation following the programming operation. For example, the storage device in the pixel 110 can be charged during a programming operation to apply a voltage to one or more of a gate or a source terminal of the driving transistor during the emission operation, thereby causing the driving transistor to convey the driving current through the light emitting device according to the voltage stored on the storage device.


Generally, in the pixel 110, the driving current that is conveyed through the light emitting device by the driving transistor during the emission operation of the pixel 110 is a current that is supplied by the first supply line 126 and is drained to a second supply line 127. The first supply line 126 and the second supply line 127 are coupled to the voltage supply 114. The first supply line 126 can provide a positive supply voltage (e.g., the voltage commonly referred to in circuit design as “ELVDD”) and the second supply line 127 can provide a negative supply voltage (e.g., the voltage commonly referred to in circuit design as “ELVSS”). In some embodiments the positive supply voltage “ELVDD” is a controllable positive supply which may be set to provide different voltage levels including for example, reference voltages, and the standard ELVDD rail. Implementations of the present disclosure can be realized where one or the other of the supply lines (e.g., the supply line 127) is fixed at a ground voltage or at another reference voltage.


The display system 150 also includes a monitoring system 112. With reference again to the pixel 110 of the display panel 120, the monitor line 128 connects the pixel 110 to the monitoring system 112. The monitoring system 12 can be integrated with the data driver 104, or can be a separate stand-alone system. In particular, the monitoring system 112 can optionally be implemented by monitoring the current and/or voltage of the data line 122 during a monitoring operation of the pixel 110, and the monitor line 128 can be entirely omitted. The monitor line 128 allows the monitoring system 112 to measure a current or voltage associated with the pixel 110 and thereby extract information indicative of a degradation or aging of the pixel 110 or indicative of a temperature of the pixel 110. In some embodiments, display panel 120 includes temperature sensing circuitry devoted to sensing temperature implemented in the pixels 110, while in other embodiments, the pixels 110 comprise circuitry which participates in both sensing temperature and driving the pixels. For example, the monitoring system 112 can extract, via the monitor line 128, a current flowing through the driving transistor within the pixel 110 and thereby determine, based on the measured current and based on the voltages applied to the driving transistor during the measurement, a threshold voltage of the driving transistor or a shift thereof. In some implementations the monitor line 128 is used during a programming cycle to provide a second voltage VMON used in addition to the programming voltage VDATA to program the pixel.


The controller and 102 and memory store 106 together or in combination with a compensation block (not shown) use compensation data or correction data, in order to address and correct for the various defects, variations, and non-uniformities, existing at the time of fabrication, and optionally, defects suffered further from aging and deterioration after usage. In some embodiments, the correction data includes data for correcting the luminance of the pixels obtained through measurement and processing using an external optical feedback system. Some embodiments employ the monitoring system 112 to characterize the behavior of the pixels and to continue to monitor aging and deterioration as the display ages and to update the correction data to compensate for said aging and deterioration over time.



FIGS. 2A and 2B illustrate a transistor 200, in this case, a p-type thin film transistor (TFT), having a gate terminal G, a source terminal S, and a drain terminal D, which exhibits a hysteresis effect in response to biasing in the saturation region.


In FIG. 2A, the transistor 200 is depicted while being forward biased 200A in the saturation region, such that the gate voltage (VG) is less than the voltage at the source (VS) so that the source-gate voltage VSG is greater than zero (VSG>0) and such that the source-drain voltage VSD is greater than the difference between the source-gate voltage VSG and the threshold voltage (VTH) of the transistor 200 (VSD>VSG−VTH). As shown, when the transistor 200 is driven as illustrated in FIG. 2A, a driving current ID flows through the transistor 200.


When the transistor 200 is biased in this manner for a sufficient duration, which varies depending upon the transistor and various conditions of operation (in some cases, for example, a duration of 1 minute or greater is sufficient), short-term trapping of carriers in the TFT channel is caused which gives rise to temporary shifts in the threshold voltage of the transistor 200. Thereafter, while carriers remain so trapped, the transistor 200 will suffer from and exhibit hysteresis effects in its I-V response as different source-gate voltages VSG are applied.


As depicted in FIG. 2B, to mitigate the effect of hysteresis on the I-V response of the transistor 200, the transistor 200 can be periodically driven 200B during a reset cycle with a negative driver voltage, such that the gate voltage (VG) is greater than the voltage at the source (VS) and thus the source-gate voltage is less than zero (VSG<0). This triggers the release of carriers and hence a reversal of the short-term trapping of carriers, resetting the transistor 200 and its threshold voltage (VTH), and mitigating hysteresis in the I-V response exhibited by the transistor 200. As shown in FIG. 2B, when transistor 200 is driven with a negative driver voltage 200B, no current flows the source S to the drain D. Some embodiments which follow utilize a reset cycle prior to each programming cycle to improve performance of the transistor 200.


With reference to FIG. 3, the structure of a four transistor single capacitor (4T1C) pixel circuit 300 according to an embodiment utilizing in-pixel compensation will now be described. The 4T1C pixel circuit 300 corresponds, for example, to a single pixel 110 in the ith row of the display system 150 depicted in FIG. 1. The 4T1C pixel circuit 300 depicted in FIG. 3 is based on NMOS transistors. It should be understood that variations of this pixel and its functioning are contemplated and include different types of transistors (PMOS, NMOS, or CMOS) and different semiconductor materials (e.g. LTPS, Metal Oxide, etc.).


The 4T1C pixel circuit 300 includes a driving transistor 310 (T1), a light emitting device 320, a first switch transistor 330 (T2), a second switch transistor 340 (T3), a third switch transistor 350 (T4), and a storage capacitor 360 (Cs). Each of the driving transistor 310, the first switch transistor 330, the second switch transistor 340, and the third switch transistor 350 having first, second, and gate terminals, and each of the light emitting device 320 and the storage capacitor 360 having first and second terminals.


The gate terminal of the driving transistor 310 is coupled to a first terminal of the storage capacitor 360, while the first terminal of the driving transistor 310 is coupled to the second terminal of the storage capacitor 360, and the second terminal of the driving transistor 310 is coupled to the first terminal of the light emitting device 320. The gate terminal of the first switch transistor 330 is coupled to a write signal line (WRi) of the ith row, while the first terminal of the first switch transistor 330 is coupled to a data line (VDATA), and the second terminal of the first switch transistor 330 is coupled to the gate terminal of the driving transistor 310. A node common to the gate terminal of the driving transistor 310 and the storage capacitor 360 as well as the first switch transistor 330 is labelled by its voltage VG in the figure. The gate terminal of the second switch transistor 340 is coupled to a read line (RDi) of the ith row, while the first terminal of the second switch transistor 340 is coupled to a monitor line (VMON), and the second terminal of the second switch transistor 340 is coupled to the second terminal of the storage capacitor 360. The gate terminal of the third switch transistor 350 is coupled to an emission signal line (EMi) of the ith row, while the first terminal of the third switch transistor 350 is coupled to a first reference potential ELVDD, and the second terminal of the third switch transistor 350 is coupled to the second terminal of the storage capacitor 360. A node common to the second terminal of the storage capacitor 360, the driving transistor 310, the second switch transistor 340, and the third switch transistor 350 is labelled by its voltage VS in the figure. The second terminal of the light emitting device 320 is coupled to a second reference potential ELVSS. A capacitance of the light emitting device 320 is depicted in FIG. 3 as CLD. In some embodiments, the light emitting device 320 is an OLED.


The 4T1C pixel circuit 300 of FIG. 3, as will become apparent from the description of its functioning below, is capable of achieving a good level of in-pixel compensation which is useful for mitigating the hysteresis effects in the driving transistor 310.


With reference also to FIG. 4, an example of a display timing 400 for the 4T1C pixel circuit 300 depicted in FIG. 3 will now be described. The complete display timing 400 occurs typically once per frame and includes a programming cycle 410, a calibration cycle 420, a settling cycle 430, and an emission cycle 440. During the programming cycle 410 over a period TRD, the read signal (RDi) and write signal (WRi) are held low while the emission (EMi) signal is held high. The emission signal (EMi) is held high throughout the programming, calibration, and settling cycles 410420430 to ensure the third switch transistor 350 remains OFF during those cycles (TEM).


During the programming cycle 410 the first switch transistor 330 and the second switch transistor 340 are both ON. The voltage of the storage capacitor 360 and therefore the voltage VSG of the driving transistor 310 is charged to a value of VMON−VDATA where VMON is a voltage of the monitor line and VDATA is a voltage of the data line. These voltages are set in accordance with a desired programming voltage for causing the pixel 300 to emit light at a desired luminance according to image data.


At the beginning of the calibration cycle 420, the read signal (RDi) goes high to turn OFF the second switch transistor 340 to discharge some of the voltage (charge) of the storage capacitor 360 through the driving transistor 310. The amount discharged is a function of the characteristics of the driving transistor 310. For example, if the driving transistor 310 is “strong”, the discharge occurs relatively quickly and relatively more charge is discharged from the storage capacitor 360 through the driving transistor 310 during the fixed duration of the calibration cycle 420. On the other hand, if the driving transistor 310 is “weak”, the discharge occurs relatively slowly and relatively less charge is discharged from the storage capacitor 360 through the driving transistor 310 during the calibration cycle 420. As a result, the voltage (charge) stored in the storage capacitor 360 (VP) is reduced comparatively more for relatively strong driving transistors versus comparatively less for relatively weak driving transistors, thereby providing some compensation for non-uniformity and variations in the driving transistors across the display whether due to variations in fabrication, variations in degradation over time, or variations due to hysteresis in the temporary threshold voltage of the driving transistor 310.


After the calibration cycle 420, a settling cycle 430 is performed prior to the emission. During the settling cycle 430 the second and third switch transistors 340, 350 remain OFF, while the write signal (WRi) goes high to also turn OFF the first switch transistor 330. After completion of the duration of the settling cycle 430 at the start of the emission cycle 440, the emission signal (EMi) goes low turning ON the third switch transistor 350 allowing current to flow through the light emitting device 320 according to the calibrated stored voltage on the storage capacitor 360.


Although the pixel 300 circuit is capable of achieving in-pixel compensation including that related to hysteresis to a good level for high and medium grayscales, low grayscale compensation may be insufficient to meet high-end uniformity specifications.


With reference to FIG. 5, the structure of a five transistor, single capacitor (5T1C) pixel circuit 500 according to an embodiment will now be described. The 5T1C pixel circuit 500 corresponds, for example, to a single pixel 110 in the ith row of the display system 150 depicted in FIG. 1. The 5T1C pixel circuit 500 depicted in FIG. 5 is based on NMOS transistors. It should be understood that variations of this pixel and its functioning are contemplated and include different types of transistors (PMOS, NMOS, or CMOS) and different semiconductor materials (e.g. LTPS, Metal Oxide, etc.).


The 5T1C pixel circuit 500 includes a driving transistor 510 (T1), a light emitting device 520, a first switch transistor 530 (T2), a second switch transistor 540 (T3), a third switch transistor 550 (T4), and a storage capacitor 560 (Cs) in substantially the same configuration as that of the 4T1C pixel circuit 300 of FIG. 3. The 5T1C pixel circuit 500 also includes a reset switch transistor 570 (T5) coupled between ELVDD and a node between the first switch transistor 530 and the storage capacitor 560.


The gate terminal of the driving transistor 510 is coupled to a first terminal of the storage capacitor 560, while the first terminal of the driving transistor 510 is coupled to the second terminal of the storage capacitor 560, and the second terminal of the driving transistor 510 is coupled to the first terminal of the light emitting device 520. The gate terminal of the first switch transistor 530 is coupled to a write signal line (WRi) of the ith row, while the first terminal of the first switch transistor 530 is coupled to a data line (VDATA), and the second terminal of the first switch transistor 530 is coupled to the gate terminal of the driving transistor 510. A node common to the gate terminal of the driving transistor 510 and the storage capacitor 560 as well as the first switch transistor 530 is labelled by its voltage VG in the figure. The gate terminal of the second switch transistor 540 is coupled to a read line (RDi) of the ith row, while the first terminal of the second switch transistor 540 is coupled to a monitor line (VMON), and the second terminal of the second switch transistor 540 is coupled to the second terminal of the storage capacitor 560. The gate terminal of the third switch transistor 550 is coupled to an emission signal line (EMi) of the ith row, while the first terminal of the third switch transistor 550 is coupled to a first reference potential ELVDD, and the second terminal of the third switch transistor 550 is coupled to the second terminal of the storage capacitor 560. A node common to the second terminal of the storage capacitor 560, the driving transistor 510, the second switch transistor 540, and the third switch transistor 550 is labelled by its voltage VS in the figure. The second terminal of the light emitting device 520 is coupled to a second reference potential ELVSS. A capacitance of the light emitting device 520 is depicted in FIG. 5 as CLD. In some embodiments, the light emitting device 520 is an OLED.


As mentioned above, the 5T1C pixel circuit 500 includes a reset switch transistor 570 coupled between the gate terminal of the drive transistor 510 and the first reference potential ELVDD. The first terminal of the reset switch transistor 570 is coupled to the first reference potential ELVDD and the second terminal of the reset switch transistor 570 is coupled to the node VG common to the first switch transistor 530, the storage capacitor 560, and the driving transistor 510. The gate terminal of the reset switch transistor 570 is coupled to a read or write signal line of a different row, for example, the read line RDi−1 of the (i−1)th row or the write signal line WRi−1 of the (i−1)th row. The 5T1C pixel circuit 500 is capable of achieving both a good level of in-pixel compensation if so driven (which is useful for mitigating the hysteresis effects in the driving transistor 510) as well as being capable of releasing charges trapped in the channel of the driving transistor 510 through the reset cycle described further below.


With reference to FIG. 6, the structure of a modified implementation of a five transistor, single capacitor (5T1C) pixel circuit 600 according to an embodiment will now be described. The modified 5T1C pixel circuit 600 corresponds, for example, to a single pixel 110 in the ith row of the display system 150 depicted in FIG. 1. The modified 5T1C pixel circuit 600 depicted in FIG. 6 is based on NMOS transistors. It should be understood that variations of this pixel and its functioning are contemplated and include different types of transistors (PMOS, NMOS, or CMOS) and different semiconductor materials (e.g. LTPS, Metal Oxide, etc.).


The modified 5T1C pixel circuit 600 includes a driving transistor 610 (T1), a light emitting device 620, a first switch transistor 630 (T2), a second switch transistor 640 (T3), a third switch transistor 650 (T4), a storage capacitor 660 (Cs), and a reset switch transistor 670 (T5) in substantially the same configuration as that of the 5T1C pixel circuit 500 of FIG. 5. The modified 5T1C pixel circuit 600 differs from the pixel circuit 500 only in that the gate terminal of the second switch transistor 640 is coupled to the write signal line (WRi) of the ith row (to which the gate terminal of the first switch transistor 630 is also coupled), and the gate terminal of the reset switch transistor 670 is coupled to a write signal line of a different row, namely, the write signal line WRi−1 of the (i−1)th row. This simplifies row (gate) control signals required per row of pixels of the display system 150.


The modified 5T1C pixel circuit 600, in a similar manner as the 5T1C 500 pixel circuit is capable of releasing charges trapped in the channel of the driving transistor 510 through the reset cycle described below.


With reference also to FIG. 7, an example of a display timing 700 for 5T1C pixel circuits 500 and 600 of the ith row depicted in FIGS. 5-6 will now be described. The complete display timing 700 occurs typically once per frame and includes a post-emission settling cycle 702 (which occurs after a previous emission cycle 740x of a previous frame), a reset cycle 704, a first settling cycle 706, a programming cycle 710, first and second pre-emission settling cycles 730a, 730b, and an emission cycle 740.


At the end of the previous emission cycle 740x and the beginning of the post-emission settling cycle 702, the emission signal is (EMi) is switched from low to high in order to turn OFF the third switch transistor 550, 650. During non-emission cycles 702, 704, 706, 710, 730a, 730b the emission (EMi) signal is held high to ensure the third switch transistor 550 or 650 remains OFF during those cycles.


During the post-emission settling cycle 702 each of the transistors of the pixel circuit 500600 is OFF allowing the voltage VS to settle to VOLED (the turn on voltage of the light emitting device 520620), while the voltage VG to settle to the voltage of the light emitting device minus a voltage on the storage capacitor 560660 related to a pixel programming of the pixel during the previous frame (VOLED−VP1).


After a duration of the post-emission settling cycle 702, a sufficient settling time for VS to settle to a low voltage, the write or read signal controlling the reset switch transistor 570670, namely read signal RDi−1 for the (i−1)th row, or write signal WRi−1 for the (i−1)th row, switches from high to low, turning the reset switch transistor 570670 ON, which charges node VG up to ELVDD during the reset cycle 704. Since VS has been discharged to a low voltage of VOLED which is much less than ELVDD, during reset cycle 704 VSG goes less than zero, the driving transistor 510610 becomes negatively biased which triggers the release of carriers and hence reversal of the short-term trapping of carriers, resetting the driving transistor 510610 and its threshold voltage (VTH), and mitigating hysteresis in the I-V response exhibited by the driving transistor 510610 when it is programmed in the following programming cycle 710. The negative biasing utilizing the ELVDD rail is programming independent and provides a high magnitude of reverse biasing for effective release of carriers and hence reduction of hysteresis effects.


After the reset cycle 704, the read signal RDi−1 for the (i−1)th row, or write signal WRi−1 for the (i−1)th row, switches from low to high, turning the reset switch transistor 570670 OFF. For a relatively short first settling cycle 706, each of the transistors of the pixel circuit 500600 are OFF. Following the first settling cycle 706, during the programming cycle 710, both the first switch transistor 530630 and the second switch transistor 540640 are turned ON.


For embodiments which include distinct read RD and write WR control signals, such as for the 5T1C pixel circuit 500, the read signal RDi for the ith row, and the write signal WRi for the ith row both switch from high to low, turning both the first switch transistor 530 and the second switch transistor 540 ON. For embodiments with only a write signal WR such as for the 5T1C pixel circuit 600, the write signal WRi for the ith row switches from high to low, turning both the first switch transistor 630 and the second switch transistor 640 ON.


This exposes the first terminal of the storage capacitor 560660 and the node VG to VDATA on the data line, and exposes the second terminal of the storage capacitor 560660 and the node VS to the voltage VMON on the monitor line.


Over the duration that the first switch transistor 530 is ON (TWR), VG is charged to VDATA, and over the duration that the second switch transistor 540 is ON (TRD), VS is charged to VMON. In embodiments with only write signals WRi, both the first and second switch transistors 630640 are ON during TWR, during which time VG is charged to VDATA and VS is charged to VMON.


In some embodiments, the first switch transistor 530630 and the second switch transistor 540640 are turned OFF at the same time at the end of the programming cycle 710. In embodiments with separate WRi and RDi signals such as the 5TC1 pixel circuit 500, the timing of TWR and TRD may be different, and such that TRD<TWR<TRWOW(i) (where TROW(i) is the total duration of the programming cycle 710) so as to provide the programming and compensation cycles and the in-pixel compensation described in association with the embodiment depicted in FIG. 3 and FIG. 4.


Once both of the first switch transistor 530630 and the second switch transistor 540640 are turned OFF, after the end of the programming cycle 710, is a first pre-emission settling cycles 730a, followed by a second pre-emission settling cycle 730b during which each transistor of the 5T1C pixel circuit 500600 are OFF, allowing the voltage VS to settle at VOLED, and allowing the voltage at VG to settle at VOLED−VP2, where VP2 is related to the programming voltage (VMON−VDATA) and any shift caused by the threshold voltage and any in-pixel compensation. The reset cycle should reduce any hysteresis effects on that threshold voltage and any in-pixel compensation should also reduce the effects of other variations in threshold voltage (such as variations in fabrication) so that VP2 more closely matches the desired programming.


Finally, at the beginning of the emission cycle 740, the emission (EMi) signal is switched from high to low to turn ON the third switch transistor 550 or 650.


The same token used for programming a pixel in one row (i−1) over either the WRi−1 or RDi−1 signal lines (of duration TWR or TRD), is re-used to control the reset switch transistor 570, 670 of a pixel in another row (i). The timing generally for programming and settling row i−1 (TROW(i−1)), occurs just prior to but for the same duration as that of the programming and settling of row i (TROW(i)).


With reference also to FIG. 8 and FIG. 9, an implementation of 5T1C pixel circuits 500600 in which the second and third switch transistors are shared between two or more adjacent 5T1C pixels will now be described.


With reference to FIG. 8, a first subpixel 801A and second subpixel 801B each include the a first switch transistor 830A 830B, a driving transistor 810A 810B, a light emitting device 820A 820B, and a reset transistor 870A 870B as shown and described in association with the 5T1C pixel circuit 500 of FIG. 5. The first and second subpixels 801A 801B, however, share the node VS common and between the driving transistors 810A 810B and the storage capacitors 860A 860B. Also shared between the first and second subpixels 801A 801B, are a third switch transistor 850 (T4) coupled between the node VS and ELVDD, and a second switch transistor 840 (T3) coupled between the node VS and the monitor line VMON. The gate terminal of the third switch transistor 850 is coupled to an emission signal line (EMi) of the ith row, while the first terminal of the third switch transistor 850 is coupled to the first reference potential ELVDD, and the second terminal of the third switch transistor 850 is coupled to node VS which is common to the second terminal of the storage capacitors 860A 860B. The gate terminal of the second switch transistor 840 is coupled to a read line (RDi) of the ith row, while the first terminal of the second switch transistor 840 is coupled to a monitor line (VMON), and the second terminal of the second switch transistor 840 is also coupled to the node VS.


Each of the first and second subpixels 801A 801B functions the same as the 5T1C pixel circuit 500 of FIG. 5 and according to the timing illustrated in FIG. 7 and discussed above. Utilizing the configuration of FIG. 8 in a design implementation where pixel area is limited by the TFT device count, sharing of the second and third switch transistors 840850 between two or more adjacent sub-pixels reduces the effective device count per subpixel.


With reference to FIG. 9, a first subpixel 901A and second subpixel 901B each include a first switch transistor 930A 930B, a driving transistor 910A 910B, a light emitting device 920A 920B, and a reset transistor 970A 970B as shown and described in association with the 5T1C pixel circuit 600 of FIG. 6. The first and second subpixels 901A 901B, however, share the node VS common and between the driving transistors 910A 910B and the storage capacitors 960A 960B. Also shared between the first and second subpixels 901A 901B, are a third switch transistor 950 (T4) coupled between the node VS and ELVDD, and a second switch transistor 940 (T3) coupled between the node VS and the monitor line VMON. The gate terminal of the third switch transistor 950 is coupled to an emission signal line (EMi) of the ith row, while the first terminal of the third switch transistor 950 is coupled to the first reference potential ELVDD, and the second terminal of the third switch transistor 950 is coupled to node VS which is common to the second terminal of the storage capacitors 960A 960B. The gate terminal of the second switch transistor 940 is coupled to a write signal line (WRi) of the ith row, while the first terminal of the second switch transistor 940 is coupled to a monitor line (VMON), and the second terminal of the second switch transistor 940 is also coupled to the node VS.


Each of the first and second subpixels 901A 901B functions the same as the 5T1C pixel circuit 600 of FIG. 6 and according to the timing illustrated in FIG. 7 and discussed above. Utilizing the configuration of FIG. 9 in a design implementation where pixel area is limited by the TFT device count, sharing of the second and third switch transistors 940950 between two or more adjacent sub-pixels reduces the effective device count per subpixel. Additionally, as with the embodiment of FIG. 6, the utilization of write signal line WRi and WRi−1 only (without the use of read lines RDi and RDi−1) simplifies row (gate) control signals required per row of pixels of the display system 150.


With reference to FIG. 10, an alternate example of a display timing 1000 for the 4T1C pixel circuit 300 depicted in FIG. 3 which includes both reset and in pixel compensation will now be described. The complete display timing 1000 occurs typically once per frame and includes a rest cycle 1004, a programming cycle 1010, a compensation cycle 1020, a settling cycle 1030, and an emission cycle 1040. The write signal (WRi) is held low throughout the reset, programming, and calibration cycles 100410101020, keeping the data line voltage VDATA coupled to VG. For the embodiment of FIG. 4, the supply voltage ELVDD of the 4T1C pixel circuit 300 of FIG. 3 is controllable.


During the reset cycle 1004, the emission signal (EMi) is held high while the read signal (RDi) is held low ensuring the third switch transistor 350 is OFF and the second switch transistor 340 is ON exposing the node VS to the voltage on the monitor line VMON. Also during the reset cycle 1004 the voltage on the monitor line VMON is set to 0 volts and the voltage of the data line is set at a pixel data level (typically 6 to 9 volts), giving rise to a negative VSG of 6 to 9 volts. The driving transistor 310 being negatively biased triggers the release of carriers and hence reversal of the short-term trapping of carriers, resetting the driving transistor 310 and its threshold voltage (VTH), and mitigating hysteresis in the I-V response exhibited by the driving transistor 310 when it is programmed in the following programming cycle 1010.


During the programming cycle 1010 the read signal (RDi) goes high turning OFF the second switch transistor 340 and the emission signal (EMi) goes low turning ON the third switch transistor 350. The voltage ELVDD is set to a reference voltage VREF (similar to, for example, the reference voltage VMON described in association with FIG. 4, and provided on the monitor line during programming cycle 410). Since the first switch transistor 330 and the third switch transistor 350 are both ON, the voltage of the storage capacitor 360 and therefore the voltage VSG of the driving transistor 310 is charged to a value of VREF−VDATA. These voltages are set in accordance with a desired programming voltage for causing the pixel 300 to emit light at a desired luminance according to image data.


At the beginning of the calibration cycle 1020, the emission signal (EMi) goes high to turn OFF the third switch transistor 350 to discharge some of the voltage (charge) of the storage capacitor 360 through the driving transistor 310. The amount discharged is a function of the characteristics of the driving transistor 310. For example, if the driving transistor 310 is “strong”, the discharge occurs relatively quickly and relatively more charge is discharged from the storage capacitor 360 through the driving transistor 310 during the fixed duration of the calibration cycle 420. On the other hand, if the driving transistor 310 is “weak”, the discharge occurs relatively slowly and relatively less charge is discharged from the storage capacitor 360 through the driving transistor 310 during the calibration cycle 1020. As a result, the voltage (charge) stored in the storage capacitor 360 (VP) is reduced comparatively more for relatively strong driving transistors versus comparatively less for relatively weak driving transistors, thereby providing some compensation for non-uniformity and variations in the driving transistors across the display whether due to variations in fabrication, variations in degradation over time, or variations due to hysteresis in the temporary threshold voltage of the driving transistor 310.


After the calibration cycle 1020, a settling cycle 1030 is performed prior to the emission. During the settling cycle 1030 the second and third switch transistors 340, 350 remain OFF, while the write signal (WRi) goes high to also turn OFF the first switch transistor 330. After completion of the duration of the settling cycle 1030 at the start of the emission cycle 1040, ELVDD is set to the standard positive reference ELVDD rail instead of VREF, and the emission signal (EMi) goes low turning ON the third switch transistor 350 allowing current to flow through the light emitting device 320 according to the calibrated stored voltage on the storage capacitor 360.


Driven in this manner, in conjunction with a controllable positive reference potential ELVDD, the pixel 300 circuit is capable of achieving in-pixel compensation including that related to hysteresis to a good level for high and medium grayscales, as well as performing a reset cycle for directly reducing hysteresis effects on the threshold voltage of the driving transistor 310 caused by trapped carriers, which better address low grayscale compensation required to meet high-end uniformity specifications.


While particular implementations and applications of the present disclosure have been illustrated and described, it is to be understood that the present disclosure is not limited to the precise construction and compositions disclosed herein and that various modifications, changes, and variations can be apparent from the foregoing descriptions without departing from the spirit and scope of an invention as defined in the appended claims.

Claims
  • 1. A display system comprising: an array of pixel circuits arranged in rows and columns, each pixel circuit including: a driving transistor;a storage capacitor coupled across a gate terminal and a first terminal of the driving transistor;a light emitting device coupled to a second terminal of the driving transistor; anda reset switch transistor coupled between a first reference potential and a node common to a first terminal of the storage capacitor and the gate terminal of the driving transistor; anda controller for driving each pixel circuit during each frame over a plurality of operation cycles for the pixel circuit including a programming cycle for programming the storage capacitor of the pixel circuit, and a reset cycle prior to the programming cycle for resetting the driving transistor of the pixel circuit, the controller resetting the driving transistor of the pixel circuit by activating the reset switch transistor of the pixel circuit during the reset cycle to expose the node of the pixel circuit to the reference potential which causes reverse biasing across the gate and first terminal of the driving transistor.
  • 2. The display system of claim 1 wherein the controller activates the reset switch transistor of the pixel circuit during the reset cycle of the pixel circuit with a control signal used for controlling a programming of another pixel circuit during the programming cycle of the another pixel circuit.
  • 3. The display system of claim 2 wherein the pixel circuit is of one row other than another row of the another pixel circuit.
  • 4. The display system of claim 3 wherein the one row and the another row are adjacent rows.
  • 5. The display system of claim 4 wherein the controller programs the pixel circuit during the programming cycle of the pixel circuit using a write signal for the one row for controlling a first switch transistor for coupling a data line with the storage capacitor of the pixel circuit and using a read signal for the one row for controlling a second switch transistor for coupling a monitor line with the storage capacitor of the pixel circuit, wherein the control signal used for controlling the programming of the another pixel circuit is one of a write signal and a read signal for the another row.
  • 6. The display system of claim 5 wherein the controller further is for driving each pixel circuit over a plurality of operation cycles including a compensation cycle and a settling cycle after the programming cycle, during the compensation cycle the controller using the read signal to deactivate the second switch transistor to decouple the monitor line from the storage capacitor of the pixel circuit allowing the storage capacitor to discharge through the driving transistor of the pixel circuit during the compensation cycle.
  • 7. The display system of claim 5 further comprising a third switch transistor shared by at least a first and a second pixel circuit of the one row, wherein the second switch transistor is shared by the at least a first and a second pixel circuit, wherein the controller programs the at least a first and a second pixel circuit during the programming cycle using the read signal for the one row for controlling the shared second switch transistor for coupling the monitor line with the storage capacitors of the at least a first and a second pixel circuit, wherein the controller further is for driving each pixel circuit over a plurality of operation cycles including an emission cycle after the programming cycle, during the emission cycle the controller using an emission signal line to control the third switch transistor to couple the driving transistors of the at least a first and a second pixel circuit to the first reference potential.
  • 8. The display system of claim 4 wherein the controller programs the pixel circuit during the programming cycle of the first circuit using a write signal for the one row for controlling a first switch transistor for coupling a data line with the storage capacitor of the pixel circuit and for controlling a second switch transistor for coupling a monitor line with the storage capacitor of the pixel circuit, wherein the control signal used for controlling the programming of the another pixel is a write signal for the another row.
  • 9. The display system of claim 8 further comprising a third switch transistor shared by at least a first and a second pixel circuit of the one row, wherein the second switch transistor is shared by the at least a first and a second pixel circuit, wherein the controller further is for driving each pixel circuit over a plurality of operation cycles including an emission cycle after the programming cycle, during the emission cycle the controller using an emission signal line to control the third switch transistor to couple the driving transistors of the at least a first and a second pixel circuit to the first reference potential.
  • 10. A method of driving a display system, the display system including an array of pixel circuits arranged in rows and columns, each pixel circuit including: a driving transistor;a storage capacitor coupled across a gate terminal and a first terminal of the driving transistor;a light emitting device coupled to a second terminal of the driving transistor; anda reset switch transistor coupled between a first reference potential and a node common to a first terminal of the storage capacitor and the gate terminal of the driving transistor; the method comprising:driving each pixel circuit during each frame over a plurality of operation cycles for the pixel circuit including a programming cycle and a reset cycle, comprising: during the programming cycle, programming the storage capacitor of the pixel circuit, andduring a reset cycle prior to the programming cycle, resetting the driving transistor of the pixel circuit by activating the reset switch transistor of the pixel circuit during the reset cycle to expose the node of the pixel circuit to the reference potential which causes reverse biasing across the gate and first terminal of the driving transistor.
  • 11. The method of claim 10 wherein resetting the driving transistor comprises activating the reset switch transistor of the pixel circuit with a control signal used for controlling a programming of another pixel circuit during the programming cycle of the another pixel circuit.
  • 12. The method of claim 11 wherein the pixel circuit is of one row other than another row of the another pixel circuit.
  • 13. The method of claim 12 wherein the one row and the another row are adjacent rows.
  • 14. The method of claim 13 further comprising, programming the pixel circuit during the programming cycle using a write signal for the one row for controlling a first switch transistor for coupling a data line with the storage capacitor of the pixel circuit and using a read signal for the one row for controlling a second switch transistor for coupling a monitor line with the storage capacitor of the pixel circuit, wherein the control signal used for controlling the programming of the another pixel circuit is one of a write signal and a read signal for the another row.
  • 15. The method of claim 14 wherein the plurality of operation cycles includes a compensation cycle and a settling cycle, wherein driving each pixel circuit further comprises after the programming cycle, during compensation cycle, deactivating the second switch transistor using the read signal to decouple the monitor line from the storage capacitor of the pixel circuit allowing the storage capacitor to discharge through the driving transistor of the pixel circuit during the compensation cycle.
  • 16. The method of claim 13 further comprising, programming the pixel circuit during the programming cycle using a write signal for the one row for controlling a first switch transistor for coupling a data line with the storage capacitor of the pixel circuit and for controlling a second switch transistor for coupling a monitor line with the storage capacitor of the pixel circuit, wherein the control signal used for controlling the programming of the another pixel is a write signal for the another row.
  • 17. A display system comprising: an array of pixel circuits arranged in rows and columns, each pixel circuit including: a driving transistor;a storage capacitor coupled across a gate terminal and a first terminal of the driving transistor;a light emitting device coupled to a second terminal of the driving transistor; anda switch transistor coupled between a reference voltage and a node common to a first terminal of the storage capacitor and the first terminal of the driving transistor; anda controller for driving each pixel circuit during each frame over a plurality of operation cycles for the pixel circuit including a programming cycle for programming the storage capacitor of the pixel circuit, and a reset cycle prior to the programming cycle for resetting the driving transistor of the pixel circuit, the controller resetting the driving transistor of the pixel circuit by activating the switch transistor of the pixel circuit during the reset cycle to expose the node of the pixel circuit to the reference voltage which is set to a voltage to cause reverse biasing across the gate and first terminal of the driving transistor.
  • 18. The display system of claim 17 wherein the controller programs the pixel circuit during the programming cycle of the pixel circuit by deactivating the switch transistor, activating a first switch transistor for coupling a data line with the storage capacitor and the gate terminal of the driving transistor of the pixel circuit and activating a second switch transistor for coupling a controllable reference potential with the node of the pixel circuit.
  • 19. The display system of claim 18 wherein the controller further is for driving each pixel circuit over a plurality of operation cycles including a compensation cycle and a settling cycle after the programming cycle, during the compensation cycle the controller deactivating the second switch transistor to decouple the controllable reference potential from the node of the pixel circuit allowing the storage capacitor to discharge through the driving transistor of the pixel circuit during the compensation cycle.
  • 20. A method of driving a display system, the display system including an array of pixel circuits arranged in rows and columns, each pixel circuit including: a driving transistor;a storage capacitor coupled across a gate terminal and a first terminal of the driving transistor;a light emitting device coupled to a second terminal of the driving transistor; anda switch transistor coupled between a reference voltage and a node common to a first terminal of the storage capacitor and the first terminal of the driving transistor; the method comprising:driving each pixel circuit during each frame over a plurality of operation cycles for the pixel circuit including a programming cycle and a reset cycle, comprising: during the programming cycle, programming the storage capacitor of the pixel circuit, andduring a reset cycle prior to the programming cycle, resetting the driving transistor of the pixel circuit by activating the switch transistor of the pixel circuit during the reset cycle to expose the node of the pixel circuit to the reference voltage which is set to a voltage to cause reverse biasing across the gate and first terminal of the driving transistor.
  • 21. The method of claim 20 further comprising, programming the pixel circuit during the programming cycle by deactivating the switch transistor, activating a first switch transistor for coupling a data line with the storage capacitor and the gate terminal of the driving transistor of the pixel circuit, and activating a second switch transistor for coupling a controllable reference potential with the node of the pixel circuit.
  • 22. The method of claim 21 wherein the plurality of operation cycles includes a compensation cycle and a settling cycle, wherein driving each pixel circuit further comprises after the programming cycle, during the compensation cycle, deactivating the second switch transistor to decouple the controllable reference potential from the node of the pixel circuit allowing the storage capacitor to discharge through the driving transistor of the pixel circuit during the compensation cycle.
PRIORITY CLAIM

This application claims priority to U.S. Provisional Application No. 62/430,437, filed Dec. 6, 2016, which is hereby incorporated by reference in its entirety.

US Referenced Citations (372)
Number Name Date Kind
4354162 Wright Oct 1982 A
4758831 Kasahara et al. Jul 1988 A
4963860 Stewart Oct 1990 A
4975691 Lee Dec 1990 A
4996523 Bell et al. Feb 1991 A
5051739 Hayashida et al. Sep 1991 A
5222082 Plus Jun 1993 A
5266515 Robb et al. Nov 1993 A
5498880 Lee et al. Mar 1996 A
5589847 Lewis Dec 1996 A
5619033 Weisfield Apr 1997 A
5648276 Hara et al. Jul 1997 A
5670973 Bassetti et al. Sep 1997 A
5684365 Tang et al. Nov 1997 A
5686935 Weisbrod Nov 1997 A
5712653 Katoh et al. Jan 1998 A
5714968 Ikeda Feb 1998 A
5747928 Shanks et al. May 1998 A
5748160 Shieh et al. May 1998 A
5784042 Ono et al. Jul 1998 A
5790234 Matsuyama Aug 1998 A
5815303 Berlin Sep 1998 A
5870071 Kawahata Feb 1999 A
5874803 Garbuzov et al. Feb 1999 A
5880582 Sawada Mar 1999 A
5903248 Irwin May 1999 A
5917280 Burrows et al. Jun 1999 A
5923794 McGrath et al. Jul 1999 A
5952789 Stewart et al. Sep 1999 A
5990629 Yamada et al. Nov 1999 A
6023259 Howard et al. Feb 2000 A
6069365 Chow et al. May 2000 A
6081131 Ishii Jun 2000 A
6091203 Kawashima et al. Jul 2000 A
6097360 Holloman Aug 2000 A
6144222 Ho Nov 2000 A
6157583 Starnes et al. Dec 2000 A
6166489 Thompson et al. Dec 2000 A
6177915 Beeteson et al. Jan 2001 B1
6225846 Wada et al. May 2001 B1
6229508 Kane May 2001 B1
6232939 Saito et al. May 2001 B1
6246180 Nishigaki Jun 2001 B1
6252248 Sano et al. Jun 2001 B1
6259424 Kurogane Jul 2001 B1
6274887 Yamazaki et al. Aug 2001 B1
6288696 Holloman Sep 2001 B1
6300928 Kim Oct 2001 B1
6303963 Ohtani et al. Oct 2001 B1
6306694 Yamazaki et al. Oct 2001 B1
6307322 Dawson et al. Oct 2001 B1
6316786 Mueller et al. Nov 2001 B1
6320325 Cok et al. Nov 2001 B1
6323631 Juang Nov 2001 B1
6323832 Nishizawa et al. Nov 2001 B1
6345085 Yeo et al. Feb 2002 B1
6348835 Sato et al. Feb 2002 B1
6365917 Yamazaki Apr 2002 B1
6373453 Yudasaka Apr 2002 B1
6384427 Yamazaki et al. May 2002 B1
6392617 Gleason May 2002 B1
6399988 Yamazaki Jun 2002 B1
6414661 Shen et al. Jul 2002 B1
6420758 Nakajima Jul 2002 B1
6420834 Yamazaki et al. Jul 2002 B2
6420988 Azami et al. Jul 2002 B1
6433488 Bu Aug 2002 B1
6445376 Parrish Sep 2002 B2
6468638 Jacobsen et al. Oct 2002 B2
6489952 Tanaka et al. Dec 2002 B1
6501098 Yamazaki Dec 2002 B2
6501466 Yamagashi et al. Dec 2002 B1
6512271 Yamazaki et al. Jan 2003 B1
6518594 Nakajima et al. Feb 2003 B1
6524895 Yamazaki et al. Feb 2003 B2
6531713 Yamazaki Mar 2003 B1
6559594 Fukunaga et al. May 2003 B2
6573195 Yamazaki et al. Jun 2003 B1
6573584 Nagakari et al. Jun 2003 B1
6576926 Yamazaki et al. Jun 2003 B1
6577302 Hunter Jun 2003 B2
6580408 Bae et al. Jun 2003 B1
6580657 Sanford et al. Jun 2003 B2
6583775 Sekiya et al. Jun 2003 B1
6583776 Yamazaki et al. Jun 2003 B2
6587086 Koyama Jul 2003 B1
6593691 Nishi et al. Jul 2003 B2
6594606 Everitt Jul 2003 B2
6597203 Forbes Jul 2003 B2
6611108 Kimura Aug 2003 B2
6617644 Yamazaki et al. Sep 2003 B1
6618030 Kane et al. Sep 2003 B2
6641933 Yamazaki et al. Nov 2003 B1
6661180 Koyama Dec 2003 B2
6661397 Mikami et al. Dec 2003 B2
6670637 Yamazaki et al. Dec 2003 B2
6677713 Sung Jan 2004 B1
6680577 Inukai et al. Jan 2004 B1
6687266 Ma et al. Feb 2004 B1
6690344 Takeuchi et al. Feb 2004 B1
6693388 Oomura Feb 2004 B2
6693610 Shannon et al. Feb 2004 B2
6697057 Koyama et al. Feb 2004 B2
6720942 Lee et al. Apr 2004 B2
6734636 Sanford et al. May 2004 B2
6738034 Kaneko et al. May 2004 B2
6738035 Fan May 2004 B1
6771028 Winters Aug 2004 B1
6777712 Sanford et al. Aug 2004 B2
6780687 Nakajima et al. Aug 2004 B2
6806638 Lih et al. Oct 2004 B2
6806857 Sempel et al. Oct 2004 B2
6809706 Shimoda Oct 2004 B2
6859193 Yumoto Feb 2005 B1
6861670 Ohtani et al. Mar 2005 B1
6873117 Ishizuka Mar 2005 B2
6873320 Nakamura Mar 2005 B2
6878968 Ohnuma Apr 2005 B1
6909114 Yamazaki Jun 2005 B1
6909419 Zavracky et al. Jun 2005 B2
6919871 Kwon Jul 2005 B2
6937215 Lo Aug 2005 B2
6940214 Komiya et al. Sep 2005 B1
6943500 LeChevalier Sep 2005 B2
6954194 Matsumoto et al. Oct 2005 B2
6956547 Bae et al. Oct 2005 B2
6995510 Murakami et al. Feb 2006 B2
6995519 Arnold et al. Feb 2006 B2
7022556 Adachi Apr 2006 B1
7023408 Chen et al. Apr 2006 B2
7027015 Booth, Jr. et al. Apr 2006 B2
7034793 Sekiya et al. Apr 2006 B2
7088051 Cok Aug 2006 B1
7106285 Naugler Sep 2006 B2
7116058 Lo et al. Oct 2006 B2
7129914 Knapp et al. Oct 2006 B2
7129917 Yamazaki et al. Oct 2006 B2
7141821 Yamazaki et al. Nov 2006 B1
7161566 Cok et al. Jan 2007 B2
7193589 Yoshida et al. Mar 2007 B2
7199516 Seo et al. Apr 2007 B2
7220997 Nakata May 2007 B2
7235810 Yamazaki et al. Jun 2007 B1
7245277 Ishizuka Jul 2007 B2
7248236 Nathan et al. Jul 2007 B2
7264979 Yamagata et al. Sep 2007 B2
7274345 Imamura et al. Sep 2007 B2
7274363 Ishizuka et al. Sep 2007 B2
7279711 Yamazaki et al. Oct 2007 B1
7304621 Oomori et al. Dec 2007 B2
7310092 Imamura Dec 2007 B2
7315295 Kimura Jan 2008 B2
7317429 Shirasaki et al. Jan 2008 B2
7319465 Mikami et al. Jan 2008 B2
7321348 Cok et al. Jan 2008 B2
7339636 Voloschenko et al. Mar 2008 B2
7355574 Leon et al. Apr 2008 B1
7358941 Ono et al. Apr 2008 B2
7402467 Kadono et al. Jul 2008 B1
7414600 Nathan et al. Aug 2008 B2
7432885 Asano et al. Oct 2008 B2
7474285 Kimura Jan 2009 B2
7485478 Yamagata et al. Feb 2009 B2
7502000 Yuki et al. Mar 2009 B2
7535449 Miyazawa May 2009 B2
7554512 Steer Jun 2009 B2
7569849 Nathan et al. Aug 2009 B2
7619594 Hu Nov 2009 B2
7619597 Nathan et al. Nov 2009 B2
7697052 Yamazaki et al. Apr 2010 B1
7825419 Yamagata et al. Nov 2010 B2
7859492 Kohno Dec 2010 B2
7868859 Tomida et al. Jan 2011 B2
7876294 Sasaki et al. Jan 2011 B2
7948170 Striakhilev et al. May 2011 B2
7948456 Yamashita May 2011 B2
7969390 Yoshida Jun 2011 B2
7995010 Yamazaki et al. Aug 2011 B2
8044893 Nathan et al. Oct 2011 B2
8115707 Nathan et al. Feb 2012 B2
8378362 Heo et al. Feb 2013 B2
8493295 Yamazaki et al. Jul 2013 B2
8497525 Yamagata et al. Jul 2013 B2
9385169 Chaji et al. Jul 2016 B2
9606607 Chaji Mar 2017 B2
9633597 Nathan et al. Apr 2017 B2
9728135 Nathan et al. Aug 2017 B2
9741292 Nathan et al. Aug 2017 B2
20010002703 Koyama Jun 2001 A1
20010004190 Nishi et al. Jun 2001 A1
20010013806 Notani Aug 2001 A1
20010015653 De Jong et al. Aug 2001 A1
20010020926 Kujik Sep 2001 A1
20010024186 Kane Sep 2001 A1
20010026127 Yoneda et al. Oct 2001 A1
20010026179 Saeki Oct 2001 A1
20010026257 Kimura Oct 2001 A1
20010030323 Ikeda Oct 2001 A1
20010033199 Aoki Oct 2001 A1
20010038098 Yamazaki et al. Nov 2001 A1
20010043173 Troutman Nov 2001 A1
20010045929 Prache et al. Nov 2001 A1
20010052006 Sempel et al. Dec 2001 A1
20010052898 Osame et al. Dec 2001 A1
20020000576 Inukai Jan 2002 A1
20020011796 Koyama Jan 2002 A1
20020011799 Kimura Jan 2002 A1
20020011981 Kujik Jan 2002 A1
20020015031 Fujita et al. Feb 2002 A1
20020015032 Koyama et al. Feb 2002 A1
20020030528 Matsumoto et al. Mar 2002 A1
20020030647 Hack et al. Mar 2002 A1
20020036463 Yoneda et al. Mar 2002 A1
20020047852 Inukai et al. Apr 2002 A1
20020048829 Yamazaki et al. Apr 2002 A1
20020050795 Imura May 2002 A1
20020053401 Ishikawa et al. May 2002 A1
20020070909 Asano et al. Jun 2002 A1
20020080108 Wang Jun 2002 A1
20020084463 Sanford et al. Jul 2002 A1
20020101172 Bu Aug 2002 A1
20020101433 McKnight Aug 2002 A1
20020113248 Yamagata et al. Aug 2002 A1
20020122308 Ikeda Sep 2002 A1
20020130686 Forbes Sep 2002 A1
20020154084 Tanaka et al. Oct 2002 A1
20020158823 Zavracky et al. Oct 2002 A1
20020163314 Yamazaki et al. Nov 2002 A1
20020167471 Everitt Nov 2002 A1
20020180369 Koyama Dec 2002 A1
20020180721 Kimura et al. Dec 2002 A1
20020186214 Siwinski Dec 2002 A1
20020190332 Lee et al. Dec 2002 A1
20020190924 Asano et al. Dec 2002 A1
20020190971 Nakamura et al. Dec 2002 A1
20020195967 Kim et al. Dec 2002 A1
20020195968 Sanford et al. Dec 2002 A1
20030020413 Oomura Jan 2003 A1
20030030603 Shimoda Feb 2003 A1
20030062524 Kimura Apr 2003 A1
20030063081 Kimura et al. Apr 2003 A1
20030071804 Yamazaki et al. Apr 2003 A1
20030071821 Sundahl Apr 2003 A1
20030076048 Rutherford Apr 2003 A1
20030090445 Chen et al. May 2003 A1
20030090447 Kimura May 2003 A1
20030090481 Kimura May 2003 A1
20030095087 Libsch May 2003 A1
20030107560 Yumoto et al. Jun 2003 A1
20030111966 Mikami et al. Jun 2003 A1
20030122745 Miyazawa Jul 2003 A1
20030140958 Yang et al. Jul 2003 A1
20030151569 Lee et al. Aug 2003 A1
20030169219 LeChevalier Sep 2003 A1
20030174152 Noguchi Sep 2003 A1
20030178617 Appenzeller et al. Sep 2003 A1
20030179626 Sanford et al. Sep 2003 A1
20030197663 Lee et al. Oct 2003 A1
20030206060 Suzuki Nov 2003 A1
20030230980 Forrest et al. Dec 2003 A1
20040027063 Nishikawa Feb 2004 A1
20040056604 Shih et al. Mar 2004 A1
20040066357 Kawasaki Apr 2004 A1
20040070557 Asano et al. Apr 2004 A1
20040080262 Park et al. Apr 2004 A1
20040080470 Yamazaki et al. Apr 2004 A1
20040090400 Yoo May 2004 A1
20040108518 Jo Jun 2004 A1
20040113903 Mikami et al. Jun 2004 A1
20040129933 Nathan et al. Jul 2004 A1
20040130516 Nathan et al. Jul 2004 A1
20040135749 Kondakov et al. Jul 2004 A1
20040145547 Oh Jul 2004 A1
20040150592 Mizukoshi et al. Aug 2004 A1
20040150594 Koyama et al. Aug 2004 A1
20040150595 Kasai Aug 2004 A1
20040155841 Kasai Aug 2004 A1
20040174347 Sun et al. Sep 2004 A1
20040174349 Libsch Sep 2004 A1
20040183759 Stevenson et al. Sep 2004 A1
20040189627 Shirasaki et al. Sep 2004 A1
20040196275 Hattori Oct 2004 A1
20040201554 Satoh Oct 2004 A1
20040207615 Yumoto Oct 2004 A1
20040233125 Tanghe et al. Nov 2004 A1
20040239596 Ono et al. Dec 2004 A1
20040252089 Ono et al. Dec 2004 A1
20040257355 Naugler Dec 2004 A1
20040263437 Hattori Dec 2004 A1
20050007357 Yamashita et al. Jan 2005 A1
20050030267 Tanghe et al. Feb 2005 A1
20050035709 Furuie et al. Feb 2005 A1
20050067970 Libsch et al. Mar 2005 A1
20050067971 Kane Mar 2005 A1
20050068270 Awakura Mar 2005 A1
20050088085 Nishikawa et al. Apr 2005 A1
20050088103 Kageyama et al. Apr 2005 A1
20050110420 Arnold et al. May 2005 A1
20050117096 Voloschenko et al. Jun 2005 A1
20050140598 Kim et al. Jun 2005 A1
20050140610 Smith et al. Jun 2005 A1
20050145891 Abe Jul 2005 A1
20050156831 Yamazaki et al. Jul 2005 A1
20050168416 Hashimoto et al. Aug 2005 A1
20050206590 Sasaki et al. Sep 2005 A1
20050225686 Brummack et al. Oct 2005 A1
20050260777 Brabec et al. Nov 2005 A1
20050269959 Uchino et al. Dec 2005 A1
20050269960 Ono et al. Dec 2005 A1
20050285822 Reddy et al. Dec 2005 A1
20050285825 Eom et al. Dec 2005 A1
20060007072 Choi et al. Jan 2006 A1
20060012310 Chen et al. Jan 2006 A1
20060027807 Nathan et al. Feb 2006 A1
20060030084 Young Feb 2006 A1
20060038758 Routley et al. Feb 2006 A1
20060044227 Hadcock Mar 2006 A1
20060066527 Chou Mar 2006 A1
20060092185 Jo et al. May 2006 A1
20060232522 Roy et al. Oct 2006 A1
20060261841 Fish Nov 2006 A1
20060264143 Lee et al. Nov 2006 A1
20060273997 Nathan et al. Dec 2006 A1
20060284801 Yoon et al. Dec 2006 A1
20070001937 Park et al. Jan 2007 A1
20070001939 Hashimoto et al. Jan 2007 A1
20070008268 Park et al. Jan 2007 A1
20070008297 Bassetti Jan 2007 A1
20070046195 Chin et al. Mar 2007 A1
20070069998 Naugler et al. Mar 2007 A1
20070080905 Takahara Apr 2007 A1
20070080906 Tanabe Apr 2007 A1
20070080908 Nathan et al. Apr 2007 A1
20070080918 Kawachi et al. Apr 2007 A1
20070103419 Uchino et al. May 2007 A1
20070182671 Nathan et al. Aug 2007 A1
20070273294 Nagayama Nov 2007 A1
20070285359 Ono Dec 2007 A1
20070296672 Kim et al. Dec 2007 A1
20080012835 Rimon et al. Jan 2008 A1
20080042948 Yamashita et al. Feb 2008 A1
20080055209 Cok Mar 2008 A1
20080074413 Ogura Mar 2008 A1
20080088549 Nathan et al. Apr 2008 A1
20080122803 Izadi et al. May 2008 A1
20080230118 Nakatani et al. Sep 2008 A1
20090032807 Shinohara et al. Feb 2009 A1
20090051283 Cok et al. Feb 2009 A1
20090160743 Tomida et al. Jun 2009 A1
20090162961 Deane Jun 2009 A1
20090174628 Wang et al. Jul 2009 A1
20090179838 Yamashita Jul 2009 A1
20090213046 Nam Aug 2009 A1
20100039422 Seto Feb 2010 A1
20100052524 Kinoshita Mar 2010 A1
20100078230 Rosenblatt et al. Apr 2010 A1
20100079711 Tanaka Apr 2010 A1
20100097335 Jung et al. Apr 2010 A1
20100133994 Song et al. Jun 2010 A1
20100134456 Oyamada Jun 2010 A1
20100140600 Clough et al. Jun 2010 A1
20100156279 Tamura et al. Jun 2010 A1
20100237374 Chu et al. Sep 2010 A1
20100328294 Sasaki et al. Dec 2010 A1
20110090210 Sasaki et al. Apr 2011 A1
20110133636 Matsuo et al. Jun 2011 A1
20110148801 Bateman et al. Jun 2011 A1
20110180825 Lee et al. Jul 2011 A1
20120212468 Govil Aug 2012 A1
20130009930 Cho et al. Jan 2013 A1
20130032831 Chaji et al. Feb 2013 A1
20130113785 Sumi May 2013 A1
Foreign Referenced Citations (89)
Number Date Country
1294034 Jan 1992 CA
2109951 Nov 1992 CA
2 249 592 Jul 1998 CA
2 368 386 Sep 1999 CA
2 242 720 Jan 2000 CA
2 354 018 Jun 2000 CA
2 436 451 Aug 2002 CA
2 438 577 Aug 2002 CA
2 483 645 Dec 2003 CA
2 463 653 Jan 2004 CA
2498136 Mar 2004 CA
2522396 Nov 2004 CA
2443206 Mar 2005 CA
2472671 Dec 2005 CA
2567076 Jan 2006 CA
2526782 Apr 2006 CA
1381032 Nov 2002 CN
1448908 Oct 2003 CN
1776922 May 2006 CN
101032027 Sep 2007 CN
101256293 Sep 2008 CN
101727237 Jun 2010 CN
102799331 Nov 2012 CN
102955600 Mar 2013 CN
20 2006 005427 Jun 2006 DE
0 940 796 Sep 1999 EP
1 028 471 Aug 2000 EP
1 103 947 May 2001 EP
1 130 565 Sep 2001 EP
1 184 833 Mar 2002 EP
1 194 013 Apr 2002 EP
1 310 939 May 2003 EP
1 335 430 Aug 2003 EP
1 372 136 Dec 2003 EP
1 381 019 Jan 2004 EP
1 418 566 May 2004 EP
1 429 312 Jun 2004 EP
1 439 520 Jul 2004 EP
1 465 143 Oct 2004 EP
1 467 408 Oct 2004 EP
1 517 290 Mar 2005 EP
1 521 203 Apr 2005 EP
2317499 May 2011 EP
2 205 431 Dec 1988 GB
09 090405 Apr 1997 JP
10-153759 Jun 1998 JP
10-254410 Sep 1998 JP
11 231805 Aug 1999 JP
11-282419 Oct 1999 JP
2000056847 Feb 2000 JP
2000-077192 Mar 2000 JP
2000-089198 Mar 2000 JP
2000-352941 Dec 2000 JP
2002-91376 Mar 2002 JP
2002-268576 Sep 2002 JP
2002-278513 Sep 2002 JP
2002-333862 Nov 2002 JP
2003-022035 Jan 2003 JP
2003-076331 Mar 2003 JP
2003-150082 May 2003 JP
2003-177709 Jun 2003 JP
2003-271095 Sep 2003 JP
2003-308046 Oct 2003 JP
2005-057217 Mar 2005 JP
2006065148 Mar 2006 JP
2009282158 Dec 2009 JP
485337 May 2002 TW
502233 Sep 2002 TW
538650 Jun 2003 TW
569173 Jan 2004 TW
WO 9425954 Nov 1994 WO
WO 9948079 Sep 1999 WO
WO 0127910 Apr 2001 WO
WO 02067327 Aug 2002 WO
WO 03034389 Apr 2003 WO
WO 03063124 Jul 2003 WO
WO 03077231 Sep 2003 WO
WO 03105117 Dec 2003 WO
WO 2004003877 Jan 2004 WO
WO 2004034364 Apr 2004 WO
WO 2005022498 Mar 2005 WO
WO 2005029455 Mar 2005 WO
WO 2005055185 Jun 2005 WO
WO 2006053424 May 2006 WO
WO 2006063448 Jun 2006 WO
WO 2006137337 Dec 2006 WO
WO 2007003877 Jan 2007 WO
WO 2007079572 Jul 2007 WO
WO 2010023270 Mar 2010 WO
Non-Patent Literature Citations (81)
Entry
Ahnood et al.: “Effect of threshold voltage instability on field effect mobility in thin film transistors deduced from constant current measurements”; dated Aug. 2009 (3 pages).
Alexander et al.: “Pixel circuits and drive schemes for glass and elastic AMOLED displays”; dated Jul. 2005 (9 pages).
Alexander et al.: “Unique Electrical Measurement Technology for Compensation, Inspection, and Process Diagnostics of AMOLED HDTV”; dated May 2010 (4 pages).
Ashtiani et al.: “AMOLED Pixel Circuit With Electronic Compensation of Luminance Degradation”; dated Mar. 2007 (4 pages).
Chaji et al.: “A Current-Mode Comparator for Digital Calibration of Amorphous Silicon AMOLED Displays”; dated Jul. 2008 (5 pages).
Chaji et al.: “A fast settling current driver based on the CCII for AMOLED displays”; dated Dec. 2009 (6 pages).
Chaji et al.: “A Low-Cost Stable Amorphous Silicon AMOLED Display with Full V˜T- and V˜O˜L˜E˜D Shift Compensation”; dated May 2007 (4 pages).
Chaji et al.: “A low-power driving scheme for a-Si:H active-matrix organic light-emitting diode displays”; dated Jun. 2005 (4 pages).
Chaji et al.: “A low-power high-performance digital circuit for deep submicron technologies”; dated Jun. 2005 (4 pages).
Chaji et al.: “A novel a-Si:H AMOLED pixel circuit based on short-term stress stability of a-Si:H TFTs”; dated Oct. 2005 (3 pages).
Chaji et al.: “A Novel Driving Scheme and Pixel Circuit for AMOLED Displays”; dated Jun. 2006 (4 pages).
Chaji et al.: “A novel driving scheme for high-resolution large-area a-Si:H AMOLED displays”; dated Aug. 2005 (4 pages).
Chaji et al.: “A Stable Voltage-Programmed Pixel Circuit for a-Si:H AMOLED Displays”; dated Dec. 2006 (12 pages).
Chaji et al.: “A Sub-μA fast-settling current-programmed pixel circuit for AMOLED displays”; dated Sep. 2007.
Chaji et al.: “An Enhanced and Simplified Optical Feedback Pixel Circuit for AMOLED Displays”; dated Oct. 2006.
Chaji et al.: “Compensation technique for DC and transient instability of thin film transistor circuits for large-area devices”; dated Aug. 2008.
Chaji et al.: “Driving scheme for stable operation of 2-TFT a-Si AMOLED pixel”; dated Apr. 2005 (2 pages).
Chaji et al.: “Dynamic-effect compensating technique for stable a-Si:H AMOLED displays”; dated Aug. 2005 (4 pages).
Chaji et al.: “Electrical Compensation of OLED Luminance Degradation”; dated Dec. 2007 (3 pages).
Chaji et al.: “eUTDSP: a design study of a new VLIW-based DSP architecture”; dated My 2003 (4 pages).
Chaji et al.: “Fast and Offset-Leakage Insensitive Current-Mode Line Driver for Active Matrix Displays and Sensors”; dated Feb. 2009 (8 pages).
Chaji et al.: “High Speed Low Power Adder Design With a New Logic Style: Pseudo Dynamic Logic (SDL)”; dated Oct. 2001 (4 pages).
Chaji et al.: “High-precision, fast current source for large-area current-programmed a-Si flat panels”; dated Sep. 2006 (4 pages).
Chaji et al.: “Low-Cost AMOLED Television with IGNIS Compensating Technology”; dated May 2008 (4 pages).
Chaji et al.: “Low-Cost Stable a-Si:H AMOLED Display for Portable Applications”; dated Jun. 2006 (4 pages).
Chaji et al.: “Low-Power Low-Cost Voltage-Programmed a-Si:H AMOLED Display”; dated Jun. 2008 (5 pages).
Chaji et al.: “Merged phototransistor pixel with enhanced near infrared response and flicker noise reduction for biomolecular imaging”; dated Nov. 2008 (3 pages).
Chaji et al.: “Parallel Addressing Scheme for Voltage-Programmed Active-Matrix OLED Displays”; dated May 2007 (6 pages).
Chaji et al.: “Pseudo dynamic logic (SDL): a high-speed and low-power dynamic logic family”; dated 2002 (4 pages).
Chaji et al.: “Stable a-Si:H circuits based on short-term stress stability of amorphous silicon thin film transistors”; dated May 2006 (4 pages).
Chaji et al.: “Stable Pixel Circuit for Small-Area High-Resolution a-Si:H AMOLED Displays”; dated Oct. 2008 (6 pages).
Chaji et al.: “Stable RGBW AMOLED display with OLED degradation compensation using electrical feedback”; dated Feb. 2010 (2 pages).
Chaji et al.: “Thin-Film Transistor Integration for Biomedical Imaging and AMOLED Displays”; dated 2008 (177 pages).
European Search Report and Written Opinion for Application No. 08 86 5338 dated Nov. 2, 2011 (7 pages).
European Search Report for European Application No. EP 04 78 6661 dated Mar. 9, 2009.
European Search Report for European Application No. EP 05 75 9141 dated Oct. 30, 2009 .
European Search Report for European Application No. EP 05 82 1114 dated Mar. 27, 2009 (2 pages).
European Search Report for European Application No. EP 07 71 9579 dated May 20, 2009.
European Search Report dated Mar. 26, 2012 in corresponding European Patent Application No. 10000421.7 (6 pages).
Extended European Search Report dated Apr. 27, 2011 issued during prosecution of European patent application No. 09733076.5 (13 pages).
Goh et al., “A New a-Si:H Thin Film Transistor Pixel Circul for Active-Matrix Organic Light-Emitting Diodes”, IEEE Electron Device Letters, vol. 24, No. 9, Sep. 2003, 4 pages.
International Search Report for International Application No. PCT/CA02/00180 dated Jul. 31, 2002 (3 pages).
International Search Report for International Application No. PCT/CA2004/001741 dated Feb. 21, 2005.
International Search Report for International Application No. PCT/CA2005/001844 dated Mar. 28, 2006 (2 pages).
International Search Report for International Application No. PCT/CA2005/001007 dated Oct. 18, 2005.
International Search Report for International Application No. PCT/CA2007/000652 dated Jul. 25, 2007.
International Search Report for International Application No. PCT/CA2008/002307, dated Apr. 28, 2009 (3 pages).
International Search Report for International Application No. PCT/IB2011/055135, Canadian Patent Office, dated Apr. 16, 2012 (5 pages).
International Search Report dated Jul. 30, 2009 for International Application No. PCT/CA2009/000501 (4 pages).
Jafarabadiashtiani et al.: “A New Driving Method for a-Si AMOLED Displays Based on Voltage Feedback”; dated 2005 (4 pages).
Lee et al.: “Ambipolar Thin-Film Transistors Fabricated by PECVD Nanocrystalline Silicon”; dated 2006 (6 pages).
Ma e y et al: “Organic Light-Emitting Diode/Thin Film Transistor Integration for foldable Displays” Conference record of the 1997 International display research conference and international workshops on LCD technology and emissive technology. Toronto, Sep. 15-19, 1997 (6 pages).
Matsueda y et al.: “35.1: 2.5-in. AMOLED with Integrated 6-bit Gamma Compensated Digital Data Driver”; dated May 2004.
Nathan et al.: “Backplane Requirements for Active Matrix Organic Light Emitting Diode Displays”; dated 2006 (16 pages).
Nathan et al.: “Call for papers second international workshop on compact thin-film transistor (TFT) modeling for circuit simulation”; dated Sep. 2009 (1 page).
Nathan et al.: “Driving schemes for a-Si and LTPS AMOLED displays”; dated Dec. 2005 (11 pages).
Nathan et al.: “Invited Paper: a -Si for AMOLED—Meeting the Performance and Cost Demands of Display Applications (Cell Phone to HDTV)”; dated 2006 (4 pages).
Nathan et al.: “Thin film imaging technology on glass and plastic” ICM 2000, Proceedings of the 12th International Conference on Microelectronics, (IEEE Cat. No. 00EX453), Tehran Iran; dated Oct. 31-Nov. 2, 2000, pp. 11-14, ISBN: 964-360-057-2, p. 13, col. 1, line 11-48; (4 pages).
Nathan et al., “Amorphous Silicon Thin Film Transistor Circuit Integration for Organic LED Displays on Glass and Plastic”, IEEE Journal of Solid-State Circuits, vol. 39, No. 9, Sep. 2004, pp. 1477-1486.
Office Action issued in Chinese Patent Application 200910246264.4 dated Jul. 5, 2013; 8 pages.
Patent Abstracts of Japan, vol. 2000, No. 09, Oct. 13, 2000—JP 2000 172199 A, Jun. 3, 2000, abstract.
Patent Abstracts of Japan, vol. 2002, No. 03, Apr. 3, 2002 (Apr. 4, 2004 & JP 2001 318627 A (Semiconductor EnergyLab DO Ltd), Nov. 16, 2001, abstract, paragraphs '01331-01801, paragraph '01691, paragraph '01701, paragraph '01721 and figure 10.
Philipp: “Charge transfer sensing” Sensor Review, vol. 19, No. 2, Dec. 31, 1999 (Dec. 31, 1999), 10 pages.
Rafati et al.: “Comparison of a 17 b multiplier in Dual-rail domino and in Dual-rail D L (D L) logic styles”; dated 2002 (4 pages).
Safavaian et al.: “Three-TFT image sensor for real-time digital X-ray imaging”; dated Feb. 2, 2006 (2 pages).
Safavian et al.: “3-TFT active pixel sensor with correlated double sampling readout circuit for real-time medical x-ray imaging”; dated Jun. 2006 (4 pages).
Safavian et al.: “A novel current scaling active pixel sensor with correlated double sampling readout circuit for real time medical x-ray imaging”; dated May 2007 (7 pages).
Safavian et al.: “A novel hybrid active-passive pixel with correlated double sampling CMOS readout circuit for medical x-ray imaging”; dated May 2008 (4 pages).
Safavian et al.: “Self-compensated a-Si:H detector with current-mode readout circuit for digital X-ray fluoroscopy”; dated Aug. 2005 (4 pages).
Safavian et al.: “TFT active image sensor with current-mode readout circuit for digital x-ray fluoroscopy [5969D-82]”; dated Sep. 2005 (9 pages).
Sanford, James L., et al., “4.2 TFT AMOLED Pixel Circuits and Driving Methods”, SID 03 Digest, ISSN/0003, 2003, pp. 10-13.
Stewart M. et al., “Polysilicon TFT technology for active matrix OLED displays” IEEE transactions on electron devices, vol. 48, No. 5; Dated May 2001 (7 pages).
Tatsuya Sasaoka et al., 24.4L; Late-News Paper: A 13.0-inch AM-Oled Display with Top Emitting Structure and Adaptive Current Mode Programmed Pixel Circuit (TAC), SID 01 Digest, (2001), pp. 384-387.
Vygranenko et al.: “Stability of indium-oxide thin-film transistors by reactive ion beam assisted deposition”; dated 2009.
Wang et al.: “Indium oxides by reactive ion beam assisted evaporation: From material study to device application”; dated Mar. 2009 (6 pages).
Written Opinion dated Jul. 30, 2009 for International Application No. PCT/CA2009/000501 (6 pages).
Yi He et al., “Current-Source a-Si:H Thin Film Transistor Circuit for Active-Matrix Organic Light-Emitting Displays”, IEEE Electron Device Letters, vol. 21, No. 12, Dec. 2000, pp. 590-592.
Zhiguo Meng et al; “24.3: Active-Matrix Organic Light-Emitting Diode Display implemented Using Metal-Induced Unilaterally Crystallized Polycrystalline Silicon Thin-Film Transistors”, SID 01Digest, (2001), pp. 380-383.
International Search Report for Application No. PCT/IB2014/059409, Canadian Intellectual Property Office, dated Jun. 12, 2014 (4 pages).
Written Opinion for Application No. PCT/IB2014/059409, Canadian Intellectual Property Office, dated Jun. 12, 2014 (5 pages).
Extended European Search Report for Application No. EP 14181848.4, dated Mar. 5, 2015, (9 pages).
Related Publications (1)
Number Date Country
20180158415 A1 Jun 2018 US
Provisional Applications (1)
Number Date Country
62430437 Dec 2016 US