Patent Application
20240265848
This application claims the benefit of priority of China Patent Application No. 202310126170.3 filed on Feb. 6, 2023. The contents of the above application are all incorporated by reference as if fully set forth herein in its entirety.
The present application relates to the field of display technology, and especially relates to a pixel compensation circuit, a method of compensating pixel, and a display panel.
Being different from a voltage driving mode of liquid crystal display panels, organic light-emitting diode (OLED), Micro light-emitting diodes (Micro LED) and Mini light-emitting diodes (Mini LED) are current-mode driving elements. A current during display period is determined by the driving transistor, the current Ipixel satisfies a formula Ipixel=K (VGS−Vth)2. Coefficient K is related to mobility and size of a thin film transistor (TFT). VGS is a voltage difference between a gate and a source of a driving transistor. Vth is a threshold voltage of the driving transistor. It can be seen from the formula that if threshold voltages of driving transistors are different, especially in a range of low gray scale (in a case that VGS is less), the currents of pixels may be different, which eventually leads to brightness difference.
In order to compensate difference of threshold voltages of the driving transistors, various compensation methods have been provided. At present, there are two mainstream compensation methods including an external compensation and an internal compensation. The external compensation has a large compensation range of the threshold voltage for the driving transistor. However, a driving system of the external compensation is complex and has a high cost. A driving system of the internal compensation is relatively simple and has a low cost. However, the internal compensation has a low compensation range of threshold voltage of the drive transistor, so stability of the drive transistor is required to be high.
A pixel circuit of the internal compensation (nTnC) is generally more complex than a pixel circuit (3T1C) of the external compensation. Therefore, more gate scan stage transmission signals are needed, and a plurality of sets of array substrate gate driving circuits on array (GOA) are needed. Thus, a width of a bezel of the product is increased, which is unfavorable to appearance of the product.
The present application provides a pixel compensation circuit, a method of compensating pixel and a display panel capable, which may compensate a driving transistor, adopt less scanning signal lines, and facilitate a narrow bezel of a display product compared with pixel compensation circuits in prior art.
In one aspect, the present application provides a pixel compensation circuit including a compensation transistor, a driving transistor, a reset transistor, a first switching transistor, a second switching transistor, a first capacitor, a second capacitor, and a light-emitting device.
A gate of the compensation transistor is electrically connected to a current stage scanning signal line, and a source of the compensation transistor is electrically connected to a first node, and a drain of the compensation transistor is electrically connected to a data line. The current stage scanning signal line is configured to provide a scanning signal, and the data line is configured to provide a data signal.
A gate of the driving transistor is electrically connected to the first node, a source of the driving transistor is electrically connected to a drain of the first switching transistor, and a drain of the driving transistor is electrically connected to a positive electrode of the light-emitting device. A negative electrode of the light-emitting device is electrically connected to a negative power supply.
A gate of the reset transistor is electrically connected to a compensation control line, a source of the reset transistor is electrically connected to the first node, and a drain of the reset transistor is electrically connected to a second voltage terminal.
A gate of the first switching transistor is electrically connected to a control signal line, a source of the first switching transistor is electrically connected to a positive power supply, and a drain of the first switching transistor is electrically connected to the source of the driving transistor.
A gate of the second switching transistor is electrically connected to a reset signal line, a source of the second switching transistor is electrically connected to a first voltage terminal, and a drain of the second switching transistor is electrically connected to a connection point between the drain of the driving transistor and the positive electrode of the light-emitting device; and a second node is formed at the connection point.
One terminal of the first capacitor is electrically connected to the positive power supply, and another terminal of the first capacitor is electrically connected to the second node.
One terminal of the second capacitor is electrically connected to the first node, and another terminal of the second capacitor is electrically connected to the second node.
In another aspect, the present application provides a method of compensating pixel, the method includes:
In another aspect, the present application further provides a display panel including the pixel compensation circuit or employing the method for compensating pixel.
The pixel compensation circuit provided by the present application includes the compensation transistor, the driving transistor, the reset transistor, the first switching transistor, the second switching transistor, the first capacitor, the second capacitor, and the light-emitting device. A threshold voltage of the driving transistor can be compensated by combining the control signal line, the compensation control line, the reset signal line, the current stage scanning signal line, and a method for timing control that is set. Compared with the pixel compensation circuit in prior art, the present application does not need to adopt a plurality of array substrate gate driving circuit to achieve compensation function. That is, the scanning signal lines adopted by the present application are less, so that it is convenient to achieve narrow bezel of display products.
In order to more clearly illustrate technical solutions in embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, other drawings can also be obtained based on these drawings without exerting creative efforts.
The technical solutions in the embodiments of the present application are clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the embodiments described are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative works should be deemed as falling within the claims of the present application.
In the description of the present application, it should be understood that terms “first” and “second” are used for descriptive purposes only and cannot be understood to indicate or imply relative importance or to imply the number of technical features indicated. Thus, features defined as “first” and “second” may explicitly or implicitly include one or more of the features. In the description of the present application, “a plurality of” means two or more, unless expressly specified otherwise.
In the present application, the term “exemplary” is used to mean “serving as an example, illustration or illustration”. Any embodiment described in the present application as “exemplary” is not necessarily construed as being more preferred or advantageous than other embodiments. The following description is given to enable any person skilled in the art to practice and use the present application. In following description, details are listed for purpose of explanation. It should be understood that one of ordinary skill in the art can recognize that the present application may be practiced without use of these specific details. In other examples, well-known structures and processes may not be elaborated in detail to avoid unnecessary details that obscure description of the present application. Therefore, the present application is not intended to be limited to embodiments shown, but is consistent with the widest scope consistent with principles and features disclosed herein.
Embodiments of the present application provides a pixel compensation circuit, a method of compensating pixel, and a display panel.
In one aspect, the present application provides a pixel compensation circuit including a compensation transistor, a driving transistor, a reset transistor, a first switching transistor, a second switching transistor, a first capacitor, a second capacitor, and a light-emitting device. A gate of the compensation transistor is electrically connected to a current stage scanning signal line, and a source of the compensation transistor is electrically connected to a first node, and a drain of the compensation transistor is electrically connected to a data line. The current stage scanning signal line is configured to provide a scanning signal, and the data line is configured to provide a data signal. A gate of the driving transistor is electrically connected to the first node, a source of the driving transistor is electrically connected to a drain of the first switching transistor, and a drain of the driving transistor is electrically connected to a positive electrode of the light-emitting device. A negative electrode of the light-emitting device is electrically connected to a negative power supply. A gate of the reset transistor is electrically connected to a compensation control line, a source of the reset transistor is electrically connected to the first node, and a drain of the reset transistor is electrically connected to a second voltage terminal. A gate of the first switching transistor is electrically connected to a control signal line, a source of the first switching transistor is electrically connected to a positive power supply, and a drain of the first switching transistor is electrically connected to the source of the driving transistor. A gate of the second switching transistor is electrically connected to a reset signal line, a source of the second switching transistor is electrically connected to a first voltage terminal, and a drain of the second switching transistor is electrically connected to a connection point between the drain of the driving transistor and the positive electrode of the light-emitting device; and a second node is formed at the connection point. One terminal of the first capacitor is electrically connected to the positive power supply, and another terminal of the first capacitor is electrically connected to the second node. One terminal of the second capacitor is electrically connected to the first node, and another terminal of the second capacitor is electrically connected to the second node.
In some embodiments, the current stage scanning signal line, the compensation control line, the reset signal line, and the control signal line are combined to successively provide a reset stage, a detection stage, a data writing stage, and a light emitting stage, respectively.
In some embodiments, during the reset stage, both the control signal line and the current stage scanning signal line are provided with a low level, and both the compensation control line and the reset signal line are provided with a high level.
In some embodiments, during the reset stage, both the reset transistor and the second switching transistor are in an on state, and both the compensation transistor and the first switching transistor are in an off state.
In some embodiments, during the detection stage, both the control signal line and the compensation control line are provided with a high level, and both the reset signal line and the current stage scanning signal line are provided with a low level.
In some embodiments, during the detection stage, the first switching transistor and the reset transistor are both in on state, and the second switching transistor and the compensation transistor are both in an off state.
In some embodiments, during the data writing stage, the control signal line, the reset signal line, and the compensation control line are provided with a low level, and current stage scanning signal lines are provided with a high level row by row.
In some embodiments, during the data writing stage, the compensation transistor is in an on state, and the reset transistor, the first switching transistor, and the second switching transistor are in an off state.
In some embodiments, during the light emitting stage, the control signal line is provided with a high level, and the compensation control line, the reset signal line, and the current stage scanning signal line are provided with a low level.
In some embodiments, during the light emitting stage, the first switching transistor is in an on state, and the reset transistor, the second switching transistor, and the compensation transistor are all in an off state.
In another aspect, the present application provides a method of compensating pixel, the method includes:
In another aspect, the present application further provides a display panel including the pixel compensation circuit or employing the method for compensating pixel.
The pixel compensation circuit, the method of compensating pixel, and the display panel are described in detail below.
As shown in
A gate of the compensation transistor T1 is electrically connected to a current stage scanning signal line SPAM (n). A source of the compensation transistor T1 is electrically connected to a first node G. A drain of the compensation transistor T1 is electrically connected to a data line Vdata. The current stage scanning signal line SPAM is configured to provide a scanning signal. The data line Vdata is configured to provide the data signal.
The current stage scanning signal line SPAM(n) represents a gate scan signal for a nth row pixel unit outputted by a gate side driving circuit. A previous stage scan signal SPAM(n−1) represents a gate scan signal for a (n−1)th row pixel unit outputted by the gate side driving circuit.
A gate of the driving transistor T2 is electrically connected to the first node G. A source of the driving transistor T2 is electrically connected to a drain of the first switching transistor T4. A drain of the driving transistor T2 is electrically connected to a positive electrode of the light-emitting device LED. A negative electrode of the light-emitting device LED is electrically connected to a negative power supply VSS.
A gate of the reset transistor T3 is electrically connected to a compensation control line Comp(n). A source of the reset transistor T3 is electrically connected to the first node G. A drain of the reset transistor T3 is electrically connected to a second voltage terminal V2.
A gate of the first switching transistor T4 is electrically connected to a control signal line EM. A source of the first switching transistor T4 is electrically connected to a positive power supply VDD. A drain of the first switching transistor T4 is electrically connected to the source of the driving transistor T2.
A gate of the second switching transistor T5 is electrically connected to a reset signal line Res. A source of the second switching transistor T5 is electrically connected to a first voltage terminal V1. A drain of the second switching transistor T5 is electrically connected to a connection point between the drain of the driving transistor T2 and the positive electrode of the light-emitting device LED. A second node S is formed at the connection point.
One terminal of the first capacitor Cs is electrically connected to the power source positive electrode VDD, and the other end of the first capacitor Cs is electrically connected to the second node S.
One terminal of the second capacitor Cst is electrically connected to the first node G, and another terminal of the second capacitor Cst is electrically connected to the second node S.
In this embodiment, the compensation transistor T1, the driving transistor T2, the reset transistor T3, the first switching transistor T4, and the second switching transistor T5 may all adopt an N-channel thin film transistor (TFT), such as an N-channel amorphous silicon transistor (a-Si), an N-channel low temperature poly-silicon transistor (N-LTPS), or an N-channel metal oxide semiconductor field-effect Transistor (MOSFET). The compensation transistor T1, the driving transistor T2, the reset transistor T3, the first switching transistor T4, and the second switching transistor T5 may also be a P-channel thin film transistor, such as a P-channel low temperature poly-silicon (P-LTPS), a P-channel metal oxide semiconductor field effect transistor, and the like, which is not specifically limited in this embodiment.
The driving transistor T2 serves as a driving transistor for driving the light-emitting device LED to emit light in the pixel compensation circuit. The pixel compensation circuit proposed in the present application can compensate the threshold voltage of the driving transistor (i.e., the driving transistor T2). In this embodiment, the current stage scanning signal line SPAM (n), the compensation control line Comp (n), the reset signal line Res, and the control signal line EM are all controlled by an external timing controller.
In the pixel compensation circuit of the present application, as shown in
Potential changes during the reset stage, the detection stage, the data writing stage, and the light emitting stage and how to compensate the threshold voltage of the driving transistor are analyzed in detail.
During the reset stage, the control signal line EM and the current stage scanning signal line SPAM(n) are provided with a low level, and the compensation control line Comp(n) and the reset signal line Res are provided with a high level.
During this stage, as shown in
During this stage, a potential of the first node G is reset to a second voltage V2 provided by the second voltage terminal V2, and a potential of the second node S is reset to a first voltage V1 provided by the first voltage terminal V1. Since both the first switching transistor T4 and the driving transistor T2 are in an off state, the light-emitting device LED does not emit light at this stage.
During the detection stage, the control signal line EM and the compensation control line Comp(n) are both provided with a high level, and the reset signal line Res and the current stage scanning signal line SPAM(n) are both provided with a low level.
During this stage, as shown in
During this stage, a power supply positive voltage VDD starts to discharge until a voltage between gate and source of the driving transistor T2 changes into the threshold voltage Vth of the driving transistor T2, and the driving transistor T2 is turned off. At this stage, the voltage of the second node S changes into a third voltage V3, and the third voltage V3=V2−Vth. That is, the third voltage of the second node S includes the threshold voltage Vth of the driving transistor T2. Since the driving transistor T2 is in an off state, the light-emitting device LED does not emit light.
During the data writing stage, the control signal line EM, the reset signal line Res, and the compensation control line Comp(n) are all provided with a low level, and the current stage scanning signal lines SPAM (n) are successively provided with a high level row by row.
At this stage, as shown in
At this stage, the first node G is written into a data signal Vdata. Since the voltage of the second node S changes into V3 during the detection stage, the data signal Vdata is coupled to the second node S through the first capacitor Cs. A voltage of the second node S changes into a fourth voltage V4. The fourth voltage V4=V3+(Data−V2)*[Cst/(Cst+C1)]=V2−Vth+(Data−V2)*[Cst/(Cst+C1)]. Therefore, a source-drain voltage of the driving transistor T2 T2_Vgs=(Data−V2)*[Cst/(Cst+C1)]+Vth. That is, at this stage, the voltage of the second node S includes the threshold voltage Vth of the driving transistor T2. Since the driving transistor T2 and the first switching transistor T4 are still in an off state, the light-emitting device LED does not emit light.
During the light emitting stage, the control signal line EM is provided with a high level, and the compensation control line Comp(n), the reset signal line Res, and the current stage scanning signal line SPAM (n) are provided with a low level.
At this stage, as shown in
At this stage, both the first switching transistor T4 and the driving transistor T2 are turned on. Since the source-drain voltage of the driving transistor T2 T2_Vgs=(Data−V2)*[Cst/(Cst+C1)]+Vth during the data writing stage. That is, the source-drain voltage of the driving transistor T2 includes the threshold voltage Vth of the driving transistor T2. A current flowing through the light-emitting device LED is independent of the threshold voltage Vth according to a current formula of the TFT saturation region. Compensation for the threshold voltage of the driving transistor is realized, and the light-emitting device LED emits light.
By the pixel compensation circuit, an offset A Vth of the threshold voltage Vth ranges from −mV to +nV, and a variation of the current can be maintained within 5%.
To sum up, the pixel compensation circuit provided by the present application can realize compensation of the threshold voltage of the driving transistor (i.e., the driving transistor T2 in the present application) by adopting a set of GOA structure and simple timing control. Thus, uniformity and accuracy of luminous brightness of the light-emitting device LED can be improved. Compared with the pixel compensation circuit in prior art, the scanning signal lines adopted by the present application are less, so that it is convenient to achieve narrow bezel of display products.
In another embodiment of the present application, a pixel compensation circuit is further provided. As shown in
In this embodiment, the pixel compensation circuit compensates the threshold voltage of the driving transistor T2 by adopting the reset stage, the detection stage, the data writing stage, and the light emitting stage as described above.
In another embodiment of the present application, a pixel compensation circuit is further provided, as shown in
In this embodiment, the pixel compensation circuit compensates the threshold voltage of the driving transistor T2 by adopting the reset stage, the detection stage, the data writing stage, and the light emitting stage as described above.
The pixel compensation circuit provided by this embodiment can reduce the number of signal lines, thereby saving layout space.
In another embodiment of the present application, a pixel compensation circuit is further provided. As shown in
The pixel compensation circuit provided by this embodiment also removes the first switching transistor T4 in the pixel compensation circuit shown in
In this embodiment, the pixel compensation circuit implements compensation of the threshold voltage of the driving transistor T2 by using a method of timing control as described in
The pixel compensation circuit provided by the embodiment can reduce complexity of the circuit, and reduce power consumption of the display panel.
In another embodiment of the present application, the present application further provides a method for compensating pixel, as shown in
Step 101, providing the pixel compensation circuit as shown in
The pixel compensation circuit includes the compensation transistor T1, the driving transistor T2, the reset transistor T3, the first switching transistor T4, the second switching transistor T5, the first capacitor Cs, the second capacitor Cst, and the light-emitting device LED.
Step 102, providing the control signal line EM and the current stage scanning signal line SPAM (n) with a low level, and providing the compensation control line Comp(n) and the reset signal line Res with a high level during a reset stage, so that the reset transistor T3 and the second switching transistor T5 are both in an on state, and the compensation transistor T1 and the first switching transistor T4 are both in an off state. A potential of the first node G is reset to a second voltage V2 provided by the second voltage terminal V2, and a potential of the second node S is reset to a first voltage V1 provided by the first voltage terminal V1.
Step 103, providing the control signal line EM and the compensation control line Comp(n) with a high level, and providing the reset signal line Res and the current stage scanning signal line SPAM (n) with a low level during a detection stage, so that the first switching transistor T4 and the reset transistor T3 are both in an on state, and the second switching transistor T5 and the compensation transistor T1 are both in an off state. The voltage of the second node S changes into a third voltage V3, and the third voltage V3=V2−Vth. V2 is the second voltage V2, and Vth is a threshold voltage of the driving transistor T2.
Step 104, providing the control signal line EM, the reset signal line Res, and the compensation control line Comp(n) with a low level, and providing current scanning signal lines SPAM(n) with a high level row by row during a data writing stage, so that the compensation transistor T1 is in an on state, and the reset transistor T3, the first switching transistor T4, and the second switching transistor T5 are all in an off state. The first node G is written into a data signal Vdata. The voltage of the second node S changes into a fourth voltage V4, the fourth voltage V4=V3+(Data−V2)*[Cst/(Cst+C1)]=V2−Vth+(Data−V2)*[Cst/(Cst+C1)]. Data is a data signal input by the data line Vdata.
Step 105, providing the control signal line EM with a high level, and providing the compensation control line Comp(n), the reset signal line Res, and the current stage scanning signal line SPAM(n) with a low level during a light emitting stage, so that the first switching transistor T4 and the driving transistor T2 are in an on state, and the reset transistor T3, the second switching transistor T5, and the compensation transistor T1 are in an off state. A source-drain voltage of the driving transistor T2 T2_Vgs=(Data−V2)*[Cst/(Cst+C1)]+Vth, and the light-emitting device LED emits light.
In another embodiment of the present application, the present application provides a display panel comprising a pixel compensation circuit as described above or employing the method of compensating pixel.
The pixel compensation circuit, the method of compensating pixel, and the display panel provided by the embodiment of the present application are described in detail above. The principle and the implementation mode of the present application are described by applying specific examples in this article. The description of the above embodiments is only used to help understand the method and core idea of the present application. Meanwhile, to those skilled in the art, according to idea of the present application, there may be changes in specific embodiments and application scope. In summary, contents of the specification should not be understood as limiting the present application.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202310126170.3 | Feb 2023 | CN | national |
