Claims
- 1. A pixel-depth converter for converting source-pixel data having a source-pixel depth to destination-pixel data having a destination-pixel depth which differs from the source-pixel depth by a pixel-depth-conversion scale factor, the source-pixel depth being equal to one of a plurality of pixel depth values including at least the values one, two, and four, the destination-pixel depth being equal to one of a plurality of pixel depth values including at least the values two, four, and eight, the pixel-depth converter comprising:
- (a) a packed-pixel-data depacker circuit having a packed-pixel-data parallel input port, a depacked-pixel-data parallel output port, and a depacker sequencer-control-signal input port, the: packed-pixel-data input port being data-transfer connectable to a source-pixel-data memory for receiving source-pixel data words from the memory, each source-pixel data word having a packed-pixel data format and being divisible into a plurality of depacked pixel-data word components corresponding to the pixel-depth-conversion scale factor, each depacked pixel-data word component including pixel data of the source-pixel depth for a plurality of pixels and being divisible into a plurality of depacked pixel-data-word-component subfields, a plurality of groups of terminals of the depacked-pixel-data parallel output port defining depacked-word-component output-field subports, each depacked-word-component output-field subport corresponding to a pixel-depth-conversion scale Factor, the terminals of each depacked-word-component output-field subport being divisible into a plurality of depacked-word-component-output-field-subport terminal subsets, the depacker circuit being adapted to receive a source-pixel data word at the packed-pixel-data parallel input port and, responsive to a depacker sequencer-control signal applied to the depacker sequencer-control-signal input port, transmit the data word depacked-pixel-data-word-component-by-depacked-pixel-data-word-component sequentially through the depacked-word-component output-field subport of the depacked-pixel-data output port corresponding to the pixel-depth-conversion scale factor specified by the depacker-sequencer control signal;
- (b) a pixel-data-conversion-table storage circuit having a conversion-data load input port, a load-data control- signal input port, a plurality of converted-data-read parallel output ports, and a plurality of conversion-table read-address input ports, each conversion-table read-address input port being associated with a converted-data-read parallel output port, the pixel-data-conversion-table storage circuit being adapted to receive pixel-data conversion data in the conversion-data load input port and to store the pixel-data-conversion data at data-load storage locations specified by a load-data control signal applied to the load-date control-signal input port, the pixel-data-conversion-table storage circuit being adapted so that converted-pixel data from a data-read location specified by a depacked-source-pixel-data-portion conversion-lookup address applied to a conversion-table read-address input port can be read from the associated converted-data-read parallel-output port, the plurality of converted-data-read parallel output ports and associated conversion-table read-address input ports being operable effectively independently of one another so that conversion-lookup addresses may be applied independently in parallel to the plurality of conversion-table read-address input ports of the pixel-data-conversion-table storage circuit and converted-pixel data from the data-read storage locations specified by the addresses can be read in parallel from the associated converted-data-read parallel output port; and
- (c) a plurality of conversion-table address-selector multiplexers, each conversion-table address-selector multiplexer having a plurality of conversion-table address-selector-multiplexer depacked-source-pixel-data-portion input ports, a conversion-lookup address output port and an address-selector-multiplexer control-signal input port, corresponding depacked-source-pixel-data-portion input ports of the conversion-table address-selector multiplexers being associated with a pixel-depth-conversion scale factor, each of the depacked-source-pixel-data-portion input ports being connected to a corresponding depacked-word-component-output-field-subport terminal subset of the depacked-word-component output-field subport which corresponds to the associated pixel-depth-conversion scale factor, the conversion-lookup address output port of each of the conversion-table address selector-multiplexers being connected to an associated conversion-table read-address input port of the pixel-data-conversion-table storage circuit, and the address-selector-multiplexer control-signal input ports being connectable to a scale-factor-selection signal bus for receiving a scale-factor-selection signal which specifies the desired pixel-depth-conversion scale factor and corresponding depacked-word-component-output-field-subport terminal subsets to supply depacked-source-pixel-data-portion conversion-lookup addresses for the desired pixel data conversion.
- 2. The pixel-depth converter according to claim 1 in which the packed-pixel-data depacker circuit comprises:
- (a.1) a data-shift multiplexer including a no-shift-primer shift-multiplexer data input port, a first-shift-increment shift-multiplexer data input port, a second-shift-increment shift-multiplexer input port, a shift-multiplexer data output port, and a shift-increment control-signal input port, each shift-multiplexer data input port having a plurality of shift-multiplexer input terminals, the shift-multiplexer output port having a plurality of shift-mutiplexer output terminals, the data-shift multiplexer being adapted to cause a selected shift-multiplexer data input port to be connected to the shift-multiplexer data output port in response to a shift-increment control signal applied to the shift-increment control-signal input port; and
- (a.2) a data-return register having a plurality of return-register cells, each return-register cell being of a Type-D type and having a return- register input terminal, a return- register output terminal, and a return-register-cell clock input terminal, the data-return register having a return-register clock input port connected to the return-register-cell clock input terminals so that application of a return-register clock signal to the return-register clock input port causes data present at the input terminals of the return-register cells to be loaded into the cells, each return-register input terminal being connected to a corresponding shift-multiplexer output terminal, the no-shift-primer shift-multiplexer data input port constituting the packed-pixel-data parallel input port of the packed-pixel-data depacker circuit, shift-multiplexer data input terminals of the first-shift-increment data input port being connected to return-register output terminals of the data-return register in a first-shift-increment shifted-position fashion so that in operation when the first-shift-increment shift-multilplexer data input port is connected to the shift-multiplexer data output port, at least a portion of a data word appearing at the return-register output terminals of the data-return register appears at the shift-multiplexer data output port shifted by a first shift increment, shift-multiplexer input terminals of the second-shift-increment data input port being connected to return-register output terminals of the data-return register in a second-shift-increment shifted-position fashion so that in operation when the second-shift-increment shift-multiplexer data input port is connected to the shift-multiplexer data output port, at least a portion of a data word appearing at the return-register output terminals of the data-return register appears at the shift-multiplexer data output port shifted by a second shift increment, the first shift increment differing from the second shift increment, at least a depacked-pixel-data portion of the shift-multiplexer output terminals of the shift-multiplexer data output port being connected to the depacked-pixel-data parallel output port of the packed-pixel-data depacked circuit.
- 3. The pixel-depth converter according to claim 2 in which the first shift increment is four and the second shift increment is eight.
- 4. The pixel-depth converter according to claim 3 in which shift-multiplexer input terminals of the first-shift-increment data input port are connected to return-register output terminals in a shift-right fashion so that in operation when the first-shift-increment shift-multiplexer data input port is connected to the shift-multiplexer data output port, at least a portion of a data word appearing at the return-register output terminals appears at the shift-multiplexer data output port shifted to the right, and in which shift-multiplexer input terminals of the second-shift-increment data input port are connected to return-register output terminals of the data-return register in a shift-right fashion so that in operation when the second-shift-increment shift-multiplexer data input port is connected to the shift-multiplexer data output port, at least a portion of a data word appearing at the return-register output terminals appears at the shift-multiplexer data output port shifted to the right.
- 5. The pixel-depth converter according to claim 1 in which the pixel-data-conversion-table storage circuit includes:
- (b.1) a plurality of conversion-table registers, each conversion-table register having a plurality of register input terminals and a like plurality of register output terminals, corresponding ones of the register input terminals on the various conversion-table registers being connected in parallel to form the conversion-data load input port of the pixel-data-table storage circuit, each conversion table register having a conversion-table load-register control-signal input terminal, the conversion-table load-register control-signal input terminals of the conversion table registers collectively constituting the load-data control-signal input port of the pixel-data-conversion-table storage circuit, and the register output terminals of the conversion-table registers being grouped to define a plurality of conversion-table-entry effective-register output-terminal groupings; and
- (b.2) a plurality of conversion-table readout multiplexers, each conversion-table readout multiplexer having a plurality of conversion-table-multiplexer data input ports, a conversion-table-multiplexer data output port, and a conversion-table readout-multiplexer effective-register-select control input port, the conversion-table readout-multiplexer effective-register-select control input port of each conversion-table readout multiplexer constituting a conversion-table read-address input port of the pixel-data-conversion-table-storage circuit, the conversion-table multiplexer data output port of each conversion-table readout multiplexer constituting a converted-data-read parallel output port of the pixel-data-conversion-table storage circuit, corresponding ones of the conversion-table-multiplexer data input ports of the conversion-table-readout multiplexers being connected in parallel to an associated conversion-table-entry effective-register output-terminal grouping of register output terminals so that conversion-table-readout multiplexers can effectively independently read the pixel-data-conversion data appearing on the effective-register output-terminal groupings of register output terminals of the conversion table registers.
- 6. The pixel-depth converter according to claim 5 in which the pixel-data-conversion-table storage circuit includes four 32-bit conversion-table registers and four conversion-table readout multiplexers, each conversion-table readout multiplexer being eight-bits wide and having sixteen conversion-table-multiplexer data input ports, the 128 register output terminals of the four conversion-table registers being grouped to define sixteen conversion-table-entry effective-register output-terminal groupings of eight register output terminals each.
- 7. The pixel-depth converter according to claim 1 in which the pixel-data-conversion-table storage circuit includes a plurality of conversion-table random-access-memory circuits, each conversion-table random-access-memory circuit having a conversion-table RAM load-data input port, a conversion-table RAM read-data output port and a conversion-table RAM address/control input port, the conversion-table RAM load-data input ports of the conversion-table random-access-memory circuits being connected in parallel to constitute the conversion-data load input port of the pixel-data-conversion-table storage circuit, the conversion-table RAM address/control input port of each conversion-table random-access-memory circuit including load-data address/control input terminals, the load-data address/control input terminals of the conversion-table random-access-memory circuits being connected in parallel to constitute the load-data control-signal input port of the pixel-data-conversion-table storage circuit, each conversion-table RAM read-data output port constituting a converted-data-read parallel output port of the pixel-data-conversion-table storage circuit, and the conversion-table RAM address/control input port of each conversion-table random-access-memory circuit including read-data address/control input terminals which constitute a conversion-table read-address input port of the pixel-data-conversion-table storage circuit, so that the plurality of conversion-table random-access-memory circuits can be loaded in parallel with identical pixel-data-conversion data essentially simultaneously and can be read individually effectively independently of one another essentially simultaneously.
- 8. A pixel-depth converter for converting source-pixel data having a source-pixel depth to destination-pixel data having a destination-pixel depth which differs from the source-pixel depth by a pixel-depth-conversion scale factor, the source-pixel depth being equal to one of a plurality of pixel depth values including at least the values two, four and eight, the destination-pixel depth being equal to one of a plurality of pixel depth values including at least the values one, two and four, the pixel-depth converter comprising:
- (a) a plurality of odd/even line-selector multiplexers connected in a cascaded fashion, each odd/even line-selector multiplexer being a two-to-one multiplexer having an odd/parity input port, an even-parity input port, a selected-parity output port and a parity-select control-signal input port, a first-stage odd/even line-selector multiplexer being connectable to a source-pixel-data memory by way of a source-pixel data bus for receiving source-pixel data words from the memory, input terminals of the odd-parity input port of the first-stage odd/even line-selector multiplexer being connected respectively to alternate lines of the source-pixel data bus having odd-parity bit-position indexes, input terminal s of the even-parity input port of the first-stage odd/even line-selector multiplexer being connected respectively to alternate lines of the source-pixel data bus having even-parity bit-position indexes, input terminals of the odd-parity input port of each succeeding odd/even line- selector multiplexer after the first- stage odd/even line- selector multiplexer being connected respectively to alternate output terminals of the selected-parity output port of the immediately-preceding odd/even line-selector multiplexer having odd-parity bit-position indexes, input terminals of the even-parity input port of each succeeding odd/even line selector multiplexer after the first-stage odd/even line-selector multiplexer being connected respectively to alternate output terminals of the selected-parity output port of the immediately preceding odd/even line-selector multiplexer having even-parity bit-position indexes, the parity-select control-signal input ports of the odd/even line-selector multiplexers constituting a plane-select control-word signal input port of the pixel-depth converter; and
- (b) a plurality of stage-select multiplexers, each stage-select multiplexer having a plurality of stage-select-multiplexer data input ports, a stage-select-multiplexer data output port, and a stage-select control-signal input port, input terminals of the stage-select-multiplexer data input ports of the stage-select multiplexers being connected respectively to output terminals of selected-parity output ports of the odd/even line-selector multiplexers so that, in operation, data at the output terminals of a selected-parity output of one of the odd/even line-selector multiplexers specified by a stage-select control signal applied to the stage-select control-signal input ports of the stage-select multiplexers appears at a corresponding number of output terminal s of one or more stage- select multiplexer output ports of the stage-select multiplexers.
- 9. A pixel-depth converter according to claim 8 further comprising:
- (c) an extracted-data-consolidator circuit, the extracted-data-consolidator circuit including:
- (c.1) a multi stage data-consolidator first-in-first-out device having a parallel-load FIFO data input port, a clear-selected-stages control-signal input port, a source-bits-per-pixel control-signal input port, and a plurality of FIFO read-data output ports, each FIFO read-data output port being connected to a corresponding one of the FIFO stages for reading at least a portion of data in the FIFO stage; and
- (c.2) a data-consolidator multiplexer having a plurality of data-consolidation input ports, a consolidated-data output port and a data-consolidation-group-select control-signal input port, each of the data-consolidation input ports being connected to consolidation output terminals of a data-consolidation grouping of one or more FIFO read-data output ports, so that in operation at least data-word portions of one or more successive data words loaded in the data-consolidator FIFO device specified by a source-bits-per-pixel control signal applied to the data-consolidation group-select control-signal input port of the data-consolidator multiplexer appear in a consolidated format at the consolidated data output of the data-consolidator multiplexer of the extracted data consolidator.
- 10. A pixel-depth converter for converting source-pixel data having a source-pixel depth to destination pixel data having a destination-pixel depth which differs from the source-pixel depth by a pixel-depth-conversion scale factor, the source-pixel depth being equal to one of a plurality of pixel depth values including at least the values one, two, four and eight the destination-pixel depth being equal to one of a plurality of pixel depth values including at least the values one, two, four, and eight, the pixel-depth converter comprising:
- (a) a pixel-depth expansion circuit comprising:
- (a.1) a packed-pixel-data depacker circuit having a packed-pixel-data parallel input port, a depacked-pixel-data parallel output port, and a depacker sequencer-control-signal input port, the packed-pixel-data input port being data-transfer connectable to a source-pixel-data memory for receiving source-pixel data words from the memory, each source-pixel data word having a packed-pixel data format and being divisible into a plurality of depacked pixel-data word components corresponding to the pixel.-depth-conversion scale factor, each depacked pixel-data word component including pixel data of the source-pixel depth for a plurality of pixels and being divisible into a plurality of depacked pixel-data-word-component subfields, a plurality of groups of terminals of the depacked-pixel-data parallel output port defining depacked-word-component output-field subports, each depacked-word-component output-field subport corresponding to a pixel-depth-conversion scale factor, the terminals of each depacked-word-component output-field subport being divisible into a plurality of depacked-word-component-output-field-subport terminal subsets, the depacker circuit being adapted to receive a source-pixel data word at the packed-pixel-data parallel input port and responsive to a depacker sequencer-control signal applied to the depacker sequencer-control-signal input port, transmit the data word depacked-pixel-data-word-component-by-depacked-pixel-data-word-component sequentially through the depacked-word-component output-field subport of the depacked-pixel-data output port corresponding to the pixel-depth-conversion scale factor specified by the depacker-sequencer control signal;
- (a.2) a pixel-data-conversion-table storage circuit having a conversion-data load input port, a load-data control-signal input port, a plurality of converted-data-read parallel output ports, and a plurality of conversion-table read-address input ports, each conversion-table read-address input port being associated with a converted-data-read parallel output port, the pixel-data-conversion-table storage circuit being adapted to receive pixel-data conversion data in the conversion-data load input port and to store the pixel-data-conversion data at data-load storage locations specified by a load-data control signal applied to the load-data control-signal input port, the pixel-data-conversion-table storage circuit being adapted so that converted-pixel data from a data-read location specified by a depacked-source-pixel-data-portion conversion-lookup address applied to a conversion-table read-address input port can be read from the associated converted-data-read parallel output port, the plurality of converted-data-read parallel output ports and associated conversion-table read-address input ports being operable effectively independently of one another so that conversion-lookup addresses may be applied independently in parallel to the plurality of conversion-table read-address input ports of the pixel-data-conversion-table storage circuit and converted-pixel data from the data-read storage locations specified by the addresses can be read in parallel from the associated converted-data-read parallel output port; and
- (a.3) a plurality of conversion-table address-selector multiplexers, each conversion-table address-selector multiplexer having a plurality of conversion-table address-selector-multiplexer depacked-source-pixel-data-portion input ports, a conversion-lookup address output port and art address-selector-multiplexer control-signal input port, corresponding depacked-source-pixel-data-portion input ports of the conversion-table address-selector multiplexers being associated with a pixel-depth-conversion scale factor, each of the depacked- source-pixel-data-portion input ports being connected to a corresponding depacked-word-component-output-field-subport terminal subset of the depacked-word-component output-field subport which corresponds to the associated pixel-depth-conversion scale factor, the conversion-lookup address output port of each of the conversion-table address selector-multiplexers being connected to an associated conversion-table read-address input port of the pixel-data-conversion-table storage circuit, and the address-selector-multiplexer control-signal input ports being connectable to a scale-factor-selection signal bus for receiving a scale-factor-selection signal which specifies the desired pixel-depth-conversion scale factor and corresponding depacked-word-component-output-field-subport terminal subsets to supply depacked-source-pixel-data-portion conversion-lookup addresses for a desired pixel data conversion; and
- (b) a plane-extractor circuit comprising:
- (b.1) a plurality of odd/even line-selector multiplexers connected in a cascaded fashion, each odd/even line-selector multiplexer being a two-to-one multiplexer having an odd/parity input port, an even-parity input port, a selected-parity output port and a parity-select control-signal input port, a first-stage odd/even line- selector multiplexer being connectable to a source-pixel-data memory by way of a source-pixel data bus for receiving source-pixel data words from the memory, input terminals of the odd-parity input port of the first-stage odd/even line-selector multiplexer being connected respectively to alternate lines of the source-pixel data bus having odd-parity bit-position indexes, input terminals of the even-parity input port of the first-stage odd/even line-selector multiplexer being connected respectively to alternate lines of the source-pixel data bus having even-parity bit-position indexes, input terminals of the odd-parity input port of each succeeding odd/even line-selector multiplexer after the first-stage odd/even line-selector multiplexer being connected respectively to alternate output terminals of the selected-parity output port of the immediately-preceding odd/even line-selector multiplexer having odd-parity bit-position indexes, input terminals of the even-parity input port of each succeeding odd/even line selector multiplexer after the first-stage odd/even line,-selector multiplexer being connected respectively to alternate output terminals of the selected-parity output port of the immediately preceding odd/even line- selector multiplexer having even-parity bit-position indexes, the parity-select control- signal input ports of the odd/even line-selector multiplexers constituting a plane-select control-word signal input port of the pixel-depth converter; and
- (b.2) a plurality of stage-select multiplexers, each stage-select multiplexer having a plurality of stage-select-multiplexer data input ports, a stage-select-multiplexer data output port, and a stage-select control-signal input port, input terminals of the stage-select-multiplexer data input ports of the stage-select multiplexers being connected respectively to output terminals of selected-parity output ports of the odd/even line-selector multiplexers, so that, in operation, data at the output terminals of a selected-parity output of one of the odd/even line- selector multiplexers specified by a stage-select control signal applied to the stage-select control-signal input ports of the stage-select multiplexers appears at a corresponding number of output terminals of one or more stage-select multiplexer output ports of the stage-select multiplexers.
- 11. The pixel-depth converter of claim 10 in which the pixel-depth expansion circuit and the plane-extractor circuit are connected in parallel.
Parent Case Info
This application is a continuation of application Ser. No. 07/971,702, filed 4 Nov., 1992, now abandoned, which in turn was a continuation of application Ser. No. 07/879,523, filed 4 May 1992, now abandoned, which in turn was a continuation of application Ser. No. 07/798,033, filed 20 Nov. 1991, now abandoned, which in turn was a continuation of application Ser. No. 07/524,201, filed 16 May 1990, now abandoned.
US Referenced Citations (15)
Non-Patent Literature Citations (1)
Entry |
Texas Instruments "TMS34010 User's Guide", pp. 5-5 through 5-6, 7-1 through 7-10, 12-161 through 12-163 (1986). |
Continuations (4)
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971702 |
Nov 1992 |
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879523 |
May 1992 |
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798033 |
Nov 1991 |
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524201 |
May 1990 |
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