Patent Grant
12112692
The present application claims priority of China Patent Application No. 202211401508.3 filed on Nov. 9, 2022, the entire contents of which are hereby incorporated by reference.
The present disclosure relates to the field of display panels, and in particular to a pixel drive circuit, a driving method, and a display panel.
Currently, inorganic micro light emitting diode (Micro LED) displays are one of the hot spots in display research.
Compared with OLED displays, Micro LEDs have the advantages of high reliability, low power consumption, high brightness, and fast response time, etc. Among them, the drive circuit for controlling the LED light emission is the core technology of Micro LED display and has important research significance.
However, since the luminous efficiency of LEDs varies greatly under different driving currents, in order to reduce the power consumption of Micro LED displays, it is necessary to maintain the LEDs working at relatively high currents for keeping the LEDs always in a high-efficiency operating range.
The main technical problem solved by the present disclosure is to provide a pixel drive circuit and its driving method, and a display panel to realize the light-emitting element to maintain in a high-efficiency working range.
To solve the above technical problem, the present disclosure provides a pixel drive circuit, including: a light-emitting element; a power supply line, including a high-potential power supply and a low-potential power supply, connected to the light-emitting element; a pulse amplitude modulation unit, including a first drive transistor connected to the light-emitting element and the power supply line; wherein a driving current with different amplitudes is provided to the light-emitting element according to a voltage applied to a gate of the first drive transistor; and a pulse width modulation unit, including a second drive transistor connected to the light-emitting element and the pulse amplitude modulation unit; wherein a duration of the driving current of the light-emitting element is controlled according to a voltage applied to a gate of the second drive transistor.
In some embodiments, a source of the first drive transistor is connected to the power supply line, a drain of the first drive transistor is connected to a source of the second drive transistor, and a drain of the second drive transistor is connected to the light-emitting element.
In some embodiments, the pixel drive circuit further includes a driving current detection unit connected to the drain of the first drive transistor and configured to detect a driving current of the first drive transistor; wherein the driving current detection unit includes a first switch transistor; a source of the first switch transistor is connected to the drain of the first drive transistor, a drain of the first switch transistor is connected to a measurement line, and a gate of the first switch transistor is connected to a scan control line.
In some embodiments, the pulse width modulation unit further includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, and a second capacitor; a first pole plate of the first capacitor is connected to the gate of the second drive transistor, and a second pole plate of the first capacitor is connected to the power supply line; a source of the first transistor is connected to a first signal line, a drain of the first transistor is connected to the gate of the second drive transistor, and a gate of the first transistor is connected to a first scan control line; a source of the second transistor is connected to a second signal line, a drain of the second transistor is connected to the gate of the second drive transistor, and a gate of the second transistor is connected to a drain of the third transistor and to a first pole plate of the second capacitor; a source of the third transistor is connected to a third signal line, the drain of the third transistor is connected to the gate of the second transistor and to the first pole plate of the second capacitor, and a gate of the third transistor is connected to a second scan control line; a source of the fourth transistor is connected to a control signal line, a drain of the fourth transistor is connected to a second pole plate of the second capacitor, and a gate of the fourth transistor is connected to a third scan control line.
In some embodiments, the pulse width modulation unit further includes a fifth transistor connected in parallel with the first transistor to control a gate voltage of the second drive transistor; wherein a source of the fifth transistor is connected to the first signal line, a drain of the fifth transistor is connected to the gate of the second drive transistor, and a gate of the fifth transistor is connected to the second scan control line, for maintaining an initial voltage of the gate of the second drive transistor.
In some embodiments, the pixel drive circuit further includes a control unit connected to the light-emitting element and the power supply line, for controlling connection or disconnection of the light-emitting element; wherein the control unit includes a second switch transistor; a source of the second switch transistor is connected to the drain of the second drive transistor, a drain of the second switch transistor is connected to the light-emitting element, and a gate of the second switch transistor is connected to a fourth scan control line.
In some embodiments, the pulse amplitude modulation unit further includes a sixth transistor and a third capacitor; a source of the sixth transistor is connected to a data line, a drain of the sixth transistor is connected to a gate of the first drive transistor and to a first pole plate of the third capacitor, and a gate of the sixth transistor is connected to the first scan control line; a second pole plate of the second capacitor is connected to the power supply line.
In some embodiments, each of the first drive transistor, second drive transistor, first transistor, second transistor, third transistor, fourth transistor, fifth transistor, sixth transistor, first switch transistor, and second switch transistor is an N-type transistor or a P-type transistor.
The present disclosure provides a driving method of the pixel drive circuit; wherein the driving method includes: a first stage, where the first scan control line of an Nth row controls the sixth transistor and the first transistor to be turned on, a data voltage of the data line is transmitted through the sixth transistor to the first pole plate of the third capacitor and the gate of the first drive transistor, and the data voltage is maintained through the third capacitor to achieve an amplitude setting of a driving current of the first drive transistor; a first voltage of the first signal line is transmitted through the first transistor to the gate of the second drive transistor and to the first pole plate of the first capacitor, and the first voltage is maintained through the first capacitor to keep the second drive transistor in a turned-off state; a second stage, where the second scan control line of an Nth row controls the third transistor to be turned on, and a third voltage of the third signal line is transmitted through the third transistor to the gate of the second transistor and the first pole plate of the second capacitor, to keep the second transistor turned off; the third scan control line controls the fourth transistor to be turned on, and a first level voltage of the control signal line is written to the second pole plate of the second capacitor through the fourth transistor and transmitted to the gate of the second transistor through a coupling effect of the second capacitor; a third stage, where the third scan control line of an Nth row controls the fourth transistor to be turned on, and a second level voltage of the control signal line is written to the second pole plate of the second capacitor through the fourth transistor and transmitted to the gate of the second transistor through the coupling effect of the second capacitor, to turn off the second transistor; and a fourth stage, the third scan control lines of all rows control the fourth transistor to be turned on, and a swing voltage of the control signal line is transmitted through the fourth transistor to the gate of the second transistor to control the second transistor to be turned on; a second voltage of the second signal line is transmitted through the second transistor to the gate of the second drive transistor to control the second drive transistor to be turned on; wherein a turned-on time of the second transistor is controlled through the swing voltage, and a turned-on time of the second drive transistor is controlled, thereby controlling a light-emitting time of the light emitting element.
In some embodiments, the second transistor is a P-type transistor, and the swing voltage is a uniformly falling voltage; the light-emitting time is related to a decreasing slope of the swing voltage.
In some embodiments, the second transistor is an N-type transistor, and the swing voltage is a uniformly rising voltage.
In some embodiments, in the second or third stage, the scan control line of the Nth row further controls the first switching transistor to be turned on, causing the drain of the first drive transistor to form a path with a measurement line, for measuring the driving current of the first drive transistor.
In some embodiments, the scan control line is the second scan control line or the third scan control line.
In some embodiments, in the second stage, the second scan control line of the Nth row further controls the fifth transistor to be turned on, and the first voltage of the first signal line is transmitted to the first pole plate of the first capacitor and to the gate of the second drive transistor, keeping a gate voltage of the second drive transistor constant.
In some embodiments, in the fourth stage, the fourth scan control line controls the second switch transistor to be turned on, enabling the power supply line to form a path with the light-emitting element and causing the light-emitting element to emit light.
The present disclosure further provides a display panel, including a plurality of pixel cells arranged in an array; wherein each pixel cell is arranged with the pixel drive circuit as above.
The beneficial effect of the present disclosure is that the gate voltage of the first drive transistor of the pulse amplitude modulation unit is controlled by the transistor and control line to modulate the driving current of the light-emitting element, and the gate voltage of the second drive transistor of the pulse amplitude modulation unit is controlled to modulate the light-emitting time of the light-emitting element. The present disclosure realizes PWM modulation and PAM modulation by controlling the gate voltages of the two TFTs separately, such that the light-emitting element can always be in a high-efficiency operating range and the cutting of gray scale can be easily realized.
In order to illustrate the technical solutions more clearly in the embodiments of the present disclosure, the following will briefly describe the accompanying drawings required in the description of the embodiments, and it is obvious that the following description of the accompanying drawings are only some of the embodiments of the present disclosure. For those skilled in the art, other accompanying drawings may be obtained from these drawings without creative labor.
The following will be a clear and complete description of the technical solutions in the embodiments of the present disclosure, in conjunction with the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, and not all of them. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without making creative labor fall within the scope of the present disclosure.
The terms used in the embodiments of the present disclosure are intended solely for the purpose of describing particular embodiments and are not intended to limit the present disclosure. The singular forms of “one”, “said”, and “the” as used in the embodiments of the present disclosure and the appended claims are also intended to include plural forms, unless clearly indicated above. Unless other meanings are clearly indicated above, “a plurality” generally includes at least two, but does not exclude the inclusion of at least one.
It should be understood that the term “and/or” as used herein is simply a description of the association of related objects, indicating that three relationships can exist, e.g., A and/or B, which can mean: A alone, both A and B, and B alone. In addition, the character “/” in this document generally indicates that the associated objects before and after are in an “or” relationship. The terms “first”, “second”, etc. in the specification, claims, and the above-mentioned drawings of the present disclosure are used to distinguish similar objects, and need not be used to describe a specific order or sequence.
It is to be understood that the term “including”, “comprising”, or any other variation thereof, as used herein, is intended to cover non-exclusive inclusion such that a process, method, article, or apparatus including a series of elements includes not only those elements, but may further include other elements not expressly listed, and may further include elements that are inherent to such process, method, article, or apparatus. Without further limitation, the elements defined by the statement “including” do not preclude the existence of additional identical elements in the process, method, article, or apparatus that include said elements.
It should be noted that when there are directional indications (such as up, down, left, right, forward, backward) in the present disclosure, the directional indications are intended only to explain the relative positions, movements, etc. of components in a particular posture (as shown in the accompanying drawings), and if that particular posture is changed, the directional indications are also changed accordingly.
References herein to “embodiments” mean that particular features, structures, or characteristics described in connection with the embodiments may be included in at least one embodiment of the present disclosure. The presence of the phrase at each location in the specification does not necessarily mean the same embodiment, nor is it a separate or alternative embodiment that is mutually exclusive with other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.
The present disclosure provides a pixel drive circuit. Referring to
The power supply line includes a high-potential power supply line VDD and a low-potential power supply line VSS. The power flows through the high-potential power supply line VDD, through the light-emitting element, and then to the low-potential power supply line VSS. The low-potential power supply line VSS may be grounded and is not limited herein. In the embodiments, the power supply line refers to the high-potential power supply line VDD.
In the embodiments, the power supply line and the light-emitting element are connected by the pulse amplitude modulation unit and the pulse width modulation unit. The driving current of the light-emitting element is adjusted by the pulse amplitude modulation unit, and the light-emitting time of the light-emitting element is adjusted by the pulse width modulation unit.
Specifically, the pulse amplitude modulation unit includes a first drive transistor; a source of the first drive transistor is connected to the high-potential power supply line, a drain of the first drive transistor is connected to the light-emitting element, and the driving current is provided to the light-emitting element with different amplitudes according to the voltage applied to a gate of the first drive transistor. That is, the magnitude of the current flowing through the source/drain of the first drive transistor is controlled by controlling the gate voltage of the first drive transistor. Among them, the driving current I=½ μCW/L (VGS−Vth)2, where VGS is the gate source voltage of the first drive transistor and Vth is a threshold voltage for turning on the first drive transistor. The driving current is also the driving current flowing through the light-emitting element, and the driving current is related to the luminous brightness of the light-emitting element.
The pulse width modulation unit includes a second drive transistor; a source of the second drive transistor is connected to the drain of the first drive transistor, and a drain of the second drive transistor is connected to the light-emitting element to connect the pulse amplitude modulation unit and the light-emitting element. The pulse width modulation unit controls the turned-on time of the second drive transistor based on adjusting the voltage applied to the gate of the second drive transistor, thereby controlling the duration of the driving current flowing through the light-emitting element, that is, controlling the light-emitting duration of the light-emitting element. In the embodiments, the pulse width modulation unit and the pulse amplitude modulation unit are connected in series.
In other embodiments, the pulse amplitude modulation unit and pulse width modulation unit may be swapped in order, without limitation here.
The beneficial effect of the present embodiments is that the driving current and light-emitting time of the light-emitting element are controlled by the first drive transistor and the second drive transistor, respectively, such that the driving current and light-emitting time of the light-emitting element can be controlled by controlling the gate voltage of the first transistor and the second transistor, respectively, which is convenient to control and adjust.
The present disclosure further provides a specific circuit structure of the first pixel drive circuit. Specifically, referring to
A first pole plate of the first capacitor C2 is connected to the gate of the second drive transistor T4, and a second pole plate of the first capacitor C2 is connected to the high-potential power supply line VDD.
A source of the first transistor T8 is connected to a first signal line gh1, a drain of the first transistor T8 is connected to the gate of the second drive transistor T4 and to the first pole plate of the first capacitor C2, and a gate of the first transistor T8 is connected to a first scan control line scant. The first transistor T8 can charge a first voltage gh1 to the gate of the second drive transistor T4 and the first voltage gh1 is maintained through the first pole plate of the first capacitor C2. The first voltage gh1 is configured to turn off the second drive transistor T4.
A source of the second transistor T7 is connected to a second signal line g1, a drain of the second transistor T7 is connected to the gate of the second drive transistor T4, and a gate of the second transistor T7 is connected to a drain of the third transistor T6 and to a first pole plate of the second capacitor C3.
A source of the third transistor T6 is connected to a third signal line gh2, the drain of the third transistor T6 is connected to the gate of the second transistor T7, and a gate of the third transistor T6 is connected to a second scan control line scant and to the first pole plate of the second capacitor C3.
A source of the fourth transistor T5 is connected to a control signal line a, a drain of the fourth transistor T5 is connected to a second pole plate of the second capacitor C3, and a gate of the fourth transistor T5 is connected to a third scan control line scan3. The voltage of the gate of the second transistor T7 is adjusted by the third transistor T6 and the fourth transistor T5 cooperatively.
In the embodiments, an initial voltage is charged to the gate of the second drive transistor T4 through the first transistor T8 to ensure that the second drive transistor T4 is turned off, and the gate voltage of the second transistor T7 is controlled to control turning on the second transistor T7, such that the gate of the second drive transistor T4 is charged with a turning-on voltage through the second transistor T7 to enable the second drive transistor T4 to turn on, and the turned-on time of the second drive transistor T4 is controlled to control the light-emitting time of the light-emitting element LED.
In a specific embodiment, to prevent the gate voltage of the second drive transistor T4 from changing caused by the second transistor T7 being accidentally turned on when the voltage at the gate of the second transistor T7 is modulated, a fifth transistor T9 is connected in series with the gate of the second drive transistor T4. The fifth transistor T9 is connected in parallel with the first transistor T8 to control the gate voltage of the second drive transistor during the charging process.
In other embodiments, since a change in the voltage of the third transistor T6 and the fourth transistor T5 does not necessarily cause the second transistor T7 to be turned on, the fifth transistor T9 may be omitted.
In the embodiments, further, in order to prevent the light-emitting element LED emitting light caused by the second drive transistor T4 being turned on in the charging process, a control unit is arranged between the light-emitting element and the power supply line for controlling connection or disconnection between the light-emitting element and the power supply line. The control unit may be connected at any position between the power supply line and the light-emitting element. In the embodiments, the control unit is connected between the pulse width modulation unit and the light-emitting element LED. In other embodiments, the control unit may be connected between the pulse amplitude modulation unit and the pulse width modulation unit, without limitation herein.
In the embodiments, the control unit includes a second switch transistor T10; a source of the second switch transistor T10 is connected to the drain of the second drive transistor T4, a drain of the second switch transistor T10 is connected to the light-emitting element LED, and a gate of the second switch transistor T10 is connected to a fourth scan control line EM. In the embodiments, since the path of the light-emitting element is controlled by the second switch transistor T10, the light-emitting element will not be caused to emit light even if the second drive transistor T4 is turned on during a non-light-emitting stage. In the embodiments, the fifth transistor T9 may be omitted, as shown in
In the embodiments, the pulse amplitude modulation unit includes a first drive transistor T2, a sixth transistor T1, and a third capacitor C1. Specifically, a source of the sixth transistor T1 is connected to a data line data, a drain of the sixth transistor T1 is connected to a gate of the first drive transistor T2 and to a first pole plate of the third capacitor C1, and a gate of the sixth transistor T1 is connected to the first scan control line scant. The sixth transistor T1 can charge a data voltage to the first drive transistor T2 to turn on the first drive transistor T2, and the data voltage is maintained through the third capacitor C1, such that the first drive transistor T2 is always in the turned-on state. The gate voltage of the first drive transistor T2 is controlled by controlling the magnitude of the data voltage, thereby controlling the driving current.
In the embodiments, the pulse amplitude modulation unit may compensate directly the voltage to the gate of the first drive transistor T2 through the data line data. In other embodiments, the pulse amplitude modulation unit may be other internal compensation structures for compensation, which will not be described in detail herein.
In the embodiments, the pixel drive circuit further includes a driving current detection unit, arranged between the pulse amplitude modulation unit and the pulse width modulation unit, to detect the driving current of the pulse amplitude modulation unit when the second drive transistor of the pulse width modulation unit is turned off. Specifically, an end of the driving current detection unit is connected to the drain of the first drive transistor of the pulse amplitude modulation unit, and the other end is connected to the data line data through a measurement line, for detecting the driving current of the first drive transistor and subsequently compensating the data line data, thereby achieving amplitude control of the driving current.
Specifically, the driving current detection unit includes a first switch transistor T3; a source of the first switch transistor T3 is connected to the drain of the first drive transistor T2, a drain of the first switch transistor T3 is connected to the measurement line detect, and a gate of the first switch transistor T3 is connected to a scan control line. The scan control line controls to turn on the first switch transistor T3. In the embodiments, the scan control line is the second scan control line scan2 to control to turn on the first switch transistor T3 in a second stage, thereby achieving the measurement of the driving current. The measurement line detect is connected to a timing controller to facilitate compensation of the data line data at a subsequent stage. The first switch transistor T3 and the third transistor T6 share the second scan control line scan2, which enables the detection of the driving current and avoids adding more alignments. In other embodiments, the scan control line is the third scan control line scan3, which will not be limited herein.
In the embodiments, T1, T2, T3, T4, T5, T6, T7, T8, T9, T10 in the pixel drive circuit are each a low-potential conduction P-type transistor. In other embodiments, T1, T2, T3, T4, T5, T6, T7, T8, T9, T10 may all be N-type transistors with high potential conduction, or form a mixed drive circuit with some transistors being P-type and some transistors being N-type, which will not be limited herein.
The following is an example of a driving method in which T1, T2, T3, T4, T5, T6, T7, T8, and T10 are all P-type transistors with low potential conduction.
The present disclosure provides a first driving method according to the structure of the pixel driving transistor of the first embodiment. Specifically, referring to
In the first stage, the first scan control line of an Nth row controls the sixth transistor T1 and the first transistor T8 to be turned on, the data voltage Vdata of the data line data is transmitted through the sixth transistor T1 to the first pole plate of the third capacitor C1 and the gate of the first drive transistor T2, and the data voltage Vdata is maintained through the third capacitor C1 to achieve the amplitude setting of the driving current of the first drive transistor T2. In addition, the first voltage Vgh1 of the first signal line gh1 is transmitted through the first transistor T8 to the gate of the second drive transistor T4 and to the first pole plate of the first capacitor C2, and the first voltage Vgh1 is maintained through the first capacitor C2 to keep the second drive transistor T4 in a turned-off state. The first voltage Vgh1 shall be a positive voltage to make the second drive transistor T4, which is turned on at a low level, turned off. Obviously, when the second drive transistor T4 is negative, the first voltage Vgh1 shall be negative, which is not limited herein. The first voltage Vgh1 is of a value that makes the second drive transistor T4 turned off.
Specifically, further referring to
In the second stage, the second scan control line scan2 of an Nth row controls the third transistor T6 to be turned on, and the third voltage Vgh2 of the third signal line gh2 is transmitted through the third transistor T6 to the gate of the second transistor T7 and the first pole plate of the second capacitor C3, to keep the second transistor T7 turned off through the second capacitor C3. In addition, the third scan control line scan3 controls the fourth transistor T5 to be turned on, and a first level voltage Va of the control signal line a is written to the second pole plate of the second capacitor C3 through the fourth transistor and transmitted to the gate of the second transistor T7 through the coupling effect of the second capacitor C3. The first level voltage Va is a negative voltage, i.e. −Va.
Specifically, referring to
Since it is possible for Vgh2-Va to be less than 0, such that the second transistor T7 of the P-type is turned on not within expectation, and the second drive transistor T4 may be turned on, causing the light-emitting element LED to emit light. In the embodiments, by arranging the second switch transistor T10 between the second drive transistor T4 and the light-emitting element LED, the power supply line VDD and the light-emitting element LED are thereby controlled to be turned off. In other embodiments, the second drive transistor T4 is prevented from being turned on by arranging the fifth transistor T9 for compensation at the gate of the second drive transistor T4 such that the gate voltage of the second drive transistor T4 is maintained at a voltage that causes turning-off.
In other embodiments, the first level voltage Va may be controlled such that Vgh2-Va is greater than or equal to 0, thereby making the second transistor T7 turned off and controlling the second drive transistor T4 to be turned off, without limitation herein.
In the embodiments, even if the second drive transistor T4 is turned on, the light-emitting element LED does not emit light because the second switch transistor T10 in the turned-off state. When the second transistor T7 is turned on not within expectation, the voltage at point C will change, i.e., the initial voltage at point C does not change from Vgh1 to Vg1 before the start of the light-emitting stage, but from an unknown voltage to Vg1. However, In the embodiments, as shown in
In the embodiments, the driving current may be measured by controlling the first switch transistor T3 to be turned on in the second stage. In other embodiments, it is also possible to control the first switch transistor T3 to be turned on in the third stage to measure the driving current, without limitation herein. Specifically, the scan control line is either the second scan control line scant or the third scan control line scan3, or in other embodiments, the scan control line may be a separate control signal line. In the second stage, the scan control line of an Nth row controls the first switch transistor T3 to be turned on such that the drain of the first drive transistor T2 forms a path with the measurement line detect, thereby measuring the driving current of the first drive transistor T2 through the measurement line detect.
In the third stage, the third scan control line scan3 of an Nth row controls the fourth transistor T5 to be turned on, and a second level voltage Va0=0V of the control signal line a is written to the second pole plate of the second capacitor C3 through the fourth transistor and transmitted to the gate of the second transistor T7 through the coupling effect of the second capacitor C3 to turn off the second transistor T7.
Specifically, referring to
In the third stage, the width of the signal change of the control signal line a is less than the width of the third scan control line scan3, as shown in
In the fourth stage, the third scan control lines scan3 of all rows control the fourth transistor T5 to be turned on, and the swing voltage Vsweep of the control signal line a is transmitted through the fourth transistor T5 to the gate of the second transistor T7 to control the second transistor T7 to be turned on, at which time the second voltage of the second signal line Vg1 is transmitted through the second transistor T7 to the gate of the second drive transistor T4 to control the second drive transistor T4 to be turned on.
In the embodiments, in the fourth stage, the fourth scan control line EM controls the second switch transistor T10 to be turned on such that the light-emitting element LED and the power supply line VDD form a path.
Specifically, referring to
The swing voltage Vsweep is uniformly rising voltage or uniformly falling voltage, and when rising or falling to a certain value, it reaches a turning-on voltage (Vth) of the second transistor T7 and is maintained by the second capacitor C3, such that the second transistor T7 is always turned on, controlling the second drive transistor T4 to be turned on, such that the light-emitting element LED emits light. When the swing voltage Vsweep returns to −Va potential, the potential at the point E returns to Vgh2 and the second transistor T7 is turned off. At this time, the second drive transistor T4 is in the turned-on state at the second voltage Vg1. Therefore, it is necessary to control the light-emitting element LED not to emit light by controlling the second switch transistor T10 to be turned off. In the embodiments, after the end of luminescence, the voltage at point C remains at Vg1 until the next time the first transistor T8 is turned on, and then becomes Vgh1. The Vgh1 may be zero or positive.
In the fourth stage, the third scan control line scan3 is at a low potential voltage and the fourth transistor T5 is always turned on, such that the swing voltage Vsweep is input to the gate of the second transistor T7.
In the embodiments, when without the second switch transistor T10, the second drive transistor T4 is always turned on at the second voltage Vg1, which can keep the light-emitting element LED in the light-emitting state and thus cannot achieve the purpose of modulating the width. In other embodiments, the second switch transistor T10 may be arranged between the gate of the second drive transistor T4 and the drain of the second transistor T7.
In the embodiments, the second transistor T7 is a P-type transistor, and the swing voltage Vsweep is a uniformly falling voltage. The swing voltage Vsweep is coupled through a capacitor to point E. The voltage at point E is uniformly pulled down, and when the collimation at point E reaches the turning-on voltage of the second transistor T7 (i.e., the threshold voltage Vth), the second voltage Vg1 of the second signal line is written to point C, causing the second drive transistor T4 to be turned on, at which time the loop from VDD to VSS is turned on and the LED emits light. Assuming a uniformly decreasing slope of Vsweep of K and a total time of the light-emitting stage of T0, the light-emitting time is T0−(Vgh2+Va−Vth)/K. The light-emitting time is related not only to K but also to the Va voltage.
Therefore, in a specific embodiment, the Va voltage may be compensated by the control signal line a. Since the first drive transistor T2 and the second transistor T7 are located in the same pixel, the threshold voltages Vth of T2 and T7 are considered to drift to the same extent. In the second stage, when the driving current detection unit compensates for the data line data, it can also compensate for the Va voltage, thereby enabling pulse width modulation.
In other embodiments, when the second transistor T7 is a P-type transistor, the swing voltage Vsweep is a uniformly rising voltage, and the light-emitting time of the light-emitting element LED is also related to the slope of the swing voltage Vsweep. For the analysis process, reference may be made to the above embodiments, which will not be repeated herein.
The beneficial effect of the first embodiment is that the driving current and light-emitting time of the light-emitting element LED in the pixel are adjusted by controlling the gate voltage of the first drive transistor and the second drive transistor, respectively. The driving current of the LED is measured by the driving current detection unit to facilitate subsequent compensation adjustment of the driving current. In addition, the pulse width modulation of the driving current I is achieved by the slope of the swing voltage.
In the embodiments, the control signals of the first scan control line scant, the second scan control line scan2, the third scan control line scan3, the control signal line a, and the fourth scan control line EM are at low-level voltages. In other embodiments, the control signals of the first scan control line scant, the second scan control line scan2, the third scan control line scan3, the control signal line a, and the fourth scan control line EM may be high-level voltages, or partly high-level voltages and partly low-level voltages, depending on the P/N type of the transistor, without limitation herein.
The present disclosure further provides a second pixel drive circuit. Specifically, referring to
Specifically, a first pole plate of the first capacitor C2 is connected to a gate of the second drive transistor T4, and a second pole plate of the first capacitor C2 is connected to a high-potential power supply line VDD.
A source of the first transistor T8 is connected to a first signal line gh1, a drain of the first transistor T8 is connected to the gate of the second drive transistor T4 and the first pole plate of the first capacitor C2, and a gate of the first transistor T8 is connected to a first scan control line scant. The first transistor T8 is configured to charge a first voltage gh1 to the gate of the second drive transistor T4, and the first voltage gh1 is maintained through the first pole plate of the first capacitor C2. The first voltage gh1 is configured to turn off the second drive transistor T4.
A source of the second transistor T7 is connected to a second signal line g1, a drain of the second transistor T7 is connected to the gate of the second drive transistor T4, and a gate of the second transistor T7 is connected to a drain of the third transistor T6 and to a first pole plate of the second capacitor C3.
A source of the third transistor T6 is connected to a third signal line gh2, a drain of the third transistor T6 is connected to the gate of the second transistor T7, and a gate of the third transistor T6 is connected to a second scan control line scan2 and to the first pole plate of the second capacitor C3.
A source of the fourth transistor T5 is connected to a control signal line a, a drain of the fourth transistor T5 is connected to a second pole plate of the second capacitor C3, and a gate of the fourth transistor T5 is connected to a third scan control line scan3. The voltage of the gate of the second transistor T7 is adjusted by the third transistor T6 and the fourth transistor T5 cooperatively.
A source of the fifth transistor T9 is connected to the first signal line gh1, a drain of the fifth transistor T9 is connected to the gate of the second drive transistor T4 and to the first pole plate of the first capacitor C2, and a gate of the fifth transistor T9 is connected to the second scan control line scan2.
In the embodiments, by turning on the fifth transistor T9 in a second stage, the fifth transistor T9 is made to be turned on simultaneously with the third transistor T6, such that even if the second transistor T7 is turned on and the second drive transistor T4 is charged with the Vg1 voltage, the gate of the second drive transistor T4 may be charged by the fifth transistor T9 to offset the voltage of the second drive transistor T4, thereby keeping the voltage of the second drive transistor T4 constant.
In the embodiments, the resistance of the fifth transistor T9 is much less than the resistance of the second transistor T7, such that the voltage charged by the second transistor T7 to the second drive transistor T4 flows out through the fifth transistor T9 without causing a change in the gate voltage of the second drive transistor T4.
In the embodiments, the timing diagram of the driving signals of each transistor is similar to that of the first embodiment, and details thereof may refer to
In the embodiments, the difference lies only in that the fifth transistor T9 is turned on in the second stage. Specifically, referring to
In the second stage, the fifth transistor T9 is controlled to be turned on. In this way, even though T7 is turned on at a certain instant, the potential at point C does not change too much due to the turning-on of the fifth transistor T9, thereby ensuring the turned-off state of the second drive transistor T4. Specifically, the gate of the fifth transistor T9 is controlled by the second scan control line scant to be turned on at the second stage such that the first voltage Vgh1 of the first signal line gh1 is transmitted to the first pole plate of the first capacitor C2 and to the gate of the second drive transistor T4, keeping the voltage of the gate of the second drive transistor T4 from changing abruptly and keeping the second drive transistor T4 being turned on. The conduction of each of the other transistors remains unchanged, as described in the first embodiment.
In the first, third, and fourth stages, the conduction of each transistor remains unchanged, as described in the first embodiment.
In the embodiments, the third scanning control line scan3 controls the fourth transistor T5 to be turned on, the swing voltage Vsweep of the control signal line a controls the second transistor T7 to be turned on, and the second voltage Vg1 of the second signal line g1 controls the second drive transistor T4 to be turned on. The first drive transistor T2 remains in the turned-on state in the presence of the third capacitor C1 until a next data writing stage starts. When the next data writing stage is started, the first scan control line scant controls the first transistor T8 to be turned on, writing an initial voltage to the second drive transistor T4, such that the second drive transistor T4 is turned off and the light-emitting element LED emits light. In the embodiments, the second drive transistor T4 is in an uncontrollable stage between the end of the light-emitting stage and the start of the next writing stage, i.e., the present embodiment is less preferred than the first embodiment.
The beneficial effect of the embodiments is that the PWM is turned on in the light-emitting stage and is off in the non-light-emitting stage by internal compensation of the PWM.
The present disclosure further provides a display panel, the display panel includes multiple pixel cells arranged in an array, and each pixel cell is arranged with the pixel drive circuit in any of the above embodiments. Specifically, referring to
The beneficial effect of the present disclosure is that the PAM and PWM modulation of the light-emitting elements in the display panel is realized by 9/10 TFTs and 3 capacitors C and multiple control lines.
The above is only an embodiment of the present disclosure and is not intended to limit the scope of the present disclosure. Any equivalent structure or equivalent process transformation made by using the contents of the specification and the accompanying drawings of the present disclosure, or applied directly or indirectly in other related technical fields, are included in the scope of the present disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202211401508.3 | Nov 2022 | CN | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 11798470 | Li | Oct 2023 | B1 |
| 20140333686 | Kim | Nov 2014 | A1 |
| 20190371232 | Kim | Dec 2019 | A1 |
| 20220114951 | Chang | Apr 2022 | A1 |
| Number | Date | Country |
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| 110021264 | Jul 2019 | CN |
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| 112767874 | May 2021 | CN |
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| 112927651 | Jun 2021 | CN |
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| 114333685 | Apr 2022 | CN |
| 14519980 | May 2022 | CN |
| 112927651 | May 2022 | CN |
| 114566115 | May 2022 | CN |
| 114783358 | Jul 2022 | CN |
| 115662343 | Jan 2023 | CN |
| 20030044566 | Jun 2003 | KR |
| Entry |
|---|
| Chinese First Office Action, Chinese Application No. 202211401508.3, mailed Feb. 3, 2023 (16 pages). |
| Notification to Grant Patent Right for Invention, Chinese Application No. 202211401508.3, mailed Feb. 25, 2023 (4 pages). |
| International Search Report, International Application No. PCT/CN2023/094634, mailed Aug. 1, 2023 (15 pages). |
| Number | Date | Country | |
|---|---|---|---|
| 20240153442 A1 | May 2024 | US |
