Patent Application
20250140181
The present disclosure relates to a field of display technology, and in particular to a field of display panel manufacturing technologies, and specifically to a pixel driving circuit and a display panel.
Compared with liquid crystal displays, self-emitting displays have the advantages of high color gamut, high contrast ratio, short response time and high bendability, and are well recognized by the industry as having a great development potential in the next generation of display.
Currently, the light emitting elements in the self-emitting display are all current-driven. That is, light emitting brightness depends on a magnitude of a current flowing through the light emitting elements. After the panel is produced, the light emitting brightness of the light emitting element is generally adjusted by adjusting the magnitude of the data voltage, while the gate-source voltage of the driving transistor does not change in the light emitting stage, so the light emitting brightness of the light emitting element cannot be changed. However, limited by the hardware influence of the data driving chip, and considering the impact of compensation in terms of a threshold voltage, a uniformity image, and the like, the driving transistor has a relatively low gate-source voltage in the light emitting stage, so that the current flowing through the light emitting element is relatively small, and brightness of the light emitting element and a self-emitting display formed thereby is relatively low.
Therefore, an existing self-emitting display has a relatively low light emitting brightness due to the limitation of the hardware of the data driving chip, which needs to be improved.
Embodiments of the present disclosure provide a pixel driving circuit and a display panel, so as to resolve a technical problem that the existing self-emitting display has a relatively low light emitting brightness restricted to the hardware influence of the data driving chip.
The present disclosure provides a pixel driving circuit, including:
The present disclosure provides the pixel driving circuit and the display panel, including: the driving transistor connected in series with the light emitting element between the first power supply line and the second power supply line, wherein the source of the driving transistor is electrically connected to the light emitting element; the data transistor, wherein the source of the data transistor is electrically connected to the data line, the drain of the data transistor is electrically connected to the gate of the driving transistor, and the gate of the data transistor is loaded with the data control signal; and the boost module, wherein the input terminal of the boost module is configured to be loaded with the boost input signal, and the output terminal of the boost module is electrically connected to the gate of the driving transistor; wherein the boost module controls the voltage of the gate of the driving transistor to boost from the first voltage in the first stage to the second voltage in the second stage, the second stage is later than the first stage, and the driving transistor is configured to generate the driving current based at least on the second voltage to drive the light emitting element to emit light; wherein the boost module includes: the first capacitor, wherein the first electrode plate of the first capacitor is electrically connected to the input terminal of the boost module to be loaded with the boost input signal; the second capacitor, wherein the first electrode plate of the second capacitor is loaded with the first signal; and the third capacitor, wherein the first electrode plate of the third capacitor is electrically connected to the gate of the driving transistor to serve as the output terminal of the boost module, and all of the second electrode plate of the first capacitor, the second electrode plate of the second capacitor, and the second electrode plate of the third capacitor are electrically connected to the same node. In the present disclosure, by disposing the boost module of which the input terminal is loaded with the boost input signal and the output terminal is electrically connected to the gate of the driving transistor through the first capacitor, the second capacitor, and the third capacitor forming a “T” type network, in combination with a voltage dividing function of the first capacitor and the second capacitor as well as a coupling effect of the third capacitor, the gate voltage of the driving transistor can be modulated by being boosted from the first voltage to the second voltage, so as to increase the driving current flowing through the light emitting element, thereby improving light emitting brightness of the light emitting element, and thus improving brightness of the display panel.
The present disclosure is further illustrated below by referring to the accompanying drawings. It should be noted that the accompanying drawings in the following description are merely intended to explain some embodiments of the present disclosure. A person skilled in the art may still obtain other drawings from these accompanying drawings without creative efforts.
Technical solutions in embodiments of the present disclosure will be clearly and completely described below in conjunction with drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of embodiments of the present disclosure, rather than all the embodiments. Any ordinarily skilled person in the technical field of the present invention could still obtain other accompanying drawings without use laborious invention based on the present accompanying drawings.
The terms “first”, “second” and “third” in the present disclosure are used to distinguish different objects, and are not used to describe a specific order. In addition, the terms “include” and “have” and any variations thereto are intended to cover non-exclusive inclusions. For example, a process, a method, a system, a product, or a device that includes a series of steps or modules is not limited to the listed steps or modules, but optionally further includes the unlisted steps or modules, or optionally further includes another step or module inherent to the process, the method, the product, or the device. In addition, the terms “source” and “drain” may be interchanged, as long as a corresponding transistor has at least one source and at least one drain.
The term “embodiments” referred in this specification means that specific features, structures, or characteristics described in connection with the embodiments may be included in at least one embodiment of the present disclosure. The term “embodiments” appearing at all locations in the specification does not necessarily refer to same embodiments, or they are independent or alternative embodiments that are compatible or not compatible each other. It is explicitly and implicitly understood by a person skilled in the art that the embodiments described in this specification may be combined with other embodiments.
An embodiment of the present disclosure provides a pixel driving circuit. The pixel driving circuit includes, but not limited to, those illustrated in the following embodiments and a combination of the following embodiments.
In an embodiment, as shown in
As shown in
Specifically, as shown in
It should be noted that, when the pixel driving circuit 100 is in a light emitting stage, because the light emitting element L has a relatively stable voltage drop, the source voltage Vs of the source S of the driving transistor TI may be a relatively stable value. That is, it may be considered that, in this case, the light emitting brightness of the light emitting element L may be determined by the gate voltage Vg of the gate G of the driving transistor T1. It may be known in combination with the foregoing that the gate voltage Vg loaded to the gate G of the driving transistor T1 may generally be determined based at least on a voltage value corresponding to an expected gray scale of the light emitting element L. However, limited by hardware of a data driving chip, and considering the impact of compensation such as a threshold voltage and an uniformity image, it is actually relatively small for a voltage that is “determined based on a voltage value corresponding to an expected gray scale of the light emitting element L” and loaded to the gate G of the driving transistor T1, so that a driving current flowing through the light emitting element L is relatively small, and thus the light emitting brightness of the light emitting element L is relatively low.
It may be understood that the present embodiment is provided with the boost module 10 of which the input terminal is loaded with the boost input signal CK and the output terminal is electrically connected to the gate G of the driving transistor T1. Compared with the foregoing, that is, the gate voltage Vg of the gate G of the driving transistor T1 may further be determined by the boost input signal CK. In the first stage, the gate G of the driving transistor T1 has the first voltage Vg1. In combination with the foregoing, the first stage herein may be considered as the “light emitting stage” mentioned above. The first voltage Vg1 may be determined by at least the voltage that is “determined based on a voltage value corresponding to an expected gray scale of the light emitting element L” and loaded to the gate G of the driving transistor T1, and the first voltage Vgl causes the gate-source voltage Vgs of the driving transistor T1 to drive the light emitting element L to emit light having the first brightness at this time, where “the voltage value corresponding to an expected gray scale of the light emitting element L” can be understood as above-mentioned data signal transmitted by the respective data line. Further, in the present embodiment, the boost module 10 can be configured to be in the second stage so that the gate G of the driving transistor T1 has the second voltage Vg2 related to the boost input signal CK, where the second voltage Vg2 is greater than the first voltage Vg1, and the second stage herein may be understood as “brightening stage” after the first stage (light emitting stage). That is, the gate voltage Vg of the driving transistor T1 may be boosted from the first voltage Vg1 to the second voltage Vg2 under the action of the boost module 10 and the boost input signal CK, so as to increase the driving current flowing through the light emitting element L. The second voltage Vg2 causes the gate-source voltage Vgs of the driving transistor T1 to drive the light emitting element L to emit light having the second brightness larger than the first brightness at this time, so as to improve the light emitting brightness of the light emitting element L. A specific structure of the boost module 10 and a waveform of the boost input signal CK may be properly set according to an actual situation, so as to better improve light emitting brightness of the light emitting element L.
As shown in
In an embodiment, as shown in
The first boost transistor T2 may be an N-type transistor or a P-type transistor. An example in which the first boost transistor T2 is an N-type transistor is taken herein. Specifically, as shown in
Certainly, as shown in
Particularly, when the first boost transistor T2 is turned on without considering change of the first signal on the first wiring, if a voltage value of the boost input signal CK remains unchanged, that is, a voltage of the node A remains unchanged, then the gate voltage Vg of the gate G of the driving transistor T1 also remains unchanged when the gate G of the driving transistor T1 is switched from the first voltage Vg1 being loaded to the gate G to a floating state because the voltage difference across the first capacitor C1 cannot be abruptly changed.
Specifically, an example is taken herein, in which the voltage value of the first signal in the first stage is equal to the voltage value of the first signal in the second signal. In combination with the foregoing, the voltage value corresponding to the boost input signal CK is boosted from the first boost input voltage Vcl to the second boost input voltage Vch in both the first stage and the second stage. The voltage at the node A is changed correspondingly due to the voltage dividing function of the first capacitor C1 and the second capacitor C2. In combination with the coupling effect of the third capacitor C3, that is, a voltage difference between the first electrode and the second electrode of the third capacitor C3 cannot be abruptly changed, so that the gate voltage Vg of the gate G of the driving transistor T1 is boosted from the first voltage Vg1 to the second voltage Vg2, thereby increasing the driving current flowing through the light emitting element L to improve light emitting brightness of the light emitting element L. The specific structure and parameters of the boost module 10 and the waveform of the boost input signal CK may be appropriately set according to an actual situation, so that the light emitting brightness of the light emitting element L is preferably improved.
Further, the first wiring may be connected to the source S of the driving transistor T1 (i.e., the first electrode plate of the second capacitor C2 is electrically connected to the source S of the driving transistor T1) as shown in FIG.4, or the first wiring may be connected to the drain D of the driving transistor T1 (i.e., the first electrode plate of the second capacitor C2 is electrically connected to the drain D of the driving transistor T1) as shown in
In combination with the foregoing, the first signal may also have different voltages in the first stage and the second stage. For example, when the voltage value of the first signal in the second stage is greater than the voltage value of the first signal in the first stage, it needs to be satisfied that the absolute value of the change value of the voltage of the first signal acting on the node A in the first stage and the second stage is less than the absolute value of the change value of the voltage of the boost input signal CK in the first stage and the second stage. For example, when the voltage value of the first signal in the second stage is less than the voltage value of the first signal in the first stage, the change value of the voltage of the boost input singal CK acting on the node A in both the first stage and the second stage may be less than or even equal to 0.
In an embodiment, as shown in
Specifically, in combination with the foregoing, based on such an embodiment in which the gate of the first boost transistor T2 may be electrically connected to the gate G of the driving transistor T1 to obtain the gate voltage Vg of the gate G of the driving transistor T1 as the first boost control signal, the embodiment is equivalent to an embodiment which adds a second boost transistor T3 connected in series between the input terminal of the boost module 10 and the source of the first boost transistor T2 that is controlled by the second boost control signal to be turned on. Both the first boost control signal and the second boost control signal may be considered to jointly determine whether the boost input signal CK can be loaded to the node A, where the second boost control signal may be, but not limited to, the light emitting control signal EM. In combination to the foregoing, that is, on the basis of controlling, by means of the first boost control signal, whether to turn on the first boost transistor T2 in the first stage and the second stage, the present embodiment can implement further control on whether the boost input signal CK can be loaded to the node A by using the added second boost control signal and the added second boost transistor T3, thereby improving an accuracy of the operation of the boost block 10.
In an embodiment, as shown in
Likewise, in combination with the foregoing, the gate G of the driving transistor T1 has the first voltage Vg1 in the first stage, and the first stage may be considered as the foregoing “light emitting stage”. The first voltage Vg1 may be determined by at least the voltage that is “determined based on the voltage value corresponding to the expected gray scale of the light emitting element L” and loaded to the gate G of the driving transistor T1. Specifically, in the embodiment, the boost module 10 is further configured to cause the gate G of the driving transistor T1 to have the third voltage Vg3 in the third stage. The third stage may be understood as a data writing stage earlier than the light emitting stage. That is, the third voltage Vg3 may be equal to the voltage that is “determined based on the voltage value corresponding to the expected gray scale of the light emitting element L” and loaded to the gate G of the driving transistor T1. In this case, the source S of the driving transistor Vg3 has a relatively low voltage. Further, in combination with the foregoing, because the light emitting element L is turned on in the light emitting stage later than the third stage, the voltage of the source S of the driving transistor Vg3 is boosted. Because the voltage difference across the fourth capacitor C4 cannot be abruptly changed, the gate voltage Vg of the gate G of the driving transistor Vg3 may also be boosted from the third voltage Vg3 to the first voltage Vg1, so as to increase the gate-source voltage Vgs of the driving transistor T1 and the driving current flowing through the light emitting element L to improve the light emitting brightness of the light emitting element L.
Therefore, when the third voltage Vg3 is constant, the change amount of the gate voltage Vg of the gate G of the driving transistor T1 is related to the voltage of the source S of the driving transistor T1, and is specifically related to the difference of the voltages of the source S of the driving transistor T1 in the third stage and the first stage. It should be noted that, in combination with the foregoing, the boost switch K in the embodiment may be closed at least in the third stage and the first stage, so that the fourth capacitor C4 is electrically connected between the gate G and the source S of the driving transistor T1 to enable the gate voltage Vg of the gate G of the driving transistor T1 to be changed with the change of the source voltage Vs of the source S of the driving transistor T1, and may be opened in the second stage, so as to avoid a case that the gate-source voltage Vgs cannot be boosted due to the source voltage Vs of the source S of the driving transistor T1 being synchronously changed with the change of the gate voltage Vg of the gate G of the driving transistor T1 and the driving current flowing through the light emitting element L cannot be increased.
In an embodiment, as shown in
It should be noted that the pixel driving circuit 100 in the present disclosure may include the boost module 10 and the driving transistor T1 as described above. Further, the pixel driving circuit 100 may further include a data writing module and a reset module that are electrically connected to the driving transistor T1. The data writing module may be electrically connected to one of the gate G and the source S of the driving transistor T1, and the reset module may be electrically connected to another of the gate G and the source S of the driving transistor T1. Specifically, an example is taken in the embodiment, in which the data writing module is electrically connected to the gate G of the driving transistor T1, the reset module is electrically connected to the source S of the driving transistor T1, the data writing module includes the data transistor T4 mentioned above, and the reset module includes the reset transistor T5 mentioned above. That is, an example is taken in the embodiment, in which the pixel driving circuit 100 can include an 3T1C circuit consisted of the driving transistor T1, the data transistor T4, the reset transistor T5, and the second capacitor C2. Certainly, the circuit included in the pixel driving circuit 100 is not limited to the 3T1C circuit, and may further include, for example, a 6T1C circuit, a 7T1C circuit, or other circuits.
It may be understood that, in combination with the foregoing, in the embodiment, the data control signal, Scan, may control the data transistor T4 to be turned on at least in the third stage, so that the data signal, Data, on the data line is loaded to the gate G of the driving transistor T1 to turn on the driving transistor T1, and the reset control signal, Sense Gate, may control the reset transistor T5 to be turned on at least before the third stage, so that the reset signal Vref on the reset line is loaded to the source S of the driving transistor T1 to reset the source S of the driving transistor T1.
In an embodiment, as shown in
In an embodiment, as shown in
An embodiment of the present disclosure provides a display panel including a pixel driving circuit. The pixel driving circuit includes: a first transistor connected in series with a light emitting element between a first power supply line and a second power supply line, where a source of the first transistor is electrically connected to the light emitting element; a second transistor, where a source of the second transistor is electrically connected to a first signal line, a drain of the second transistor is electrically connected to a gate of the first transistor, and a gate of the second transistor is electrically connected to a second signal line; and a first module, where an input terminal of the first module is electrically connected to a third signal line, an output terminal of the first module is electrically connected to the gate of the first transistor, and a control terminal of the boost module is electrically connected to a fourth signal line; where the first module includes: a first capacitor, where a first electrode plate of the first capacitor is electrically connected to an input terminal of the first module; a second capacitor, where the first electrode plate of the second capacitor is electrically connected to the first wiring; and a third capacitor, where a first electrode plate of the third capacitor is electrically connected to the gate of the first transistor to serve as the output terminal of the first module, where the second electrode plate of the first capacitor, the second electrode plate of the second capacitor, and the second electrode plate of the third capacitor are electrically connected to the same node.
Specifically, the first module may further include a first sub-module, and an input terminal of the first sub-module is configured as the input terminal of the first module. Further, in combination with
In an embodiment, the first sub-module includes: a third transistor, where a drain of the third transistor is electrically connected to a first electrode plate of the first capacitor to serve as the output terminal of the first sub-module, a source of the third transistor is electrically connected to the input terminal of the first module, and a gate of the third transistor is electrically connected to the fifth signal line.
Further, in combination with
In an embodiment, the first sub-module further includes: a fourth transistor, wherein a drain of the fourth transistor is electrically connected to the source of the third transistor, a source of the fourth transistor is electrically connected to the input terminal of the first module, and a gate of the fourth transistor is electrically connected to a sixth signal line different from the gate of the first transistor; where, the gate of the third transistor is electrically connected to the gate of the first transistor.
Further, as shown in
In an embodiment, the first electrode plate of the second capacitor is electrically connected to the drain of the first transistor, and the first module further includes a fourth capacitor; a first switch connected in series with the fourth capacitor between the gate of the first transistor and the source of the first transistor; where the first switch is configured to control the fourth capacitor to be electrically connected between the gate of the first transistor and the source of the first transistor.
Further, as shown in
In an embodiment, the pixel driving circuit further includes: a fifth transistor, where a source of the fifth transistor is electrically connected to a sixth signal line, a drain of the fifth transistor is electrically connected to the source of the first transistor, and a gate of the fifth transistor is electrically connected to an eighth signal line.
Further, in combination with
An embodiment of the present disclosure provides a driving method for driving the pixel driving circuit 100 according to any of the foregoing as shown in
Specifically, in combination with the foregoing, the magnitude of the driving current flowing through the light emitting element L is positively correlated with the gate-source voltage Vgs between the gate G and the source S of the driving transistor T. The first stage is used as the light emitting stage, and in a subsequent light emitting process of the light emitting element L, it may be considered that the source voltage Vs of the source S of the driving transistor T1 is approximately equal to the voltage of the source S of the driving transistor T1 in the first stage. Therefore, in the embodiment, the boost input signal CK is configured, in the first stage, based on the source voltage Vs of the source S of the driving transistor T1, so that the second voltage Vg2 may be configured based on the source voltage Vs of the source S of the driving transistor T1. For example, if the source voltage Vs of the source S of the driving transistor T1 is larger and the first boost input voltage Vcl of the corresponding boost input signal Vcl in the first stage is constant (for example, is equal to zero), the second boost input voltage Vch of the boost input signal CK in the second stage may be configured to be larger, so that the second voltage Vg2 of the gate G of the driving transistor T1 is larger. Therefore, the gate-source voltage Vgs between the gate G and the source S of the driving transistor T1 is appropriate in the second stage.
Specifically, based on the circuit diagrams shown in
In the reset stage t1, the data control signal, Scan, is configured to be equal to a corresponding high potential to control the data transistor T4 to be turned on, and the data signal Data on the data line is configured to be equal to a corresponding low potential to be transmitted to the gate G of the driving transistor T1 via the data transistor T4 to reset the gate G of the driving transistor T1. At the same time, the reset control signal Sense Gate is configured to be equal to a corresponding high potential to control the reset transistor T5 to be turned on, and the reset signal Vref on the reset line is configured to be equal to a corresponding low potential to be transmitted to the source S of the driving transistor T1 via the reset transistor T5 to reset the source S of the driving transistor T1;
In the data writing stage t2, the data control signal Scan maintains a corresponding high potential to maintain the data transistor T4 to be turned on, and the data signal Scan on the data line is configured to be equal to a corresponding high potential Vdata to be transmitted to the gate G of the driving transistor T1 via the data transistor T4, so that the gate voltage Vg of the gate G of the driving transistor T1 is equal to Vdata and the second boost control signal (for example, the light emitting control signal EM) is maintained at the corresponding high potential. The boost input signal CK at the input terminal of the boost module 10 is configured to be equal to the corresponding low potential Vel and be transmitted to the first electrode via the first capacitor C1 to maintain the voltage to be unchanged. At the same time, the reset control signal, Sense Gate, maintains the corresponding high potential to maintain the reset transistor T5 to be turned on, and the reset signal Vref on the reset line is constantly equal to the corresponding low potential and be transmitted to the source S of the driving transistor T1 to maintain the voltage to be unchanged, so as to maintain the light emitting element L to be cutted off. In combination with the electrics characteristics related to the “T” type network, the voltage at the node A may be equal to ΔVdata*C3/(C1+C2+C3);
In a light emitting stage t3, the data control signal Scan is configured to be equal to a corresponding low potential to control the data transistor T4 to be turned off, and the reset control signal Sense Gate is configured to be equal to a corresponding low potential to control the reset transistor T5 to be turned off. Firstly, the gate voltage Vg of the gate G of the driving transistor T1 is still equal to Vdata at the initial moment of the light emitting stage t3, so that the reset transistor T5 is turned off. A path formed by at least the third capacitor C3 and the first capacitor C1 is maintained to be still equal to Vdata so as to maintain the driving transistor T1 to be still turned on. The second power supply signal VDD on the second power supply line is constantly equal to a corresponding high potential and the first power supply signal VSS on the first power supply line is constantly equal to a corresponding low potential, so that the light emitting element L is turned on, a driving current I flows through the light emitting element L in the first current value I1, and the source voltage Vs of the source S of the driving transistor T1 is equal to a conduction voltage drop VL of the light emitting element L. The source voltage Vs of the source S of the driving transistor T1 is equal to the conduction voltage drop VL of the light emitting element L. The second boost control signal (for example, the light emitting control signal EM) is still maintained at the corresponding high potential to enable the first boost transistor T1 to be still maintained to be turned on, so that the boost input signal CK is equal to the corresponding low potential Vcl to be transmitted to the first electrode plate of the first capacitor C1 to maintain the voltage to be unchanged. In combination with the electrics characteristics related to the “T” type network, the voltage at the node A may be boosted to ΔVdata*C3/(C1+C2+C3)+ΔVs*C2/(C1+C2+C3), where ΔVs is the change amount of the source voltage Vs of the source S of the driving transistor T1, which may be equal to the conduction voltage drop VL;
In a brightening stage t4, at its initial moment, the gate voltage Vg of the gate G of the driving transistor T1 is still equal to Vdata, and the second boost control signal (e.g., the light emitting control signal EM) is still maintained at the corresponding high potential so that the first boost transistor T2 is still maintained to be turned on. The boost input signal CK is configured to be equal to the corresponding high potential Vch so as to be transmitted to the first electrode plate of the first capacitor C1 to be increased by (Vch−Vcl). The source voltage Vs of the source S of the driving transistor T1 is configured to be still equal to the conduction voltage drop VL of the light emitting element L. In combination with the voltage dividing function of the first capacitor C1 and the second capacitor C2, the voltage at the node A may also be increased to (Vch−Vcl)*C1/(C1+C2). Further, in combination with the coupling effect of the third capacitor C3, the change amount of the gate voltage Vg of the driving transistor T1 may be equal to the voltage change amount ΔVa at the node A in the light emitting stage t3 to the brightening stage t4, i.e., equal to (Vch−Vcl)*C1/(C1+C2)−[AVdata*C3/(C1+C2+C3)+ΔVs*C2/(C1+C2+C3)], That is, in the light emitting stage t3 to the brightening stage t4, the gate-source voltage Vgs between the gate G and the source S of the driving transistor T1 is increased somewhat to cause the driving current I flowing through the light emitting element L to be increased to the second current value I2, so that the source voltage Vs of the source S of the driving transistor T1 also slightly increased.
It may be understood that, in combination with the foregoing, the boost module 10 and the corresponding boost input signal CK are disposed in the present disclosure, so that the pixel driving circuit 100 has the “brightening stage” mentioned above. Further, the first capacitor C1 and the second capacitor C2 are disposed to perform the voltage dividing function, and the third capacitor C3 is disposed to achieve a coupling effect, so that, in the “brightening stage”, the gate voltage Vg of the gate G of the driving transistor T1 is increased, so that the gate-source voltage Vgs between the gate G and the source S of the driving transistor T1 is increased. Therefore, the driving current I flowing through the light emitting element L is also increased, thereby improving the light emitting brightness of the light emitting element L, and thus improving the brightness of the display panel.
It should be noted that, after the brightening stage t4 of the frame, even if the boost input signal CK is maintained at the high potential for a time period to implement another function for another component to which the boost input signal CK is loaded, that is, to improve a multiplexing rate of the boost input signal CK, the second boost control signal (e.g., the light emitting control signal EM) being configured to be equal to a corresponding low potential may control the second boost transistor T3 to be turned off, so that the node A is floated, so as to terminate modulation of the gate voltage Vg of the gate G of the driving transistor T1. In addition, in combination with the foregoing, in the reset stage t1, the data writing stage t2, and the light emitting stage t3 in certain frame, because no voltage change of the node A is required to modulate the gate voltage Vg of the gate G of the driving transistor T1, the second boost control signal (e.g., the light emitting control signal EM) may also be the low voltage in the reset stage t1 and the data writing stage t2 to control the second boost transistor T3 to be turned off in order to save energy.
Similarly, based on the circuit diagram shown in
An embodiment of the present disclosure provides a display panel including a plurality of the pixel driving circuits 100 according to any of the foregoing as shown in
In an embodiment, as shown in
In an embodiment, compared with the pixel driving circuit 100 close to the data generation chip, the voltage value of the data signal, Data, for the pixel driving circuit 100 away from the data generation chip has a larger absolute value. It should be noted that the data generation chip is disposed close to at least one side of the plurality of pixel driving circuits 100, that is, the distance of each of the plurality of pixel driving circuits 100 from the data generation chip is different, resulting in a different degree of attenuation of the data signals, Data, received by the pixel driving circuits 100 at different positions. For example, the data signal, Data, loaded to each of the data lines is the same, resulting in a difference in the magnitude of the voltage of the data signals, Data, finally loaded to the pixel driving circuits 100 at different positions and affecting image display uniformity.
It may be understood in the embodiment that, compared with the pixel driving circuit 100 close to the data generation chip, the received data signal, Data, for the pixel driving circuit 100 away from the data generation chip is attenuated larger. Moreover, the voltage value of the data signal, Data, loaded by the pixel driving circuit 100 away from the data generation chip is configured to be a larger absolute value in the embodiment, so as to compensate for too large data signal, Data, due to the larger distance from the data generation chip. Therefore, the difference in attenuation of the data signals, Data, loaded by the pixel driving circuits 100 at different positions is reduced, thereby improving image display uniformity of the display panel.
In an embodiment, as shown in
Specifically, the signal generation chip and the data generation chip may be installed to either a non-display area of a front surface or a back surface of the display panel by using, but not limited to, a COF (Chip On Film), a COG (Chip On Glass), a COP (Chip On Pi), or other packaging technologies. Both the signal generation chip and the data generation chip may be disposed close to at least one side of the plurality of the pixel driving circuits 100, that is, a distance of each of the plurality of the pixel driving circuits 100 at different positions from the signal generation chip may be different, and a distance of each of the plurality of the pixel driving circuits 100 at different positions from the data generation chip may be also different. It should be noted that, in combination with the foregoing, the distance of each of the pixel driving circuits 100 at different positions from the data generation chip is different, which may cause data signals, Data, received by the pixel driving circuits 100 at different locations to be attenuated to different degrees. For example, the data signal, Data, finally loaded to each of the data lines is the same, so that magnitudes of the voltages of the data signals, Data, finally loaded to the pixel driving circuits 100 at different locations are different, which affects image display uniformity. The data signals, Data, are attenuated to different degrees, which may also cause corresponding first voltages to have different magnitudes.
It may be understood in the embodiment that, compared with the pixel driving circuit 100 close to the data generation chip, the received data signal, Data, for the pixel driving circuit 100 away from the data generation chip is attenuated larger. Moreover, in the embodiment, the boost input signal CK loaded by the pixel driving circuit 100 away from the data generation chip is configured as follows: a difference between the second boost input voltage Vch and the first boost input voltage Vcl is larger, that is, a change value ΔVa (which is positively correlated with (Vch−Vcl)) of the voltage at the node A may be also larger, so as to compensate for a loss of too small first brightness caused by too small first voltage due to the larger distance from the data generation chip. By setting larger ΔVa, a difference of difference values between the second voltage and the first voltage in the pixel driving circuit 100 in different positions is reduced, so that a difference between the second brightness of the light emitting elements L at different positions may be smaller, thereby improving uniformity of a display image on the display panel.
The present disclosure provides the pixel driving circuit and the display panel, including: the driving transistor connected in series with the light emitting element between the first power supply line and the second power supply line, wherein the source of the driving transistor is electrically connected to the light emitting element; the data transistor, wherein the source of the data transistor is electrically connected to the data line, the drain of the data transistor is electrically connected to the gate of the driving transistor, and the gate of the data transistor is loaded with the data control signal; and the boost module, wherein the input terminal of the boost module is configured to load the boost input signal, and the output terminal of the boost module is electrically connected to the gate of the driving transistor; where the boost module controls the voltage of the gate of the driving transistor to boost from the first voltage in the first stage to the second voltage in the second stage, the second stage is later than the first stage, and the driving transistor is configured to generate the driving current based at least on the second voltage to drive the light emitting element to emit light; where the boost module includes: the first capacitor, where the first electrode plate of the first capacitor is electrically connected to the input terminal of the boost module to be loaded with the boost input signal; the second capacitor, where the first electrode plate of the second capacitor is loaded with the first signal; and the third capacitor, wherein the first electrode plate of the third capacitor is electrically connected to the gate of the driving transistor to serve as the output terminal of the boost module, and all of the second electrode plate of the first capacitor, the second electrode plate of the second capacitor, and the second electrode plate of the third capacitor are electrically connected to the same node. In the present disclosure, by disposing the boost module of which the input terminal is loaded with the boost input signal and the output terminal is electrically connected to the gate of the driving transistor through the first capacitor, the second capacitor, and the third capacitor forming a “T” type network, in combination with a voltage dividing function of the first capacitor and the second capacitor as well as a coupling effect of the third capacitor by the first capacitor to change a voltage at the node related to the gate voltage of the driving transistor, the gate voltage of the driving transistor can be modulated by being boosted from the first voltage to the second voltage, so as to increase the driving current flowing through the light emitting element, thereby improving light emitting brightness of the light emitting element, and thus improving brightness of the display panel.
The pixel driving circuit and the display panel provided in the embodiments of the present disclosure are described in detail above. In this specification, principles and implementations of the present disclosure are illustrated by applying specific examples herein. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present disclosure; those of ordinary skill in the art should understand that it is still possible to modify the technical solutions recorded in the foregoing embodiments, and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202210615768.4 | May 2022 | CN | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2022/101301 | 6/24/2022 | WO |
